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https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
improving block rams inference with registered read address.
This commit is contained in:
Blaise Tine
parent
ee96d4334b
commit
f49084b298
2 changed files with 121 additions and 40 deletions
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@ -19,6 +19,7 @@ module VX_dp_ram #(
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parameter SIZE = 1,
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parameter WRENW = 1,
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parameter OUT_REG = 0,
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parameter RADDR_REG = 0,
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parameter LUTRAM = 0,
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parameter NO_RWCHECK = 0,
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parameter RW_ASSERT = 0,
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@ -57,8 +58,7 @@ module VX_dp_ram #(
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`UNUSED_PARAM (RW_ASSERT)
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`UNUSED_VAR (read)
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`RUNTIME_ASSERT((((WRENW == 1) ) || ~write) || (| wren), ("%t: invalid write enable mask", $time))
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`UNUSED_VAR (wren)
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if (OUT_REG && !READ_ENABLE) begin : g_out_reg
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`UNUSED_PARAM (NO_RWCHECK)
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@ -78,7 +78,7 @@ module VX_dp_ram #(
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end
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end
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if (RESET_OUT && reset) begin
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rdata_r <= '0;
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rdata_r <= INIT_VALUE;
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end else begin
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rdata_r <= ram[raddr];
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end
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@ -96,7 +96,7 @@ module VX_dp_ram #(
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end
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end
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if (RESET_OUT && reset) begin
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rdata_r <= '0;
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rdata_r <= INIT_VALUE;
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end else begin
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rdata_r <= ram[raddr];
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end
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@ -104,7 +104,7 @@ module VX_dp_ram #(
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end
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end
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`else
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// default synthesis
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// Not Quartus
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if (LUTRAM != 0) begin : g_lutram
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`USE_FAST_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
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`RAM_INITIALIZATION
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@ -117,7 +117,7 @@ module VX_dp_ram #(
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end
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end
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if (RESET_OUT && reset) begin
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rdata_r <= '0;
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rdata_r <= INIT_VALUE;
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end else begin
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rdata_r <= ram[raddr];
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end
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@ -135,7 +135,7 @@ module VX_dp_ram #(
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end
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end
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if (RESET_OUT && reset) begin
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rdata_r <= '0;
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rdata_r <= INIT_VALUE;
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end else begin
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rdata_r <= ram[raddr];
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end
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@ -152,7 +152,7 @@ module VX_dp_ram #(
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if (write)
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ram[waddr] <= wdata;
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if (RESET_OUT && reset) begin
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rdata_r <= '0;
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rdata_r <= INIT_VALUE;
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end else begin
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rdata_r <= ram[raddr];
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end
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@ -167,7 +167,7 @@ module VX_dp_ram #(
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if (write)
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ram[waddr] <= wdata;
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if (RESET_OUT && reset) begin
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rdata_r <= '0;
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rdata_r <= INIT_VALUE;
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end else begin
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rdata_r <= ram[raddr];
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end
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@ -179,6 +179,7 @@ module VX_dp_ram #(
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end else begin : g_no_out_reg
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// OUT_REG==0 || READ_ENABLE=1
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wire [DATAW-1:0] rdata_w;
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reg [ADDRW-1:0] raddr_reg;
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`ifdef SYNTHESIS
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if (WRENW > 1) begin : g_writeen
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`ifdef QUARTUS
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@ -192,8 +193,16 @@ module VX_dp_ram #(
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ram[waddr][i] <= wdata[i * WSELW +: WSELW];
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end
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end
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if (read) begin
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raddr_reg <= raddr;
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end
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end
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if (RADDR_REG != 0) begin : g_rdata_async
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assign rdata_w = ram[raddr_reg];
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end else begin : g_rdata_sync
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assign rdata_w = ram[raddr];
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`UNUSED_VAR (raddr_reg)
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end
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assign rdata_w = ram[raddr];
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end else begin : g_no_lutram
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if (NO_RWCHECK != 0) begin : g_no_rwcheck
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`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
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@ -205,8 +214,16 @@ module VX_dp_ram #(
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ram[waddr][i] <= wdata[i * WSELW +: WSELW];
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end
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end
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if (read) begin
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raddr_reg <= raddr;
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end
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end
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if (RADDR_REG != 0) begin : g_rdata_async
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assign rdata_w = ram[raddr_reg];
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end else begin : g_rdata_sync
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assign rdata_w = ram[raddr];
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`UNUSED_VAR (raddr_reg)
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end
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assign rdata_w = ram[raddr];
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end else begin : g_rwcheck
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reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
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`RAM_INITIALIZATION
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@ -217,8 +234,16 @@ module VX_dp_ram #(
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ram[waddr][i] <= wdata[i * WSELW +: WSELW];
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end
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end
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if (read) begin
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raddr_reg <= raddr;
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end
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end
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if (RADDR_REG != 0) begin : g_rdata_async
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assign rdata_w = ram[raddr_reg];
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end else begin : g_rdata_sync
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assign rdata_w = ram[raddr];
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`UNUSED_VAR (raddr_reg)
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end
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assign rdata_w = ram[raddr];
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end
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end
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`else
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@ -233,8 +258,16 @@ module VX_dp_ram #(
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ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
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end
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end
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if (read) begin
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raddr_reg <= raddr;
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end
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end
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if (RADDR_REG != 0) begin : g_rdata_async
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assign rdata_w = ram[raddr_reg];
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end else begin : g_rdata_sync
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assign rdata_w = ram[raddr];
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`UNUSED_VAR (raddr_reg)
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end
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assign rdata_w = ram[raddr];
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end else begin : g_no_lutram
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if (NO_RWCHECK != 0) begin : g_no_rwcheck
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`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1];
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@ -246,8 +279,16 @@ module VX_dp_ram #(
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ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
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end
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end
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if (read) begin
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raddr_reg <= raddr;
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end
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end
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if (RADDR_REG != 0) begin : g_rdata_async
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assign rdata_w = ram[raddr_reg];
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end else begin : g_rdata_sync
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assign rdata_w = ram[raddr];
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`UNUSED_VAR (raddr_reg)
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end
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assign rdata_w = ram[raddr];
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end else begin : g_rwcheck
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reg [DATAW-1:0] ram [0:SIZE-1];
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`RAM_INITIALIZATION
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@ -258,8 +299,16 @@ module VX_dp_ram #(
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ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
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end
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end
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if (read) begin
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raddr_reg <= raddr;
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end
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end
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if (RADDR_REG != 0) begin : g_rdata_async
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assign rdata_w = ram[raddr_reg];
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end else begin : g_rdata_sync
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assign rdata_w = ram[raddr];
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`UNUSED_VAR (raddr_reg)
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end
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assign rdata_w = ram[raddr];
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end
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end
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`endif
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@ -272,8 +321,16 @@ module VX_dp_ram #(
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if (write) begin
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ram[waddr] <= wdata;
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end
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if (read) begin
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raddr_reg <= raddr;
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end
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end
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if (RADDR_REG != 0) begin : g_rdata_async
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assign rdata_w = ram[raddr_reg];
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end else begin : g_rdata_sync
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assign rdata_w = ram[raddr];
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`UNUSED_VAR (raddr_reg)
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end
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assign rdata_w = ram[raddr];
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end else begin : g_no_lutram
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if (NO_RWCHECK != 0) begin : g_no_rwcheck
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`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1];
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@ -282,8 +339,16 @@ module VX_dp_ram #(
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if (write) begin
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ram[waddr] <= wdata;
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end
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if (read) begin
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raddr_reg <= raddr;
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end
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end
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if (RADDR_REG != 0) begin : g_rdata_async
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assign rdata_w = ram[raddr_reg];
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end else begin : g_rdata_sync
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assign rdata_w = ram[raddr];
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`UNUSED_VAR (raddr_reg)
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end
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assign rdata_w = ram[raddr];
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end else begin : g_rwcheck
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reg [DATAW-1:0] ram [0:SIZE-1];
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`RAM_INITIALIZATION
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@ -291,8 +356,16 @@ module VX_dp_ram #(
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if (write) begin
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ram[waddr] <= wdata;
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end
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if (read) begin
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raddr_reg <= raddr;
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end
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end
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if (RADDR_REG != 0) begin : g_rdata_async
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assign rdata_w = ram[raddr_reg];
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end else begin : g_rdata_sync
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assign rdata_w = ram[raddr];
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`UNUSED_VAR (raddr_reg)
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end
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assign rdata_w = ram[raddr];
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end
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end
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end
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@ -316,39 +389,46 @@ module VX_dp_ram #(
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ram[waddr] <= ram_n;
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end
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end
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if (read) begin
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raddr_reg <= raddr;
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end
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end
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if (!LUTRAM && NO_RWCHECK) begin : g_rdata_no_bypass
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reg [DATAW-1:0] prev_data;
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reg [ADDRW-1:0] prev_waddr;
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reg prev_write;
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if (RADDR_REG != 0) begin : g_rdata_async
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assign rdata_w = ram[raddr_reg];
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end else begin : g_rdata_sync
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`UNUSED_VAR (raddr_reg)
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if (!LUTRAM && NO_RWCHECK) begin : g_rdata_no_bypass
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reg [DATAW-1:0] prev_data;
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reg [ADDRW-1:0] prev_waddr;
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reg prev_write;
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always @(posedge clk) begin
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if (reset) begin
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prev_write <= 0;
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prev_data <= '0;
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prev_waddr <= '0;
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end else begin
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prev_write <= write;
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prev_data <= ram[waddr];
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prev_waddr <= waddr;
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always @(posedge clk) begin
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if (reset) begin
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prev_write <= 0;
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prev_data <= '0;
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prev_waddr <= '0;
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end else begin
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prev_write <= write;
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prev_data <= ram[waddr];
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prev_waddr <= waddr;
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end
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end
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end
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assign rdata_w = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr];
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if (RW_ASSERT) begin : g_rw_assert
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`RUNTIME_ASSERT(~read || (rdata_w == ram[raddr]), ("%t: read after write hazard", $time))
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assign rdata_w = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr];
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if (RW_ASSERT) begin : g_rw_assert
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`RUNTIME_ASSERT(~read || (rdata_w == ram[raddr]), ("%t: read after write hazard", $time))
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end
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end else begin : g_rdata_with_bypass
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assign rdata_w = ram[raddr];
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end
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end else begin : g_rdata_with_bypass
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assign rdata_w = ram[raddr];
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end
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`endif
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if (OUT_REG != 0) begin : g_rdata_req
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reg [DATAW-1:0] rdata_r;
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always @(posedge clk) begin
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if (READ_ENABLE && reset) begin
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rdata_r <= '0;
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rdata_r <= INIT_VALUE;
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end else if (!READ_ENABLE || read) begin
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rdata_r <= rdata_w;
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end
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@ -357,7 +437,6 @@ module VX_dp_ram #(
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end else begin : g_rdata_comb
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assign rdata = rdata_w;
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end
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end
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endmodule
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@ -26,6 +26,7 @@ module VX_sp_ram #(
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parameter RESET_OUT = 0,
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parameter READ_ENABLE = 0,
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parameter INIT_ENABLE = 0,
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parameter RADDR_REG = 0,
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parameter INIT_FILE = "",
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parameter [DATAW-1:0] INIT_VALUE = 0,
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parameter ADDRW = `LOG2UP(SIZE)
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@ -44,6 +45,7 @@ module VX_sp_ram #(
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.SIZE (SIZE),
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.WRENW (WRENW),
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.OUT_REG (OUT_REG),
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.RADDR_REG (RADDR_REG),
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.LUTRAM (LUTRAM),
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.NO_RWCHECK (NO_RWCHECK),
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.RW_ASSERT (RW_ASSERT),
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