mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 05:47:35 -04:00
minor update
This commit is contained in:
parent
b677f724aa
commit
f575f16f57
3 changed files with 5 additions and 1 deletions
|
@ -55,7 +55,7 @@ module VX_csr_arb (
|
|||
assign csr_rsp_if.ready = select_io_rsp ? csr_io_rsp_tmp_if.ready : csr_commit_if.ready;
|
||||
|
||||
// Use skid buffer on CSR IO bus to stop backpressure delay propagation
|
||||
VX_elastic_buffer #(
|
||||
VX_skid_buffer #(
|
||||
.DATAW (32)
|
||||
) io_skid_buffer (
|
||||
.clk (clk),
|
||||
|
|
|
@ -7,10 +7,12 @@ module VX_opd_collect #(
|
|||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
input wire valid_in,
|
||||
output wire ready_in,
|
||||
input wire [INSTW-1:0] inst_in,
|
||||
input wire [OPDSW-1:0] opds_in,
|
||||
|
||||
output wire [INSTW+OPDSW-1:0] data_out,
|
||||
output wire valid_out,
|
||||
input wire ready_out
|
||||
|
|
|
@ -5,9 +5,11 @@ module VX_skid_buffer #(
|
|||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
input wire valid_in,
|
||||
output wire ready_in,
|
||||
input wire [DATAW-1:0] data_in,
|
||||
|
||||
output wire [DATAW-1:0] data_out,
|
||||
input wire ready_out,
|
||||
output wire valid_out
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue