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fixed cache sources name collision

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This commit is contained in:
Blaise Tine 2023-03-25 19:05:43 -04:00
parent 1433e553a0
commit f8e222708a
14 changed files with 28 additions and 28 deletions
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4
docs/cache_subsystem.md
View file

@ -40,9 +40,9 @@ VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/c
- Core Response Merge
- Cache accesses one line at a time. As a result, each request may not come back in the same response. This module tries to recombine the responses by thread ID.
### VX_bank.v
### VX_cache_bank.v
VX_bank.v is the verilog code that handles cache bank functionality and is located in the `/hw/rtl/cache` directory.
VX_cache_bank.v is the verilog code that handles cache bank functionality and is located in the `/hw/rtl/cache` directory.
![Image of Vortex Cache Bank](./assets/img/vortex_bank.png)

2
hw/rtl/VX_scope.vh
View file

@ -55,7 +55,7 @@
`define SCOPE_BIND_VX_core_issue
`define SCOPE_IO_VX_bank
`define SCOPE_IO_VX_cache_bank
`define SCOPE_IO_VX_cache

10
hw/rtl/cache/VX_cache.sv vendored
View file

@ -185,12 +185,12 @@ module VX_cache #(
`RESET_RELAY (init_reset, reset);
VX_init_ctrl #(
VX_cache_init #(
.CACHE_SIZE (CACHE_SIZE),
.LINE_SIZE (LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.NUM_WAYS (NUM_WAYS)
) init_ctrl (
) cache_init (
.clk (clk),
.reset (init_reset),
.addr_out (init_addr),
@ -237,7 +237,7 @@ module VX_cache #(
// Core request dispatch
VX_req_dispatch #(
VX_cache_req_dispatch #(
.LINE_SIZE (LINE_SIZE),
.WORD_SIZE (WORD_SIZE),
.ADDR_WIDTH (`WORD_ADDR_WIDTH),
@ -355,7 +355,7 @@ module VX_cache #(
`RESET_RELAY (bank_reset, reset);
VX_bank #(
VX_cache_bank #(
.BANK_ID (i),
.INSTANCE_ID (INSTANCE_ID),
.CACHE_SIZE (CACHE_SIZE),
@ -429,7 +429,7 @@ module VX_cache #(
// Core responce merge
VX_rsp_merge #(
VX_cache_rsp_merge #(
.NUM_REQS (NUM_REQS),
.NUM_BANKS (NUM_BANKS),
.NUM_PORTS (NUM_PORTS),

14
hw/rtl/cache/VX_bank.sv → hw/rtl/cache/VX_cache_bank.sv vendored
View file

@ -1,6 +1,6 @@
`include "VX_cache_define.vh"
module VX_bank #(
module VX_cache_bank #(
parameter `STRING_TYPE INSTANCE_ID= "",
parameter BANK_ID = 0,
@ -244,7 +244,7 @@ module VX_bank #(
wire [NUM_WAYS-1:0] way_sel_st0;
wire [NUM_WAYS-1:0] way_sel_st1;
VX_tag_access #(
VX_cache_tags #(
.INSTANCE_ID(INSTANCE_ID),
.BANK_ID (BANK_ID),
.CACHE_SIZE (CACHE_SIZE),
@ -253,7 +253,7 @@ module VX_bank #(
.NUM_WAYS (NUM_WAYS),
.WORD_SIZE (WORD_SIZE),
.UUID_WIDTH (UUID_WIDTH)
) tag_access (
) cache_tags (
.clk (clk),
.reset (reset),
@ -314,7 +314,7 @@ module VX_bank #(
wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] creq_data_st1 = wdata_st1[0 +: NUM_PORTS * `WORD_WIDTH];
`UNUSED_VAR (wdata_st1)
VX_data_access #(
VX_cache_data #(
.INSTANCE_ID (INSTANCE_ID),
.BANK_ID (BANK_ID),
.CACHE_SIZE (CACHE_SIZE),
@ -325,7 +325,7 @@ module VX_bank #(
.WORD_SIZE (WORD_SIZE),
.WRITE_ENABLE (WRITE_ENABLE),
.UUID_WIDTH (UUID_WIDTH)
) data_access (
) cache_data (
.clk (clk),
.reset (reset),
@ -366,7 +366,7 @@ module VX_bank #(
`RESET_RELAY (miss_resrv_reset, reset);
VX_miss_resrv #(
VX_cache_mshr #(
.INSTANCE_ID (INSTANCE_ID),
.BANK_ID (BANK_ID),
.LINE_SIZE (LINE_SIZE),
@ -377,7 +377,7 @@ module VX_bank #(
.MSHR_SIZE (MSHR_SIZE),
.UUID_WIDTH (UUID_WIDTH),
.TAG_WIDTH (TAG_WIDTH)
) miss_resrv (
) cache_mshr (
.clk (clk),
.reset (miss_resrv_reset),

2
hw/rtl/cache/VX_nc_bypass.sv → hw/rtl/cache/VX_cache_bypass.sv vendored
View file

@ -1,6 +1,6 @@
`include "VX_platform.vh"
module VX_nc_bypass #(
module VX_cache_bypass #(
parameter NUM_REQS = 1,
parameter NC_TAG_BIT = 0,

2
hw/rtl/cache/VX_data_access.sv → hw/rtl/cache/VX_cache_data.sv vendored
View file

@ -1,6 +1,6 @@
`include "VX_cache_define.vh"
module VX_data_access #(
module VX_cache_data #(
parameter `STRING_TYPE INSTANCE_ID= "",
parameter BANK_ID = 0,
// Size of cache in bytes

2
hw/rtl/cache/VX_init_ctrl.sv → hw/rtl/cache/VX_cache_init.sv vendored
View file

@ -1,6 +1,6 @@
`include "VX_cache_define.vh"
module VX_init_ctrl #(
module VX_cache_init #(
// Size of cache in bytes
parameter CACHE_SIZE = 16384,
// Size of line inside a bank in bytes

2
hw/rtl/cache/VX_miss_resrv.sv → hw/rtl/cache/VX_cache_mshr.sv vendored
View file

@ -1,6 +1,6 @@
`include "VX_cache_define.vh"
module VX_miss_resrv #(
module VX_cache_mshr #(
parameter `STRING_TYPE INSTANCE_ID= "",
parameter BANK_ID = 0,

2
hw/rtl/cache/VX_req_dispatch.sv → hw/rtl/cache/VX_cache_req_dispatch.sv vendored
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
module VX_req_dispatch #(
module VX_cache_req_dispatch #(
// Size of a line in bytes
parameter LINE_SIZE = 4,
// Size of a word in bytes

2
hw/rtl/cache/VX_rsp_merge.sv → hw/rtl/cache/VX_cache_rsp_merge.sv vendored
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
module VX_rsp_merge #(
module VX_cache_rsp_merge #(
// Number of Word requests per cycle
parameter NUM_REQS = 1,
// Number of banks

2
hw/rtl/cache/VX_tag_access.sv → hw/rtl/cache/VX_cache_tags.sv vendored
View file

@ -1,6 +1,6 @@
`include "VX_cache_define.vh"
module VX_tag_access #(
module VX_cache_tags #(
parameter `STRING_TYPE INSTANCE_ID = "",
parameter BANK_ID = 0,
// Size of cache in bytes

4
hw/rtl/cache/VX_cache_wrap.sv vendored
View file

@ -197,7 +197,7 @@ module VX_cache_wrap #(
`RESET_RELAY (nc_bypass_reset, reset);
VX_nc_bypass #(
VX_cache_bypass #(
.NUM_REQS (NUM_REQS),
.NC_TAG_BIT (NC_TAG_BIT),
@ -214,7 +214,7 @@ module VX_cache_wrap #(
.MEM_TAG_OUT_WIDTH (MEM_TAG_WIDTH),
.UUID_WIDTH (UUID_WIDTH)
) nc_bypass (
) cache_bypass (
.clk (clk),
.reset (nc_bypass_reset),

4
hw/rtl/cache/VX_shared_mem.sv vendored
View file

@ -68,7 +68,7 @@ module VX_shared_mem #(
wire [NUM_BANKS-1:0][`UP(REQ_SEL_BITS)-1:0] per_bank_req_idx_unqual;
wire [NUM_BANKS-1:0] per_bank_req_ready_unqual;
VX_req_dispatch #(
VX_cache_req_dispatch #(
.LINE_SIZE (WORD_SIZE),
.WORD_SIZE (WORD_SIZE),
.ADDR_WIDTH (ADDR_WIDTH),
@ -178,7 +178,7 @@ module VX_shared_mem #(
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] rsp_tag_s;
wire [NUM_REQS-1:0] rsp_ready_s;
VX_rsp_merge #(
VX_cache_rsp_merge #(
.NUM_REQS (NUM_REQS),
.NUM_BANKS (NUM_BANKS),
.NUM_PORTS (1),

4
hw/scripts/scope.json
View file

@ -86,10 +86,10 @@
},
"VX_cache": {
"submodules": {
"bank": {"type":"VX_bank", "count":"NUM_BANKS"}
"bank": {"type":"VX_cache_bank", "count":"NUM_BANKS"}
}
},
"VX_bank": {}
"VX_cache_bank": {}
},
"taps": {
"afu": {