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This commit is contained in:
felsabbagh3 2019-11-10 01:21:09 -05:00
parent ea7bd485ca
commit fbf708e419
192 changed files with 28093 additions and 368 deletions
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1
emulator/include/core.h
View file

@ -83,6 +83,7 @@ namespace Harp {
bool interrupt(Word r0);
bool running() const;
void step();
void printStats() const;

2
emulator/test_riscv.sh
View file

@ -1,4 +1,4 @@
echo start > results.txt
# echo ../kernel/vortex_test.hex
./harptool -E -a rv32i --core ../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug
./harptool -E -a rv32i --core ../runtime/mains/dev/vx_dev_main.hex -s -b 1> emulator.debug

8
rtl/VX_define.v
View file

@ -130,11 +130,7 @@
//Cache configurations
//Bytes
`define ICACHE_SIZE 1024
`ifdef SYN
`define ICACHE_WAYS 1
`else
`define ICACHE_WAYS 2
`endif
//Bytes
`define ICACHE_BLOCK 16
`define ICACHE_BANKS 1
@ -186,11 +182,7 @@
//Cache configurations
//Bytes
`define DCACHE_SIZE 4096
`ifdef SYN
`define DCACHE_WAYS 1
`else
`define DCACHE_WAYS 2
`endif
//Bytes
`define DCACHE_BLOCK 64

4
rtl/cache/VX_cache_bank_valid.v vendored
View file

@ -19,9 +19,9 @@ module VX_cache_bank_valid
for (t_id = 0; t_id < NUM_REQ; t_id = t_id + 1)
begin
if (NUMBER_BANKS != 1) begin
thread_track_banks[i_p_addr[t_id][2+LOG_NUM_BANKS-1:2]][t_id] = i_p_valid[t_id];
thread_track_banks[i_p_addr[t_id][2+LOG_NUM_BANKS-1:2]][t_id] = i_p_valid[t_id];
end else begin
thread_track_banks[t_id] = i_p_valid[t_id];
thread_track_banks[0][t_id] = i_p_valid[t_id];
end
end
end

2
rtl/cache/VX_d_cache.v vendored
View file

@ -243,7 +243,7 @@ module VX_d_cache
assign new_stored_valid = use_valid & (~threads_serviced_Qual);
wire update_global_way_to_evict = ((state == RECIV_MEM_RSP) && (new_state == CACHE_IDLE) && (CACHE_WAYS)) && (CACHE_WAYS > 1);
wire update_global_way_to_evict = ((state == RECIV_MEM_RSP) && (new_state == CACHE_IDLE)) && (CACHE_WAYS > 1);
///////////////////////////////////////////////////////////////////////
genvar cur_t;

4
rtl/modelsim/Makefile
View file

@ -112,8 +112,8 @@ comp:
sim: comp
# vsim vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log
vsim -novopt vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log
vsim vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log
# vsim -novopt vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log

2
rtl/modelsim/vortex_tb.v
View file

@ -87,7 +87,7 @@ reg out_ebreak;
initial begin
// $fdumpfile("vortex1.vcd");
load_file("../../runtime/mains/simple/vx_simple_main.hex");
load_file("../../runtime/mains/dev/vx_dev_main.hex");
//load_file("../../kernel/vortex_test.hex");
$dumpvars(0, vortex_tb);
reset = 1;

3
runtime/mains/dev/Makefile
View file

@ -1,6 +1,7 @@
COMP = /opt/riscv/bin/riscv32-unknown-elf-gcc
CC_FLAGS = -march=rv32im -mabi=ilp32 -O0 -Wl,-Bstatic,-T,linker.ld -ffreestanding -nostdlib
# CC_FLAGS = -march=rv32im -mabi=ilp32 -O0 -Wl,-Bstatic,-T,linker.ld -ffreestanding -nostdlib
CC_FLAGS = -march=rv32im -mabi=ilp32 -O0 -Wl,-Bstatic,-T,linker.ld -ffreestanding -nostartfiles
DMP = /opt/riscv/bin/riscv32-unknown-elf-objdump
CPY = /opt/riscv/bin/riscv32-unknown-elf-objcopy

56
runtime/mains/dev/vx_dev_main.c
View file

@ -4,6 +4,14 @@
#include "../../tests/tests.h"
#include "../../vx_api/vx_api.h"
// #include <utlist.h>
#include <string.h>
#include <unistd.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
typedef struct
{
unsigned * x;
@ -46,15 +54,32 @@ void mat_add_kernel(void * void_arguments)
__endif
}
void vx_print_mat(unsigned * matPtr, int numRows, int numCols)
{
vx_print_str("---------------------\n");
for (int i = 0; i < numRows; i++)
{
for (int j = 0; j < numCols; j++)
{
unsigned index = (i * numCols) + j;
vx_print_hex(matPtr[index]);
vx_print_str(" ");
}
vx_print_str("\n");
}
}
int main()
{
// Main is called with all threads active of warp 0
vx_tmc(1);
// void * hellp = malloc(4);
vx_print_str("Dev Main\n");
vx_print_str("vx_spawnWarps\n");
mat_add_args_t arguments;
arguments.x = x;
arguments.y = y;
@ -66,19 +91,26 @@ int main()
int numWarps = 4;
int numThreads = 4;
// First kernel call
vx_spawnWarps(numWarps, numThreads, mat_add_kernel, &arguments);
vx_print_mat(z, arguments.numRows, arguments.numColums);
for (int i = 0; i < arguments.numRows; i++)
{
for (int j = 0; j < arguments.numColums; j++)
{
unsigned index = (i * arguments.numColums) + j;
vx_print_hex(z[index]);
vx_print_str(" ");
}
vx_print_str("\n");
}
arguments.x = z;
arguments.y = y;
arguments.z = z;
arguments.numColums = 4;
arguments.numRows = 4;
// Second Kernel Call
vx_spawnWarps(numWarps, numThreads, mat_add_kernel, &arguments);
vx_print_mat(z, arguments.numRows, arguments.numColums);
return 0;
}
}

611
runtime/mains/dev/vx_dev_main.dump
View file

@ -10,7 +10,7 @@ Disassembly of section .text:
80000008: 00400513 li a0,4
8000000c: 00b5106b 0xb5106b
80000010: 010000ef jal ra,80000020 <vx_set_sp>
80000014: 748000ef jal ra,8000075c <main>
80000014: 011000ef jal ra,80000824 <main>
80000018: 00000513 li a0,0
8000001c: 0005006b 0x5006b
@ -114,7 +114,7 @@ Disassembly of section .text:
80000128: 810007b7 lui a5,0x81000
8000012c: fec42703 lw a4,-20(s0)
80000130: 00271713 slli a4,a4,0x2
80000134: 10c78793 addi a5,a5,268 # 8100010c <z+0xfffffe84>
80000134: 13478793 addi a5,a5,308 # 81000134 <z+0xfffffe84>
80000138: 00f707b3 add a5,a4,a5
8000013c: 0007a783 lw a5,0(a5)
80000140: 00078513 mv a0,a5
@ -137,7 +137,7 @@ Disassembly of section .text:
8000017c: fe842503 lw a0,-24(s0)
80000180: f95ff0ef jal ra,80000114 <vx_print_hex>
80000184: 810007b7 lui a5,0x81000
80000188: 04078513 addi a0,a5,64 # 81000040 <z+0xfffffdb8>
80000188: 04078513 addi a0,a5,64 # 81000040 <z+0xfffffd90>
8000018c: f4dff0ef jal ra,800000d8 <vx_print_str>
80000190: 00000013 nop
80000194: 01c12083 lw ra,28(sp)
@ -151,13 +151,13 @@ Disassembly of section .text:
800001ac: 00812c23 sw s0,24(sp)
800001b0: 02010413 addi s0,sp,32
800001b4: 810007b7 lui a5,0x81000
800001b8: 2647a783 lw a5,612(a5) # 81000264 <z+0xffffffdc>
800001b8: 28c7a783 lw a5,652(a5) # 8100028c <z+0xffffffdc>
800001bc: 00078513 mv a0,a5
800001c0: ea9ff0ef jal ra,80000068 <vx_tmc>
800001c4: 810007b7 lui a5,0x81000
800001c8: 2607a703 lw a4,608(a5) # 81000260 <z+0xffffffd8>
800001c8: 2887a703 lw a4,648(a5) # 81000288 <z+0xffffffd8>
800001cc: 810007b7 lui a5,0x81000
800001d0: 25c7a783 lw a5,604(a5) # 8100025c <z+0xffffffd4>
800001d0: 2847a783 lw a5,644(a5) # 81000284 <z+0xffffffd4>
800001d4: 00078513 mv a0,a5
800001d8: 000700e7 jalr a4
800001dc: eadff0ef jal ra,80000088 <vx_warpID>
@ -186,15 +186,15 @@ Disassembly of section .text:
80000230: fed42023 sw a3,-32(s0)
80000234: 810007b7 lui a5,0x81000
80000238: fe442703 lw a4,-28(s0)
8000023c: 26e7a023 sw a4,608(a5) # 81000260 <z+0xffffffd8>
8000023c: 28e7a423 sw a4,648(a5) # 81000288 <z+0xffffffd8>
80000240: 810007b7 lui a5,0x81000
80000244: fe042703 lw a4,-32(s0)
80000248: 24e7ae23 sw a4,604(a5) # 8100025c <z+0xffffffd4>
80000248: 28e7a223 sw a4,644(a5) # 81000284 <z+0xffffffd4>
8000024c: 810007b7 lui a5,0x81000
80000250: fe842703 lw a4,-24(s0)
80000254: 26e7a223 sw a4,612(a5) # 81000264 <z+0xffffffdc>
80000254: 28e7a623 sw a4,652(a5) # 8100028c <z+0xffffffdc>
80000258: 800007b7 lui a5,0x80000
8000025c: 1a478793 addi a5,a5,420 # 800001a4 <z+0xfeffff1c>
8000025c: 1a478793 addi a5,a5,420 # 800001a4 <z+0xfefffef4>
80000260: 00078593 mv a1,a5
80000264: fec42503 lw a0,-20(s0)
80000268: df9ff0ef jal ra,80000060 <vx_wspawn>
@ -211,7 +211,7 @@ Disassembly of section .text:
8000028c: 00812c23 sw s0,24(sp)
80000290: 02010413 addi s0,sp,32
80000294: 810007b7 lui a5,0x81000
80000298: 08478513 addi a0,a5,132 # 81000084 <z+0xfffffdfc>
80000298: 08478513 addi a0,a5,132 # 81000084 <z+0xfffffdd4>
8000029c: e3dff0ef jal ra,800000d8 <vx_print_str>
800002a0: 00400513 li a0,4
800002a4: dc5ff0ef jal ra,80000068 <vx_tmc>
@ -221,41 +221,41 @@ Disassembly of section .text:
800002b4: 810007b7 lui a5,0x81000
800002b8: fec42683 lw a3,-20(s0)
800002bc: 00269693 slli a3,a3,0x2
800002c0: 18c78793 addi a5,a5,396 # 8100018c <z+0xffffff04>
800002c0: 1b478793 addi a5,a5,436 # 810001b4 <z+0xffffff04>
800002c4: 00f687b3 add a5,a3,a5
800002c8: 00e7a023 sw a4,0(a5)
800002cc: 00100513 li a0,1
800002d0: d99ff0ef jal ra,80000068 <vx_tmc>
800002d4: 810007b7 lui a5,0x81000
800002d8: 18c7a783 lw a5,396(a5) # 8100018c <z+0xffffff04>
800002d8: 1b47a783 lw a5,436(a5) # 810001b4 <z+0xffffff04>
800002dc: 00078513 mv a0,a5
800002e0: e35ff0ef jal ra,80000114 <vx_print_hex>
800002e4: 810007b7 lui a5,0x81000
800002e8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
800002e8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
800002ec: dedff0ef jal ra,800000d8 <vx_print_str>
800002f0: 810007b7 lui a5,0x81000
800002f4: 18c78793 addi a5,a5,396 # 8100018c <z+0xffffff04>
800002f4: 1b478793 addi a5,a5,436 # 810001b4 <z+0xffffff04>
800002f8: 0047a783 lw a5,4(a5)
800002fc: 00078513 mv a0,a5
80000300: e15ff0ef jal ra,80000114 <vx_print_hex>
80000304: 810007b7 lui a5,0x81000
80000308: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
80000308: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
8000030c: dcdff0ef jal ra,800000d8 <vx_print_str>
80000310: 810007b7 lui a5,0x81000
80000314: 18c78793 addi a5,a5,396 # 8100018c <z+0xffffff04>
80000314: 1b478793 addi a5,a5,436 # 810001b4 <z+0xffffff04>
80000318: 0087a783 lw a5,8(a5)
8000031c: 00078513 mv a0,a5
80000320: df5ff0ef jal ra,80000114 <vx_print_hex>
80000324: 810007b7 lui a5,0x81000
80000328: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
80000328: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
8000032c: dadff0ef jal ra,800000d8 <vx_print_str>
80000330: 810007b7 lui a5,0x81000
80000334: 18c78793 addi a5,a5,396 # 8100018c <z+0xffffff04>
80000334: 1b478793 addi a5,a5,436 # 810001b4 <z+0xffffff04>
80000338: 00c7a783 lw a5,12(a5)
8000033c: 00078513 mv a0,a5
80000340: dd5ff0ef jal ra,80000114 <vx_print_hex>
80000344: 810007b7 lui a5,0x81000
80000348: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
80000348: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
8000034c: d8dff0ef jal ra,800000d8 <vx_print_str>
80000350: 00000013 nop
80000354: 01c12083 lw ra,28(sp)
@ -289,7 +289,7 @@ Disassembly of section .text:
800003bc: 810007b7 lui a5,0x81000
800003c0: fec42703 lw a4,-20(s0)
800003c4: 00271713 slli a4,a4,0x2
800003c8: 27878793 addi a5,a5,632 # 81000278 <z+0xfffffff0>
800003c8: 2a078793 addi a5,a5,672 # 810002a0 <z+0xfffffff0>
800003cc: 00f707b3 add a5,a4,a5
800003d0: 00a00713 li a4,10
800003d4: 00e7a023 sw a4,0(a5)
@ -297,7 +297,7 @@ Disassembly of section .text:
800003dc: 810007b7 lui a5,0x81000
800003e0: fec42703 lw a4,-20(s0)
800003e4: 00271713 slli a4,a4,0x2
800003e8: 27878793 addi a5,a5,632 # 81000278 <z+0xfffffff0>
800003e8: 2a078793 addi a5,a5,672 # 810002a0 <z+0xfffffff0>
800003ec: 00f707b3 add a5,a4,a5
800003f0: 00b00713 li a4,11
800003f4: 00e7a023 sw a4,0(a5)
@ -314,7 +314,7 @@ Disassembly of section .text:
80000420: 810007b7 lui a5,0x81000
80000424: fec42703 lw a4,-20(s0)
80000428: 00271713 slli a4,a4,0x2
8000042c: 27878793 addi a5,a5,632 # 81000278 <z+0xfffffff0>
8000042c: 2a078793 addi a5,a5,672 # 810002a0 <z+0xfffffff0>
80000430: 00f707b3 add a5,a4,a5
80000434: 00c00713 li a4,12
80000438: 00e7a023 sw a4,0(a5)
@ -322,42 +322,42 @@ Disassembly of section .text:
80000440: 810007b7 lui a5,0x81000
80000444: fec42703 lw a4,-20(s0)
80000448: 00271713 slli a4,a4,0x2
8000044c: 27878793 addi a5,a5,632 # 81000278 <z+0xfffffff0>
8000044c: 2a078793 addi a5,a5,672 # 810002a0 <z+0xfffffff0>
80000450: 00f707b3 add a5,a4,a5
80000454: 00d00713 li a4,13
80000458: 00e7a023 sw a4,0(a5)
8000045c: c25ff0ef jal ra,80000080 <vx_join>
80000460: c21ff0ef jal ra,80000080 <vx_join>
80000464: 810007b7 lui a5,0x81000
80000468: 2787a783 lw a5,632(a5) # 81000278 <z+0xfffffff0>
80000468: 2a07a783 lw a5,672(a5) # 810002a0 <z+0xfffffff0>
8000046c: 00078513 mv a0,a5
80000470: ca5ff0ef jal ra,80000114 <vx_print_hex>
80000474: 810007b7 lui a5,0x81000
80000478: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
80000478: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
8000047c: c5dff0ef jal ra,800000d8 <vx_print_str>
80000480: 810007b7 lui a5,0x81000
80000484: 27878793 addi a5,a5,632 # 81000278 <z+0xfffffff0>
80000484: 2a078793 addi a5,a5,672 # 810002a0 <z+0xfffffff0>
80000488: 0047a783 lw a5,4(a5)
8000048c: 00078513 mv a0,a5
80000490: c85ff0ef jal ra,80000114 <vx_print_hex>
80000494: 810007b7 lui a5,0x81000
80000498: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
80000498: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
8000049c: c3dff0ef jal ra,800000d8 <vx_print_str>
800004a0: 810007b7 lui a5,0x81000
800004a4: 27878793 addi a5,a5,632 # 81000278 <z+0xfffffff0>
800004a4: 2a078793 addi a5,a5,672 # 810002a0 <z+0xfffffff0>
800004a8: 0087a783 lw a5,8(a5)
800004ac: 00078513 mv a0,a5
800004b0: c65ff0ef jal ra,80000114 <vx_print_hex>
800004b4: 810007b7 lui a5,0x81000
800004b8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
800004b8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
800004bc: c1dff0ef jal ra,800000d8 <vx_print_str>
800004c0: 810007b7 lui a5,0x81000
800004c4: 27878793 addi a5,a5,632 # 81000278 <z+0xfffffff0>
800004c4: 2a078793 addi a5,a5,672 # 810002a0 <z+0xfffffff0>
800004c8: 00c7a783 lw a5,12(a5)
800004cc: 00078513 mv a0,a5
800004d0: c45ff0ef jal ra,80000114 <vx_print_hex>
800004d4: 810007b7 lui a5,0x81000
800004d8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
800004d8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
800004dc: bfdff0ef jal ra,800000d8 <vx_print_str>
800004e0: 00000013 nop
800004e4: 01c12083 lw ra,28(sp)
@ -375,7 +375,7 @@ Disassembly of section .text:
8000050c: 810007b7 lui a5,0x81000
80000510: fec42703 lw a4,-20(s0)
80000514: 00271713 slli a4,a4,0x2
80000518: 26878793 addi a5,a5,616 # 81000268 <z+0xffffffe0>
80000518: 29078793 addi a5,a5,656 # 81000290 <z+0xffffffe0>
8000051c: 00f707b3 add a5,a4,a5
80000520: fec42703 lw a4,-20(s0)
80000524: 00e7a023 sw a4,0(a5)
@ -395,42 +395,42 @@ Disassembly of section .text:
80000554: 00812c23 sw s0,24(sp)
80000558: 02010413 addi s0,sp,32
8000055c: 800007b7 lui a5,0x80000
80000560: 4f478793 addi a5,a5,1268 # 800004f4 <z+0xff00026c>
80000560: 4f478793 addi a5,a5,1268 # 800004f4 <z+0xff000244>
80000564: fef42623 sw a5,-20(s0)
80000568: fec42583 lw a1,-20(s0)
8000056c: 00400513 li a0,4
80000570: af1ff0ef jal ra,80000060 <vx_wspawn>
80000574: f81ff0ef jal ra,800004f4 <simple_kernel>
80000578: 810007b7 lui a5,0x81000
8000057c: 2687a783 lw a5,616(a5) # 81000268 <z+0xffffffe0>
8000057c: 2907a783 lw a5,656(a5) # 81000290 <z+0xffffffe0>
80000580: 00078513 mv a0,a5
80000584: b91ff0ef jal ra,80000114 <vx_print_hex>
80000588: 810007b7 lui a5,0x81000
8000058c: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
8000058c: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
80000590: b49ff0ef jal ra,800000d8 <vx_print_str>
80000594: 810007b7 lui a5,0x81000
80000598: 26878793 addi a5,a5,616 # 81000268 <z+0xffffffe0>
80000598: 29078793 addi a5,a5,656 # 81000290 <z+0xffffffe0>
8000059c: 0047a783 lw a5,4(a5)
800005a0: 00078513 mv a0,a5
800005a4: b71ff0ef jal ra,80000114 <vx_print_hex>
800005a8: 810007b7 lui a5,0x81000
800005ac: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
800005ac: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
800005b0: b29ff0ef jal ra,800000d8 <vx_print_str>
800005b4: 810007b7 lui a5,0x81000
800005b8: 26878793 addi a5,a5,616 # 81000268 <z+0xffffffe0>
800005b8: 29078793 addi a5,a5,656 # 81000290 <z+0xffffffe0>
800005bc: 0087a783 lw a5,8(a5)
800005c0: 00078513 mv a0,a5
800005c4: b51ff0ef jal ra,80000114 <vx_print_hex>
800005c8: 810007b7 lui a5,0x81000
800005cc: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
800005cc: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
800005d0: b09ff0ef jal ra,800000d8 <vx_print_str>
800005d4: 810007b7 lui a5,0x81000
800005d8: 26878793 addi a5,a5,616 # 81000268 <z+0xffffffe0>
800005d8: 29078793 addi a5,a5,656 # 81000290 <z+0xffffffe0>
800005dc: 00c7a783 lw a5,12(a5)
800005e0: 00078513 mv a0,a5
800005e4: b31ff0ef jal ra,80000114 <vx_print_hex>
800005e8: 810007b7 lui a5,0x81000
800005ec: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe0c>
800005ec: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffde4>
800005f0: ae9ff0ef jal ra,800000d8 <vx_print_str>
800005f4: 00000013 nop
800005f8: 01c12083 lw ra,28(sp)
@ -445,7 +445,7 @@ Disassembly of section .text:
80000614: 01010413 addi s0,sp,16
80000618: c6dff0ef jal ra,80000284 <test_tmc>
8000061c: 810007b7 lui a5,0x81000
80000620: 09878513 addi a0,a5,152 # 81000098 <z+0xfffffe10>
80000620: 09878513 addi a0,a5,152 # 81000098 <z+0xfffffde8>
80000624: ab5ff0ef jal ra,800000d8 <vx_print_str>
80000628: 00400513 li a0,4
8000062c: a3dff0ef jal ra,80000068 <vx_tmc>
@ -453,7 +453,7 @@ Disassembly of section .text:
80000634: 00100513 li a0,1
80000638: a31ff0ef jal ra,80000068 <vx_tmc>
8000063c: 810007b7 lui a5,0x81000
80000640: 0ac78513 addi a0,a5,172 # 810000ac <z+0xfffffe24>
80000640: 0ac78513 addi a0,a5,172 # 810000ac <z+0xfffffdfc>
80000644: a95ff0ef jal ra,800000d8 <vx_print_str>
80000648: f05ff0ef jal ra,8000054c <test_wsapwn>
8000064c: 00000013 nop
@ -527,83 +527,139 @@ Disassembly of section .text:
80000754: 04010113 addi sp,sp,64
80000758: 00008067 ret
8000075c <main>:
8000075c: fc010113 addi sp,sp,-64
80000760: 02112e23 sw ra,60(sp)
80000764: 02812c23 sw s0,56(sp)
80000768: 04010413 addi s0,sp,64
8000076c: 00100513 li a0,1
80000770: 8f9ff0ef jal ra,80000068 <vx_tmc>
80000774: 810007b7 lui a5,0x81000
80000778: 0f878513 addi a0,a5,248 # 810000f8 <z+0xfffffe70>
8000077c: 95dff0ef jal ra,800000d8 <vx_print_str>
80000780: 810007b7 lui a5,0x81000
80000784: 1dc78793 addi a5,a5,476 # 810001dc <z+0xffffff54>
80000788: fcf42423 sw a5,-56(s0)
8000078c: 810007b7 lui a5,0x81000
80000790: 21c78793 addi a5,a5,540 # 8100021c <z+0xffffff94>
80000794: fcf42623 sw a5,-52(s0)
80000798: 810007b7 lui a5,0x81000
8000079c: 28878793 addi a5,a5,648 # 81000288 <z+0x0>
800007a0: fcf42823 sw a5,-48(s0)
800007a4: 00400793 li a5,4
800007a8: fcf42a23 sw a5,-44(s0)
800007ac: 00400793 li a5,4
800007b0: fcf42c23 sw a5,-40(s0)
800007b4: 00400793 li a5,4
800007b8: fef42223 sw a5,-28(s0)
800007bc: 00400793 li a5,4
800007c0: fef42023 sw a5,-32(s0)
800007c4: fe442703 lw a4,-28(s0)
800007c8: fe042583 lw a1,-32(s0)
800007cc: fc840793 addi a5,s0,-56
800007d0: 00078693 mv a3,a5
800007d4: 800007b7 lui a5,0x80000
800007d8: 66078613 addi a2,a5,1632 # 80000660 <z+0xff0003d8>
800007dc: 00070513 mv a0,a4
800007e0: a35ff0ef jal ra,80000214 <vx_spawnWarps>
800007e4: fe042623 sw zero,-20(s0)
800007e8: 0800006f j 80000868 <main+0x10c>
800007ec: fe042423 sw zero,-24(s0)
800007f0: 0540006f j 80000844 <main+0xe8>
800007f4: fd442703 lw a4,-44(s0)
8000075c <vx_print_mat>:
8000075c: fd010113 addi sp,sp,-48
80000760: 02112623 sw ra,44(sp)
80000764: 02812423 sw s0,40(sp)
80000768: 03010413 addi s0,sp,48
8000076c: fca42e23 sw a0,-36(s0)
80000770: fcb42c23 sw a1,-40(s0)
80000774: fcc42a23 sw a2,-44(s0)
80000778: 810007b7 lui a5,0x81000
8000077c: 0f878513 addi a0,a5,248 # 810000f8 <z+0xfffffe48>
80000780: 959ff0ef jal ra,800000d8 <vx_print_str>
80000784: fe042623 sw zero,-20(s0)
80000788: 07c0006f j 80000804 <vx_print_mat+0xa8>
8000078c: fe042423 sw zero,-24(s0)
80000790: 0500006f j 800007e0 <vx_print_mat+0x84>
80000794: fec42703 lw a4,-20(s0)
80000798: fd442783 lw a5,-44(s0)
8000079c: 02f70733 mul a4,a4,a5
800007a0: fe842783 lw a5,-24(s0)
800007a4: 00f707b3 add a5,a4,a5
800007a8: fef42223 sw a5,-28(s0)
800007ac: fe442783 lw a5,-28(s0)
800007b0: 00279793 slli a5,a5,0x2
800007b4: fdc42703 lw a4,-36(s0)
800007b8: 00f707b3 add a5,a4,a5
800007bc: 0007a783 lw a5,0(a5)
800007c0: 00078513 mv a0,a5
800007c4: 951ff0ef jal ra,80000114 <vx_print_hex>
800007c8: 810007b7 lui a5,0x81000
800007cc: 11078513 addi a0,a5,272 # 81000110 <z+0xfffffe60>
800007d0: 909ff0ef jal ra,800000d8 <vx_print_str>
800007d4: fe842783 lw a5,-24(s0)
800007d8: 00178793 addi a5,a5,1
800007dc: fef42423 sw a5,-24(s0)
800007e0: fe842703 lw a4,-24(s0)
800007e4: fd442783 lw a5,-44(s0)
800007e8: faf746e3 blt a4,a5,80000794 <vx_print_mat+0x38>
800007ec: 810007b7 lui a5,0x81000
800007f0: 11478513 addi a0,a5,276 # 81000114 <z+0xfffffe64>
800007f4: 8e5ff0ef jal ra,800000d8 <vx_print_str>
800007f8: fec42783 lw a5,-20(s0)
800007fc: 02f70733 mul a4,a4,a5
80000800: fe842783 lw a5,-24(s0)
80000804: 00f707b3 add a5,a4,a5
80000808: fcf42e23 sw a5,-36(s0)
8000080c: 810007b7 lui a5,0x81000
80000810: fdc42703 lw a4,-36(s0)
80000814: 00271713 slli a4,a4,0x2
80000818: 28878793 addi a5,a5,648 # 81000288 <z+0x0>
8000081c: 00f707b3 add a5,a4,a5
80000820: 0007a783 lw a5,0(a5)
80000824: 00078513 mv a0,a5
80000828: 8edff0ef jal ra,80000114 <vx_print_hex>
8000082c: 810007b7 lui a5,0x81000
80000830: 10478513 addi a0,a5,260 # 81000104 <z+0xfffffe7c>
80000834: 8a5ff0ef jal ra,800000d8 <vx_print_str>
80000838: fe842783 lw a5,-24(s0)
8000083c: 00178793 addi a5,a5,1
80000840: fef42423 sw a5,-24(s0)
80000844: fd442703 lw a4,-44(s0)
80000848: fe842783 lw a5,-24(s0)
8000084c: fae7e4e3 bltu a5,a4,800007f4 <main+0x98>
80000850: 810007b7 lui a5,0x81000
80000854: 10878513 addi a0,a5,264 # 81000108 <z+0xfffffe80>
80000858: 881ff0ef jal ra,800000d8 <vx_print_str>
8000085c: fec42783 lw a5,-20(s0)
80000860: 00178793 addi a5,a5,1
80000864: fef42623 sw a5,-20(s0)
80000868: fd842703 lw a4,-40(s0)
8000086c: fec42783 lw a5,-20(s0)
80000870: f6e7eee3 bltu a5,a4,800007ec <main+0x90>
80000874: 00000793 li a5,0
80000878: 00078513 mv a0,a5
8000087c: 03c12083 lw ra,60(sp)
80000880: 03812403 lw s0,56(sp)
80000884: 04010113 addi sp,sp,64
80000888: 00008067 ret
800007fc: 00178793 addi a5,a5,1
80000800: fef42623 sw a5,-20(s0)
80000804: fec42703 lw a4,-20(s0)
80000808: fd842783 lw a5,-40(s0)
8000080c: f8f740e3 blt a4,a5,8000078c <vx_print_mat+0x30>
80000810: 00000013 nop
80000814: 02c12083 lw ra,44(sp)
80000818: 02812403 lw s0,40(sp)
8000081c: 03010113 addi sp,sp,48
80000820: 00008067 ret
80000824 <main>:
80000824: fd010113 addi sp,sp,-48
80000828: 02112623 sw ra,44(sp)
8000082c: 02812423 sw s0,40(sp)
80000830: 03010413 addi s0,sp,48
80000834: 00100513 li a0,1
80000838: 831ff0ef jal ra,80000068 <vx_tmc>
8000083c: 810007b7 lui a5,0x81000
80000840: 11878513 addi a0,a5,280 # 81000118 <z+0xfffffe68>
80000844: 895ff0ef jal ra,800000d8 <vx_print_str>
80000848: 810007b7 lui a5,0x81000
8000084c: 12478513 addi a0,a5,292 # 81000124 <z+0xfffffe74>
80000850: 889ff0ef jal ra,800000d8 <vx_print_str>
80000854: 810007b7 lui a5,0x81000
80000858: 20478793 addi a5,a5,516 # 81000204 <z+0xffffff54>
8000085c: fcf42a23 sw a5,-44(s0)
80000860: 810007b7 lui a5,0x81000
80000864: 24478793 addi a5,a5,580 # 81000244 <z+0xffffff94>
80000868: fcf42c23 sw a5,-40(s0)
8000086c: 810007b7 lui a5,0x81000
80000870: 2b078793 addi a5,a5,688 # 810002b0 <z+0x0>
80000874: fcf42e23 sw a5,-36(s0)
80000878: 00400793 li a5,4
8000087c: fef42023 sw a5,-32(s0)
80000880: 00400793 li a5,4
80000884: fef42223 sw a5,-28(s0)
80000888: 00400793 li a5,4
8000088c: fef42623 sw a5,-20(s0)
80000890: 00400793 li a5,4
80000894: fef42423 sw a5,-24(s0)
80000898: fec42703 lw a4,-20(s0)
8000089c: fe842583 lw a1,-24(s0)
800008a0: fd440793 addi a5,s0,-44
800008a4: 00078693 mv a3,a5
800008a8: 800007b7 lui a5,0x80000
800008ac: 66078613 addi a2,a5,1632 # 80000660 <z+0xff0003b0>
800008b0: 00070513 mv a0,a4
800008b4: 961ff0ef jal ra,80000214 <vx_spawnWarps>
800008b8: fe442783 lw a5,-28(s0)
800008bc: 00078713 mv a4,a5
800008c0: fe042783 lw a5,-32(s0)
800008c4: 00078613 mv a2,a5
800008c8: 00070593 mv a1,a4
800008cc: 810007b7 lui a5,0x81000
800008d0: 2b078513 addi a0,a5,688 # 810002b0 <z+0x0>
800008d4: e89ff0ef jal ra,8000075c <vx_print_mat>
800008d8: 810007b7 lui a5,0x81000
800008dc: 2b078793 addi a5,a5,688 # 810002b0 <z+0x0>
800008e0: fcf42a23 sw a5,-44(s0)
800008e4: 810007b7 lui a5,0x81000
800008e8: 24478793 addi a5,a5,580 # 81000244 <z+0xffffff94>
800008ec: fcf42c23 sw a5,-40(s0)
800008f0: 810007b7 lui a5,0x81000
800008f4: 2b078793 addi a5,a5,688 # 810002b0 <z+0x0>
800008f8: fcf42e23 sw a5,-36(s0)
800008fc: 00400793 li a5,4
80000900: fef42023 sw a5,-32(s0)
80000904: 00400793 li a5,4
80000908: fef42223 sw a5,-28(s0)
8000090c: fec42703 lw a4,-20(s0)
80000910: fe842583 lw a1,-24(s0)
80000914: fd440793 addi a5,s0,-44
80000918: 00078693 mv a3,a5
8000091c: 800007b7 lui a5,0x80000
80000920: 66078613 addi a2,a5,1632 # 80000660 <z+0xff0003b0>
80000924: 00070513 mv a0,a4
80000928: 8edff0ef jal ra,80000214 <vx_spawnWarps>
8000092c: fe442783 lw a5,-28(s0)
80000930: 00078713 mv a4,a5
80000934: fe042783 lw a5,-32(s0)
80000938: 00078613 mv a2,a5
8000093c: 00070593 mv a1,a4
80000940: 810007b7 lui a5,0x81000
80000944: 2b078513 addi a0,a5,688 # 810002b0 <z+0x0>
80000948: e15ff0ef jal ra,8000075c <vx_print_mat>
8000094c: 00000793 li a5,0
80000950: 00078513 mv a0,a5
80000954: 02c12083 lw ra,44(sp)
80000958: 02812403 lw s0,40(sp)
8000095c: 03010113 addi sp,sp,48
80000960: 00008067 ret
Disassembly of section .rodata:
@ -630,7 +686,7 @@ Disassembly of section .rodata:
8100002a: 0000 unimp
8100002c: 0062 c.slli zero,0x18
8100002e: 0000 unimp
81000030: 00000063 beqz zero,81000030 <main+0xfff8d4>
81000030: 00000063 beqz zero,81000030 <main+0xfff80c>
81000034: 0064 addi s1,sp,12
81000036: 0000 unimp
81000038: 0065 c.nop 25
@ -661,7 +717,7 @@ Disassembly of section .rodata:
8100006e: 0000 unimp
81000070: 0062 c.slli zero,0x18
81000072: 0000 unimp
81000074: 00000063 beqz zero,81000074 <main+0xfff918>
81000074: 00000063 beqz zero,81000074 <main+0xfff850>
81000078: 0064 addi s1,sp,12
8100007a: 0000 unimp
8100007c: 0065 c.nop 25
@ -671,7 +727,7 @@ Disassembly of section .rodata:
81000084: 6574 flw fa3,76(a0)
81000086: 6e697473 csrrci s0,0x6e6,18
8100008a: 6d745f67 0x6d745f67
8100008e: 00000a63 beqz zero,810000a2 <main+0xfff946>
8100008e: 00000a63 beqz zero,810000a2 <main+0xfff87e>
81000092: 0000 unimp
81000094: 000a c.slli zero,0x2
81000096: 0000 unimp
@ -709,188 +765,185 @@ Disassembly of section .rodata:
810000e2: 0000 unimp
810000e4: 0062 c.slli zero,0x18
810000e6: 0000 unimp
810000e8: 00000063 beqz zero,810000e8 <main+0xfff98c>
810000e8: 00000063 beqz zero,810000e8 <main+0xfff8c4>
810000ec: 0064 addi s1,sp,12
810000ee: 0000 unimp
810000f0: 0065 c.nop 25
810000f2: 0000 unimp
810000f4: 0066 c.slli zero,0x19
810000f6: 0000 unimp
810000f8: 6544 flw fs1,12(a0)
810000fa: 2076 fld ft0,344(sp)
810000fc: 614d addi sp,sp,176
810000fe: 6e69 lui t3,0x1a
81000100: 000a c.slli zero,0x2
81000102: 0000 unimp
81000104: 0020 addi s0,sp,8
81000106: 0000 unimp
81000108: 000a c.slli zero,0x2
810000f8: 2d2d jal 81000732 <z+0x482>
810000fa: 2d2d jal 81000734 <z+0x484>
810000fc: 2d2d jal 81000736 <z+0x486>
810000fe: 2d2d jal 81000738 <z+0x488>
81000100: 2d2d jal 8100073a <z+0x48a>
81000102: 2d2d jal 8100073c <z+0x48c>
81000104: 2d2d jal 8100073e <z+0x48e>
81000106: 2d2d jal 81000740 <z+0x490>
81000108: 2d2d jal 81000742 <z+0x492>
8100010a: 2d2d jal 81000744 <z+0x494>
8100010c: 0a2d addi s4,s4,11
8100010e: 0000 unimp
81000110: 0020 addi s0,sp,8
81000112: 0000 unimp
81000114: 000a c.slli zero,0x2
81000116: 0000 unimp
81000118: 6544 flw fs1,12(a0)
8100011a: 2076 fld ft0,344(sp)
8100011c: 614d addi sp,sp,176
8100011e: 6e69 lui t3,0x1a
81000120: 000a c.slli zero,0x2
81000122: 0000 unimp
81000124: 7876 flw fa6,124(sp)
81000126: 735f 6170 6e77 0x6e776170735f
8100012c: 70726157 0x70726157
81000130: 0xa73
Disassembly of section .data:
8100010c <hextoa>:
8100010c: 0000 unimp
8100010e: 8100 0x8100
81000110: 0004 0x4
81000112: 8100 0x8100
81000114: 0008 0x8
81000116: 8100 0x8100
81000118: 000c 0xc
8100011a: 8100 0x8100
8100011c: 0010 0x10
8100011e: 8100 0x8100
81000120: 0014 0x14
81000122: 8100 0x8100
81000124: 0018 0x18
81000126: 8100 0x8100
81000128: 001c 0x1c
8100012a: 8100 0x8100
8100012c: 0020 addi s0,sp,8
8100012e: 8100 0x8100
81000130: 0024 addi s1,sp,8
81000132: 8100 0x8100
81000134: 0028 addi a0,sp,8
81000134 <hextoa>:
81000134: 0000 unimp
81000136: 8100 0x8100
81000138: 002c addi a1,sp,8
81000138: 0004 0x4
8100013a: 8100 0x8100
8100013c: 0030 addi a2,sp,8
8100013c: 0008 0x8
8100013e: 8100 0x8100
81000140: 0034 addi a3,sp,8
81000140: 000c 0xc
81000142: 8100 0x8100
81000144: 0038 addi a4,sp,8
81000144: 0010 0x10
81000146: 8100 0x8100
81000148: 003c addi a5,sp,8
81000148: 0014 0x14
8100014a: 8100 0x8100
8100014c <hextoa>:
8100014c: 0044 addi s1,sp,4
8100014c: 0018 0x18
8100014e: 8100 0x8100
81000150: 0048 addi a0,sp,4
81000150: 001c 0x1c
81000152: 8100 0x8100
81000154: 004c addi a1,sp,4
81000154: 0020 addi s0,sp,8
81000156: 8100 0x8100
81000158: 0050 addi a2,sp,4
81000158: 0024 addi s1,sp,8
8100015a: 8100 0x8100
8100015c: 0054 addi a3,sp,4
8100015c: 0028 addi a0,sp,8
8100015e: 8100 0x8100
81000160: 0058 addi a4,sp,4
81000160: 002c addi a1,sp,8
81000162: 8100 0x8100
81000164: 005c addi a5,sp,4
81000164: 0030 addi a2,sp,8
81000166: 8100 0x8100
81000168: 0060 addi s0,sp,12
81000168: 0034 addi a3,sp,8
8100016a: 8100 0x8100
8100016c: 0064 addi s1,sp,12
8100016c: 0038 addi a4,sp,8
8100016e: 8100 0x8100
81000170: 0068 addi a0,sp,12
81000170: 003c addi a5,sp,8
81000172: 8100 0x8100
81000174: 006c addi a1,sp,12
81000174 <hextoa>:
81000174: 0044 addi s1,sp,4
81000176: 8100 0x8100
81000178: 0070 addi a2,sp,12
81000178: 0048 addi a0,sp,4
8100017a: 8100 0x8100
8100017c: 0074 addi a3,sp,12
8100017c: 004c addi a1,sp,4
8100017e: 8100 0x8100
81000180: 0078 addi a4,sp,12
81000180: 0050 addi a2,sp,4
81000182: 8100 0x8100
81000184: 007c addi a5,sp,12
81000184: 0054 addi a3,sp,4
81000186: 8100 0x8100
81000188: 0080 addi s0,sp,64
81000188: 0058 addi a4,sp,4
8100018a: 8100 0x8100
8100018c <tmc_array>:
8100018c: 0005 c.nop 1
8100018e: 0000 unimp
81000190: 0005 c.nop 1
81000192: 0000 unimp
81000194: 0005 c.nop 1
81000196: 0000 unimp
81000198: 0005 c.nop 1
...
8100019c <hextoa>:
8100019c: 00b8 addi a4,sp,72
8100018c: 005c addi a5,sp,4
8100018e: 8100 0x8100
81000190: 0060 addi s0,sp,12
81000192: 8100 0x8100
81000194: 0064 addi s1,sp,12
81000196: 8100 0x8100
81000198: 0068 addi a0,sp,12
8100019a: 8100 0x8100
8100019c: 006c addi a1,sp,12
8100019e: 8100 0x8100
810001a0: 00bc addi a5,sp,72
810001a0: 0070 addi a2,sp,12
810001a2: 8100 0x8100
810001a4: 00c0 addi s0,sp,68
810001a4: 0074 addi a3,sp,12
810001a6: 8100 0x8100
810001a8: 00c4 addi s1,sp,68
810001a8: 0078 addi a4,sp,12
810001aa: 8100 0x8100
810001ac: 00c8 addi a0,sp,68
810001ac: 007c addi a5,sp,12
810001ae: 8100 0x8100
810001b0: 00cc addi a1,sp,68
810001b0: 0080 addi s0,sp,64
810001b2: 8100 0x8100
810001b4: 00d0 addi a2,sp,68
810001b6: 8100 0x8100
810001b8: 00d4 addi a3,sp,68
810001ba: 8100 0x8100
810001bc: 00d8 addi a4,sp,68
810001be: 8100 0x8100
810001c0: 00dc addi a5,sp,68
810001c2: 8100 0x8100
810001c4: 00e0 addi s0,sp,76
810001c6: 8100 0x8100
810001c8: 00e4 addi s1,sp,76
810001ca: 8100 0x8100
810001cc: 00e8 addi a0,sp,76
810001ce: 8100 0x8100
810001d0: 00ec addi a1,sp,76
810001d2: 8100 0x8100
810001d4: 00f0 addi a2,sp,76
810001d6: 8100 0x8100
810001d8: 00f4 addi a3,sp,76
810001da: 8100 0x8100
810001dc <x>:
810001dc: 0005 c.nop 1
810001de: 0000 unimp
810001e0: 0005 c.nop 1
810001e2: 0000 unimp
810001e4: 0005 c.nop 1
810001e6: 0000 unimp
810001e8: 0005 c.nop 1
810001ea: 0000 unimp
810001ec: 0006 c.slli zero,0x1
810001ee: 0000 unimp
810001f0: 0006 c.slli zero,0x1
810001f2: 0000 unimp
810001f4: 0006 c.slli zero,0x1
810001f6: 0000 unimp
810001f8: 0006 c.slli zero,0x1
810001fa: 0000 unimp
810001fc: 00000007 0x7
81000200: 00000007 0x7
81000204: 00000007 0x7
81000208: 00000007 0x7
8100020c: 0008 0x8
8100020e: 0000 unimp
81000210: 0008 0x8
81000212: 0000 unimp
81000214: 0008 0x8
81000216: 0000 unimp
81000218: 0008 0x8
810001b4 <tmc_array>:
810001b4: 0005 c.nop 1
810001b6: 0000 unimp
810001b8: 0005 c.nop 1
810001ba: 0000 unimp
810001bc: 0005 c.nop 1
810001be: 0000 unimp
810001c0: 0005 c.nop 1
...
8100021c <y>:
8100021c: 0001 nop
810001c4 <hextoa>:
810001c4: 00b8 addi a4,sp,72
810001c6: 8100 0x8100
810001c8: 00bc addi a5,sp,72
810001ca: 8100 0x8100
810001cc: 00c0 addi s0,sp,68
810001ce: 8100 0x8100
810001d0: 00c4 addi s1,sp,68
810001d2: 8100 0x8100
810001d4: 00c8 addi a0,sp,68
810001d6: 8100 0x8100
810001d8: 00cc addi a1,sp,68
810001da: 8100 0x8100
810001dc: 00d0 addi a2,sp,68
810001de: 8100 0x8100
810001e0: 00d4 addi a3,sp,68
810001e2: 8100 0x8100
810001e4: 00d8 addi a4,sp,68
810001e6: 8100 0x8100
810001e8: 00dc addi a5,sp,68
810001ea: 8100 0x8100
810001ec: 00e0 addi s0,sp,76
810001ee: 8100 0x8100
810001f0: 00e4 addi s1,sp,76
810001f2: 8100 0x8100
810001f4: 00e8 addi a0,sp,76
810001f6: 8100 0x8100
810001f8: 00ec addi a1,sp,76
810001fa: 8100 0x8100
810001fc: 00f0 addi a2,sp,76
810001fe: 8100 0x8100
81000200: 00f4 addi a3,sp,76
81000202: 8100 0x8100
81000204 <x>:
81000204: 0005 c.nop 1
81000206: 0000 unimp
81000208: 0005 c.nop 1
8100020a: 0000 unimp
8100020c: 0005 c.nop 1
8100020e: 0000 unimp
81000210: 0005 c.nop 1
81000212: 0000 unimp
81000214: 0006 c.slli zero,0x1
81000216: 0000 unimp
81000218: 0006 c.slli zero,0x1
8100021a: 0000 unimp
8100021c: 0006 c.slli zero,0x1
8100021e: 0000 unimp
81000220: 0001 nop
81000220: 0006 c.slli zero,0x1
81000222: 0000 unimp
81000224: 0001 nop
81000226: 0000 unimp
81000228: 0001 nop
8100022a: 0000 unimp
8100022c: 0001 nop
8100022e: 0000 unimp
81000230: 0001 nop
81000232: 0000 unimp
81000234: 0001 nop
81000224: 00000007 0x7
81000228: 00000007 0x7
8100022c: 00000007 0x7
81000230: 00000007 0x7
81000234: 0008 0x8
81000236: 0000 unimp
81000238: 0001 nop
81000238: 0008 0x8
8100023a: 0000 unimp
8100023c: 0001 nop
8100023c: 0008 0x8
8100023e: 0000 unimp
81000240: 0001 nop
81000242: 0000 unimp
81000240: 0008 0x8
...
81000244 <y>:
81000244: 0001 nop
81000246: 0000 unimp
81000248: 0001 nop
@ -902,29 +955,49 @@ Disassembly of section .data:
81000254: 0001 nop
81000256: 0000 unimp
81000258: 0001 nop
8100025a: 0000 unimp
8100025c: 0001 nop
8100025e: 0000 unimp
81000260: 0001 nop
81000262: 0000 unimp
81000264: 0001 nop
81000266: 0000 unimp
81000268: 0001 nop
8100026a: 0000 unimp
8100026c: 0001 nop
8100026e: 0000 unimp
81000270: 0001 nop
81000272: 0000 unimp
81000274: 0001 nop
81000276: 0000 unimp
81000278: 0001 nop
8100027a: 0000 unimp
8100027c: 0001 nop
8100027e: 0000 unimp
81000280: 0001 nop
...
Disassembly of section .bss:
8100025c <global_argument_struct>:
8100025c: 0000 unimp
81000284 <global_argument_struct>:
81000284: 0000 unimp
...
81000260 <global_function_pointer>:
81000260: 0000 unimp
81000288 <global_function_pointer>:
81000288: 0000 unimp
...
81000264 <global_num_threads>:
81000264: 0000 unimp
8100028c <global_num_threads>:
8100028c: 0000 unimp
...
81000268 <wsapwn_arr>:
81000290 <wsapwn_arr>:
...
81000278 <div_arr>:
810002a0 <div_arr>:
...
81000288 <z>:
810002b0 <z>:
...
Disassembly of section .comment:

BIN
runtime/mains/dev/vx_dev_main.elf
View file

Binary file not shown.

155
runtime/mains/dev/vx_dev_main.hex
View file

@ -1,6 +1,6 @@
:0200000480007A
:100000009705000093850502130540006B10B500AD
:10001000EF000001EF008074130500006B00050085
:10001000EF000001EF001001130500006B00050068
:10002000130540006B000500F32610029396A6010D
:10003000732600029315A6001316260037F1FF6FF2
:100040003301B1403301D1403301C100F326100226
@ -18,7 +18,7 @@
:100100001301C10067800000B702010023A0B20004
:1001100067800000130101FE232E1100232C8100B3
:10012000130401022326A4FEB70700810327C4FE9F
:10013000131727009387C710B307F70083A707009B
:100130001317270093874713B307F70083A7070018
:1001400013850700EFF05FF9130000008320C10161
:10015000032481011301010267800000130101FEE5
:10016000232E1100232C8100130401022326A4FE58
@ -26,31 +26,31 @@
:10018000EFF05FF9B707008113850704EFF0DFF4A4
:10019000130000008320C101032481011301010227
:1001A00067800000130101FE232E1100232C810023
:1001B00013040102B707008183A7472613850700B0
:1001C000EFF09FEAB707008103A70726B707008172
:1001D00083A7C72513850700E7000700EFF0DFEAD4
:1001B00013040102B707008183A7C728138507002E
:1001C000EFF09FEAB707008103A78728B7070081F0
:1001D00083A7472813850700E7000700EFF0DFEA51
:1001E0002326A4FE8327C4FE6388070013050000AE
:1001F000EFF09FE76F00C00013051000EFF0DFE69F
:10020000130000008320C1010324810113010102B6
:1002100067800000130101FE232E1100232C8100B2
:10022000130401022326A4FE2324B4FE2322C4FEC9
:100230002320D4FEB7070081032744FE23A0E7262E
:10024000B7070081032704FE23AEE724B707008128
:10025000032784FE23A2E726B70700809387471A67
:100230002320D4FEB7070081032744FE23A4E72828
:10024000B7070081032704FE23A2E728B707008130
:10025000032784FE23A6E728B70700809387471A61
:10026000938507000325C4FEEFF09FDFEFF09FF3B7
:10027000130000008320C101032481011301010246
:1002800067800000130101FE232E1100232C810042
:1002900013040102B707008113854708EFF0DFE37D
:1002A00013054000EFF05FDCEFF09FDE2326A4FE95
:1002B0000327C4FEB70700818326C4FE9396260059
:1002C0009387C718B387F60023A0E7001305100033
:1002D000EFF09FD9B707008183A7C71813850700E0
:1002C0009387471BB387F60023A0E70013051000B0
:1002D000EFF09FD9B707008183A7471B138507005D
:1002E000EFF05FE3B707008113854709EFF0DFDE2A
:1002F000B70700819387C71883A7470013850700B6
:1002F000B70700819387471B83A747001385070033
:10030000EFF05FE1B707008113854709EFF0DFDC0D
:10031000B70700819387C71883A787001385070055
:10031000B70700819387471B83A7870013850700D2
:10032000EFF05FDFB707008113854709EFF0DFDAF1
:10033000B70700819387C71883A7C70013850700F5
:10033000B70700819387471B83A7C7001385070072
:10034000EFF05FDDB707008113854709EFF0DFD8D5
:10035000130000008320C101032481011301010265
:1003600067800000130101FE232E1100232C810061
@ -59,40 +59,40 @@
:10039000EFF09FCE8347B4FE638407068327C4FE35
:1003A00093B717002305F4FE8347A4FE13850700C7
:1003B000EFF09FCC8347A4FE63820702B70700815A
:1003C0000327C4FE1317270093878727B307F70077
:1003C0000327C4FE131727009387072AB307F700F4
:1003D0001307A00023A0E7006F000002B707008109
:1003E0000327C4FE1317270093878727B307F70057
:1003E0000327C4FE131727009387072AB307F700D4
:1003F0001307B00023A0E700EFF09FC86F0040068E
:100400008327C4FE93B73700A304F4FE834794FE0A
:1004100013850700EFF05FC6834794FE63820702EF
:10042000B70700810327C4FE131727009387872788
:10042000B70700810327C4FE131727009387072A05
:10043000B307F7001307C00023A0E7006F00000216
:10044000B70700810327C4FE131727009387872768
:10044000B70700810327C4FE131727009387072AE5
:10045000B307F7001307D00023A0E700EFF05FC257
:10046000EFF01FC2B707008183A787271385070016
:10046000EFF01FC2B707008183A7072A1385070093
:10047000EFF05FCAB707008113854709EFF0DFC5CA
:10048000B70700819387872783A747001385070055
:10048000B70700819387072A83A7470013850700D2
:10049000EFF05FC8B707008113854709EFF0DFC3AE
:1004A000B70700819387872783A7870013850700F5
:1004A000B70700819387072A83A787001385070072
:1004B000EFF05FC6B707008113854709EFF0DFC192
:1004C000B70700819387872783A7C7001385070095
:1004C000B70700819387072A83A7C7001385070012
:1004D000EFF05FC4B707008113854709EFF0DFBF76
:1004E000130000008320C1010324810113010102D4
:1004F00067800000130101FE232E1100232C8100D0
:1005000013040102EFF05FB82326A4FEB7070081B1
:100510000327C4FE1317270093878726B307F70026
:100510000327C4FE1317270093870729B307F700A3
:100520000327C4FE23A0E7008327C4FE63860700D9
:1005300013050000EFF05FB3130000008320C1013A
:10054000032481011301010267800000130101FEF1
:10055000232E1100232C810013040102B707008011
:100560009387474F2326F4FE8325C4FE13054000DE
:10057000EFF01FAFEFF01FF8B707008183A78726C2
:10057000EFF01FAFEFF01FF8B707008183A707293F
:1005800013850700EFF01FB9B707008113854709EE
:10059000EFF09FB4B70700819387872683A74700B2
:10059000EFF09FB4B70700819387072983A747002F
:1005A00013850700EFF01FB7B707008113854709D0
:1005B000EFF09FB2B70700819387872683A7870054
:1005B000EFF09FB2B70700819387072983A78700D1
:1005C00013850700EFF01FB5B707008113854709B2
:1005D000EFF09FB0B70700819387872683A7C700F6
:1005D000EFF09FB0B70700819387072983A7C70073
:1005E00013850700EFF01FB3B70700811385470994
:1005F000EFF09FAE130000008320C10103248101AE
:100600001301010267800000130101FF232611007E
@ -116,26 +116,40 @@
:10072000B307F70003A707008327C4FE03A68700CB
:100730008327C4FD93972700B307F6003387E600AD
:1007400023A0E700EFF0DF93130000008320C10334
:10075000032481031301010467800000130101FCDD
:10076000232E1102232C810213040104130510000F
:10077000EFF09F8FB70700811385870FEFF0DF95AC
:10078000B70700819387C71D2324F4FCB7070081B6
:100790009387C7212326F4FCB70700819387872816
:1007A0002328F4FC93074000232AF4FC930740001D
:1007B000232CF4FC930740002322F4FE930740000F
:1007C0002320F4FE032744FE832504FE930784FCC4
:1007D00093860700B7070080138607661305070096
:1007E000EFF05FA3232604FE6F000008232404FE1D
:1007F0006F004005032744FD8327C4FE3307F7023B
:10080000832784FEB307F700232EF4FCB70700818B
:100810000327C4FD1317270093878728B307F70022
:1008200083A7070013850700EFF0DF8EB70700816D
:1008300013854710EFF05F8A832784FE93871700A4
:100840002324F4FE032744FD832784FEE3E4E7FA30
:10085000B707008113858710EFF01F888327C4FE38
:10086000938717002326F4FE032784FD8327C4FE05
:10087000E3EEE7F693070000138507008320C1032A
:0C088000032481031301010467800000C1
:10075000032481031301010467800000130101FDDC
:10076000232611022324810213040103232EA4FC57
:10077000232CB4FC232AC4FCB70700811385870F00
:10078000EFF09F95232604FE6F00C007232404FE8C
:100790006F0000050327C4FE832744FD3307F702DB
:1007A000832784FEB307F7002322F4FE832744FE49
:1007B000939727000327C4FDB307F70083A707001B
:1007C00013850700EFF01F95B70700811385071108
:1007D000EFF09F90832784FE938717002324F4FE75
:1007E000032784FE832744FDE346F7FAB707008119
:1007F00013854711EFF05F8E8327C4FE93871700A0
:100800002326F4FE0327C4FE832784FDE340F7F884
:10081000130000008320C10203248102130101039D
:1008200067800000130101FD2326110223248102A9
:100830001304010313051000EFF01F83B7070081B5
:1008400013858711EFF05F89B70700811385471281
:10085000EFF09F88B707008193874720232AF4FC95
:10086000B707008193874724232CF4FCB707008146
:100870009387072B232EF4FC930740002320F4FEDC
:10088000930740002322F4FE930740002326F4FE42
:10089000930740002324F4FE0327C4FE832584FE2F
:1008A000930744FD93860700B70700801386076609
:1008B00013050700EFF01F96832744FE13870700F8
:1008C000832704FE1386070093050700B7070081FE
:1008D0001385072BEFF09FE8B70700819387072B5D
:1008E000232AF4FCB707008193874724232CF4FCC8
:1008F000B70700819387072B232EF4FC9307400052
:100900002320F4FE930740002322F4FE0327C4FEB5
:10091000832584FE930744FD93860700B707008074
:100920001386076613050700EFF0DF8E832744FE6A
:1009300013870700832704FE13860700930507002B
:10094000B70700811385072BEFF05FE193070000E5
:10095000138507008320C1020324810213010103D0
:0409600067800000AC
:02000004810079
:10000000300000003100000032000000330000002A
:10001000340000003500000036000000370000000A
@ -152,28 +166,31 @@
:1000C0003200000033000000340000003500000062
:1000D0003600000037000000380000003900000042
:1000E0006100000062000000630000006400000086
:1000F0006500000066000000446576204D61696E71
:0A0100000A000000200000000A00C1
:10010C000000008104000081080000810C000081C7
:10011C001000008114000081180000811C00008177
:10012C002000008124000081280000812C00008127
:10013C003000008134000081380000813C000081D7
:10014C0044000081480000814C0000815000008177
:10015C0054000081580000815C0000816000008127
:10016C0064000081680000816C00008170000081D7
:10017C0074000081780000817C0000818000008187
:10018C00050000000500000005000000050000004F
:10019C00B8000081BC000081C0000081C400008157
:1001AC00C8000081CC000081D0000081D400008107
:1001BC00D8000081DC000081E0000081E4000081B7
:1001CC00E8000081EC000081F0000081F400008167
:1001DC0005000000050000000500000005000000FF
:1001EC0006000000060000000600000006000000EB
:1001FC0007000000070000000700000007000000D7
:10020C0008000000080000000800000008000000C2
:10021C0001000000010000000100000001000000CE
:10022C0001000000010000000100000001000000BE
:10023C0001000000010000000100000001000000AE
:10024C00010000000100000001000000010000009E
:1000F00065000000660000002D2D2D2D2D2D2D2DCD
:100100002D2D2D2D2D2D2D2D2D2D2D2D2D0A00009C
:10011000200000000A000000446576204D61696EF1
:100120000A00000076785F737061776E57617270B5
:03013000730A004F
:100134000000008104000081080000810C0000819F
:100144001000008114000081180000811C0000814F
:100154002000008124000081280000812C000081FF
:100164003000008134000081380000813C000081AF
:1001740044000081480000814C000081500000814F
:1001840054000081580000815C00008160000081FF
:1001940064000081680000816C00008170000081AF
:1001A40074000081780000817C000081800000815F
:1001B4000500000005000000050000000500000027
:1001C400B8000081BC000081C0000081C40000812F
:1001D400C8000081CC000081D0000081D4000081DF
:1001E400D8000081DC000081E0000081E40000818F
:1001F400E8000081EC000081F0000081F40000813F
:1002040005000000050000000500000005000000D6
:1002140006000000060000000600000006000000C2
:1002240007000000070000000700000007000000AE
:10023400080000000800000008000000080000009A
:1002440001000000010000000100000001000000A6
:100254000100000001000000010000000100000096
:100264000100000001000000010000000100000086
:100274000100000001000000010000000100000076
:040000058000000077
:00000001FF

12
runtime/vx_api/vx_api.c
View file

@ -35,3 +35,15 @@ void vx_spawnWarps(unsigned numWarps, unsigned numThreads, func_t func_ptr, void
setup_call();
}
// void vx_cl_spawnWarps(char * args, char * pocl_context, long group_x, long group_y, long group_z)
// {
// if (group_z != 1)
// {
// vx_printf("ERROR: group_z should be set equal to 1");
// return;
// }
// vx_spawnWarps(group_y, group_x, )
// }

7
runtime/vx_api/vx_api.h
View file

@ -9,8 +9,11 @@ typedef void (*func_t)(void *);
void vx_spawnWarps(unsigned numWarps, unsigned numThreads, func_t func_ptr , void * args);
void vx_cl_spawnWarps (char * /* args */,
char * /* pocl_context */,
long /* group_x */,
long /* group_y */,
long /* group_z */);

0
simX/BUGS Normal file
View file

12
simX/LICENSE Normal file
View file

@ -0,0 +1,12 @@
Copyright (c) 2011, Georgia Institute of Technology
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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################################################################################
# HARPtools by Chad D. Kersey, Summer 2011 #
################################################################################
CXXFLAGS ?= -std=c++11 -fPIC -O3 # -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
LIB_OBJS=simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp
INCLUDE=-I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl
FILE=cache_simX.v
COMP=--compiler gcc
LIB=
CF=-CFLAGS '-std=c++11 -fPIC -O3'
LIGHTW=-Wno-UNOPTFLAT -Wno-BLKLOOPINIT
EXE=--exe $(LIB_OBJS)
all: simX
# simX:
# g++ $(LDFLAGS) $(LIB_OBJS) -o simX.run
simX:
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW)
(cd obj_dir && make -j -f Vcache_simX.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
clean:
rm -rf *~ \#* *.o *.a *.so include/*~ include/\#* simX.run obj_dir

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- Anonymous chunks whose names are not saved by the object writer.
- 32-bit instruction encoding for larger-pointered architecture versions.
- HOFDump mode for HARPTool/HOFTool
- Make operation information tables into member functions of Instruction, if
possible.
- Anonymous assigned values in the assembler.
- References (pointers) as .word directive contents in the assembler.
- Instruction validation before encoding.
- Make readError in obj.cpp throw something instead of printing a message and
exiting.
- Limit checking for byte/word encoders (e.g. 255 pRegs, 256 regs for byte)
- Eliminate the tmp_buf nonsense from the chunk encoder.
- Loosen arch restrictions imposed for interoperability (the number of lanes is
typically unimportant)

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#include "include/args.h"
#include <iostream>
#include <string>
using namespace HarpTools;
using std::string;
std::string CommandLineArg::helpString;
std::map<string, CommandLineArg *> CommandLineArg::longArgs;
std::map<string, CommandLineArg *> CommandLineArg::shortArgs;
CommandLineArg::CommandLineArg(string s, string l, const char *helpText)
{
helpString += helpText;
longArgs[l] = this;
shortArgs[s] = this;
}
CommandLineArg::CommandLineArg(string l, const char *helpText) {
helpString += helpText;
longArgs[l] = this;
}
void CommandLineArg::readArgs(int argc, char **argv) {
for (int i = 0; i < argc; i++) {
std::map<string, CommandLineArg *>::iterator
s = shortArgs.find(std::string(argv[i])),
l = longArgs.find(std::string(argv[i]));
if (s != shortArgs.end()) {
i += s->second->read(argc - i, &argv[i]);
} else if (l != longArgs.end()) {
i += l->second->read(argc - i, &argv[i]);
} else {
throw BadArg(string(argv[i]));
}
}
}
void CommandLineArg::clearArgs() {
shortArgs.clear();
longArgs.clear();
helpString = "";
}
void CommandLineArg::showHelp(std::ostream &os) {
os << helpString;
}

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`include "../rtl/VX_define.v"
module cache_simX (
input wire clk, // Clock
input wire reset,
// Icache
input wire[31:0] in_icache_pc_addr,
input wire in_icache_valid_pc_addr,
output wire out_icache_stall,
// Dcache
input wire[2:0] in_dcache_mem_read,
input wire[2:0] in_dcache_mem_write,
input wire in_dcache_in_valid[`NT_M1:0],
input wire[31:0] in_dcache_in_address[`NT_M1:0],
output wire out_dcache_stall
);
//////////////////// ICACHE ///////////////////
VX_icache_request_inter VX_icache_req;
assign VX_icache_req.pc_address = in_icache_pc_addr;
assign VX_icache_req.out_cache_driver_in_mem_read = (in_icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ;
assign VX_icache_req.out_cache_driver_in_mem_write = `NO_MEM_WRITE;
assign VX_icache_req.out_cache_driver_in_valid = in_icache_valid_pc_addr;
assign VX_icache_req.out_cache_driver_in_data = 0;
VX_icache_response_inter VX_icache_rsp;
assign out_icache_stall = VX_icache_rsp.delay;
VX_dram_req_rsp_inter #(
.NUMBER_BANKS(`ICACHE_BANKS),
.NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK)
) VX_dram_req_rsp_icache();
reg icache_i_m_ready;
assign VX_dram_req_rsp_icache.i_m_ready = icache_i_m_ready;
//////////////////// DCACHE ///////////////////
VX_dcache_request_inter VX_dcache_req;
assign VX_dcache_req.out_cache_driver_in_mem_read = in_dcache_mem_read;
assign VX_dcache_req.out_cache_driver_in_mem_write = in_dcache_mem_write;
assign VX_dcache_req.out_cache_driver_in_data = 0;
genvar curr_t;
for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1)
begin
assign VX_dcache_req.out_cache_driver_in_address[curr_t] = in_dcache_in_address[curr_t];
assign VX_dcache_req.out_cache_driver_in_valid[curr_t] = in_dcache_in_valid[curr_t];
end
VX_dcache_response_inter VX_dcache_rsp;
assign out_dcache_stall = VX_dcache_rsp.delay;
VX_dram_req_rsp_inter #(
.NUMBER_BANKS(`DCACHE_BANKS),
.NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK)
) VX_dram_req_rsp();
reg dcache_i_m_ready;
assign VX_dram_req_rsp.i_m_ready = dcache_i_m_ready;
VX_dmem_controller dmem_controller (
.clk (clk),
.reset (reset),
.VX_dram_req_rsp (VX_dram_req_rsp),
.VX_dram_req_rsp_icache(VX_dram_req_rsp_icache),
.VX_icache_req (VX_icache_req),
.VX_icache_rsp (VX_icache_rsp),
.VX_dcache_req (VX_dcache_req),
.VX_dcache_rsp (VX_dcache_rsp)
);
always @(posedge clk, posedge reset) begin
if (reset)
begin
icache_i_m_ready <= 0;
dcache_i_m_ready <= 0;
end else begin
if (VX_dram_req_rsp_icache.o_m_valid) begin
icache_i_m_ready <= 1;
end else if (icache_i_m_ready) begin
icache_i_m_ready <= 0;
end else begin
icache_i_m_ready <= 0;
end
if (VX_dram_req_rsp.o_m_valid) begin
dcache_i_m_ready <= 1;
end else if (dcache_i_m_ready) begin
dcache_i_m_ready <= 0;
end else begin
dcache_i_m_ready <= 0;
end
end
end
endmodule

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#include <iostream>
#include <iomanip>
// #define USE_DEBUG 7
// #define PRINT_ACTIVE_THREADS
#include "include/types.h"
#include "include/util.h"
#include "include/archdef.h"
#include "include/mem.h"
#include "include/enc.h"
#include "include/core.h"
#include "include/debug.h"
#ifdef EMU_INSTRUMENTATION
#include "include/qsim-harp.h"
#endif
using namespace Harp;
using namespace std;
#ifdef EMU_INSTRUMENTATION
void Harp::reg_doRead(Word cpuId, Word regNum) {
Harp::OSDomain::osDomain->do_reg(cpuId, regNum, 8, true);
}
void Harp::reg_doWrite(Word cpuId, Word regNum) {
Harp::OSDomain::osDomain->do_reg(cpuId, regNum, 8, false);
}
#endif
Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
a(a), iDec(d), mem(mem), steps(0)
{
cache_simulator = new Vcache_simX;
for (unsigned i = 0; i < a.getNWarps(); ++i)
w.push_back(Warp(this, i));
w[0].activeThreads = 1;
w[0].spawned = true;
}
bool Core::interrupt(Word r0) {
w[0].interrupt(r0);
}
void Core::step()
{
this->fetch();
}
void Core::fetch()
{
++steps;
#ifdef PRINT_ACTIVE_THREADS
cout << endl << "Threads:";
#endif
for (unsigned i = 0; i < w.size(); ++i) {
if (w[i].activeThreads) {
trace_inst_t trace_inst;
trace_inst.valid_inst = false;
trace_inst.pc = 0;
trace_inst.wid = i;
trace_inst.rs1 = -1;
trace_inst.rs2 = -1;
trace_inst.rd = -1;
trace_inst.is_lw = false;
trace_inst.is_sw = false;
trace_inst.mem_addresses = new unsigned[a.getNThds()];
trace_inst.mem_stall_cycles = 0;
trace_inst.fetch_stall_cycles = 0;
trace_inst.stall_warp = false;
D(3, "Core step stepping warp " << i << '[' << w[i].activeThreads << ']');
w[i].step(&trace_inst);
D(3, "Now " << w[i].activeThreads << " active threads in " << i);
D(-1, "********************************");
D(-1, "*** valid: " << trace_inst.valid_inst << " pc: " << hex << trace_inst.pc << dec << " rs1..rs2..rd " << trace_inst.rs1 << ".." << trace_inst.rs2 << ".." << trace_inst.rd << "\n");
D(-1, "********************************");
}
#ifdef PRINT_ACTIVE_THREADS
for (unsigned j = 0; j < w[i].tmask.size(); ++j) {
if (w[i].activeThreads > j && w[i].tmask[j]) cout << " 1";
else cout << " 0";
if (j != w[i].tmask.size()-1 || i != w.size()-1) cout << ',';
}
#endif
}
#ifdef PRINT_ACTIVE_THREADS
cout << endl;
#endif
}
void Core::decode()
{
}
void Core::scheduler()
{
}
void Core::gpr_read()
{
}
void Core::execute_unit()
{
}
void Core::load_store()
{
}
bool Core::running() const {
for (unsigned i = 0; i < w.size(); ++i)
if (w[i].running()) return true;
return false;
}
void Core::printStats() const {
unsigned long insts = 0;
for (unsigned i = 0; i < w.size(); ++i)
insts += w[i].insts;
cout << "Total steps: " << steps << endl;
cout << "Total insts: " << insts << endl;
for (unsigned i = 0; i < w.size(); ++i) {
cout << "=== Warp " << i << " ===" << endl;
w[i].printStats();
}
}
Warp::Warp(Core *c, Word id) :
core(c), pc(0x80000000), interruptEnable(true),
supervisorMode(true), activeThreads(0), reg(0), pred(0),
shadowReg(core->a.getNRegs()), shadowPReg(core->a.getNPRegs()), id(id),
spawned(false), steps(0), insts(0), loads(0), stores(0)
{
D(3, "Creating a new thread with PC: " << hex << this->pc << '\n');
/* Build the register file. */
Word regNum(0);
for (Word j = 0; j < core->a.getNThds(); ++j) {
reg.push_back(vector<Reg<Word> >(0));
for (Word i = 0; i < core->a.getNRegs(); ++i) {
reg[j].push_back(Reg<Word>(id, regNum++));
}
pred.push_back(vector<Reg<bool> >(0));
for (Word i = 0; i < core->a.getNPRegs(); ++i) {
pred[j].push_back(Reg<bool>(id, regNum++));
}
bool act = false;
if (j == 0) act = true;
tmask.push_back(act);
shadowTmask.push_back(act);
}
Word csrNum(0);
for (Word i = 0; i < (1<<12); i++)
{
csr.push_back(Reg<uint16_t>(id, regNum++));
}
/* Set initial register contents. */
reg[0][0] = (core->a.getNThds()<<(core->a.getWordSize()*8 / 2)) | id;
}
void Warp::step(trace_inst_t * trace_inst) {
Size fetchPos(0), decPos, wordSize(core->a.getWordSize());
vector<Byte> fetchBuffer(wordSize);
if (activeThreads == 0) return;
++steps;
D(3, "in step pc=0x" << hex << pc);
// std::cout << "pc: " << hex << pc << "\n";
trace_inst->pc = pc;
/* Fetch and decode. */
if (wordSize < sizeof(pc)) pc &= ((1ll<<(wordSize*8))-1);
Instruction *inst;
bool fetchMore;
fetchMore = false;
unsigned fetchSize(wordSize - (pc+fetchPos)%wordSize);
fetchBuffer.resize(fetchPos + fetchSize);
Word fetched = core->mem.fetch(pc + fetchPos, supervisorMode);
writeWord(fetchBuffer, fetchPos, fetchSize, fetched);
decPos = 0;
inst = core->iDec.decode(fetchBuffer, decPos, trace_inst);
D(3, "Fetched at 0x" << hex << pc);
D(3, "0x" << hex << pc << ": " << *inst);
// Update pc
pc += decPos;
// Execute
inst->executeOn(*this);
// At Debug Level 3, print debug info after each instruction.
#ifdef USE_DEBUG
if (USE_DEBUG >= 3) {
D(3, "Register state:");
for (unsigned i = 0; i < reg[0].size(); ++i) {
D_RAW(" %r" << setfill(' ') << setw(2) << dec << i << ':');
for (unsigned j = 0; j < reg.size(); ++j)
D_RAW(' ' << setfill('0') << setw(8) << hex << reg[j][i] << setfill(' ') << ' ');
D_RAW('(' << shadowReg[i] << ')' << endl);
}
D(3, "Thread mask:");
D_RAW(" ");
for (unsigned i = 0; i < tmask.size(); ++i) D_RAW(tmask[i] << ' ');
D_RAW(endl);
D_RAW(endl);
D_RAW(endl);
}
#endif
// Clean up.
delete inst;
}
bool Warp::interrupt(Word r0) {
if (!interruptEnable) return false;
#ifdef EMU_INSTRUMENTATION
Harp::OSDomain::osDomain->do_int(0, r0);
#endif
shadowActiveThreads = activeThreads;
shadowTmask = tmask;
shadowInterruptEnable = interruptEnable; /* For traps. */
shadowSupervisorMode = supervisorMode;
for (Word i = 0; i < reg[0].size(); ++i) shadowReg[i] = reg[0][i];
for (Word i = 0; i < pred[0].size(); ++i) shadowPReg[i] = pred[0][i];
for (Word i = 0; i < reg.size(); ++i) tmask[i] = 1;
shadowPc = pc;
activeThreads = 1;
interruptEnable = false;
supervisorMode = true;
reg[0][0] = r0;
pc = core->interruptEntry;
return true;
}
void Warp::printStats() const {
cerr << "Steps : " << steps << endl
<< "Insts : " << insts << endl
<< "Loads : " << loads << endl
<< "Stores: " << stores << endl;
unsigned const grade = reg[0][28];
if (grade == 1) cerr << "GRADE: PASSED\n";
else cerr << "GRADE: FAILED " << (grade >> 1) << "\n";
}

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#include <iostream>
#include <string>
#include <stdlib.h>
#include <string.h>
#include <iomanip>
#include <vector>
#include "include/debug.h"
#include "include/types.h"
#include "include/util.h"
#include "include/enc.h"
#include "include/archdef.h"
#include "include/instruction.h"
using namespace std;
using namespace Harp;
// ByteDecoder::ByteDecoder(const ArchDef &ad) {
// wordSize = ad.getWordSize();
// }
static void decodeError(string msg) {
cout << "Instruction decoder error: " << msg << '\n';
exit(1);
}
static unsigned ceilLog2(RegNum x) {
unsigned z = 0;
bool nonZeroInnerValues(false);
if (x == 0) return 0;
while (x != 1) {
z++;
if (x&1) nonZeroInnerValues = true;
x >>= 1;
}
if (nonZeroInnerValues) z++;
return z;
}
WordDecoder::WordDecoder(const ArchDef &arch) {
inst_s = arch.getWordSize() * 8;
opcode_s = 7;
reg_s = 5;
func3_s = 3;
shift_opcode = 0;
shift_rd = opcode_s;
shift_func3 = opcode_s + reg_s;
shift_rs1 = opcode_s + reg_s + func3_s;
shift_rs2 = opcode_s + reg_s + func3_s + reg_s;
shift_func7 = opcode_s + reg_s + func3_s + reg_s + reg_s;
shift_j_u_immed = opcode_s + reg_s;
shift_s_b_immed = opcode_s + reg_s + func3_s + reg_s + reg_s;
shift_i_immed = opcode_s + reg_s + func3_s + reg_s;
reg_mask = 0x1f;
func3_mask = 0x7;
func7_mask = 0x7f;
opcode_mask = 0x7f;
i_immed_mask = 0xfff;
s_immed_mask = 0xfff;
b_immed_mask = 0x1fff;
u_immed_mask = 0xfffff;
j_immed_mask = 0xfffff;
}
static Word signExt(Word w, Size bit, Word mask) {
if (w>>(bit-1)) w |= ~mask;
return w;
}
Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_inst_t * trace_inst) {
Word code(readWord(v, idx, inst_s/8));
// std::cout << "code: " << (int) code << " v: " << v << " indx: " << idx << "\n";
Instruction &inst = * new Instruction();
// bool predicated = (code>>(n-1));
bool predicated = false;
if (predicated) { inst.setPred((code>>(inst_s-p-1))&pMask); }
Opcode op = (Opcode)((code>>shift_opcode)&opcode_mask);
// std::cout << "opcode: " << op << "\n";
inst.setOpcode(op);
bool usedImm(false);
Word imeed, dest_bits, imm_bits, bit_11, bits_4_1, bit_10_5,
bit_12, bits_19_12, bits_10_1, bit_20, unordered, func3;
// std::cout << "op: " << std::hex << op << " what " << instTable[op].iType << "\n";
switch(instTable[op].iType)
{
case InstType::N_TYPE:
break;
case InstType::R_TYPE:
inst.setPred((code>>shift_rs1) & reg_mask);
inst.setDestReg((code>>shift_rd) & reg_mask);
inst.setSrcReg((code>>shift_rs1) & reg_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setFunc3 ((code>>shift_func3) & func3_mask);
inst.setFunc7 ((code>>shift_func7) & func7_mask);
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
trace_inst->rd = ((code>>shift_rd) & reg_mask);
break;
case InstType::I_TYPE:
inst.setDestReg((code>>shift_rd) & reg_mask);
inst.setSrcReg((code>>shift_rs1) & reg_mask);
inst.setFunc7 ((code>>shift_func7) & func7_mask);
func3 = (code>>shift_func3) & func3_mask;
inst.setFunc3 (func3);
if ((func3 == 5) && (op != L_INST))
{
// std::cout << "func7: " << func7 << "\n";
inst.setSrcImm(signExt(((code>>shift_rs2)&reg_mask), 5, reg_mask));
}
else
{
inst.setSrcImm(signExt(code>>shift_i_immed, 12, i_immed_mask));
}
usedImm = true;
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
trace_inst->rd = ((code>>shift_rd) & reg_mask);
break;
case InstType::S_TYPE:
// std::cout << "************STORE\n";
inst.setSrcReg((code>>shift_rs1) & reg_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setFunc3 ((code>>shift_func3) & func3_mask);
dest_bits = (code>>shift_rd) & reg_mask;
imm_bits = (code>>shift_s_b_immed & func7_mask);
imeed = (imm_bits << reg_s) | dest_bits;
// std::cout << "ENC: store imeed: " << imeed << "\n";
inst.setSrcImm(signExt(imeed, 12, s_immed_mask));
usedImm = true;
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
break;
case InstType::B_TYPE:
inst.setSrcReg((code>>shift_rs1) & reg_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setFunc3 ((code>>shift_func3) & func3_mask);
dest_bits = (code>>shift_rd) & reg_mask;
imm_bits = (code>>shift_s_b_immed & func7_mask);
bit_11 = dest_bits & 0x1;
bits_4_1 = dest_bits >> 1;
bit_10_5 = imm_bits & 0x3f;
bit_12 = imm_bits >> 6;
imeed = 0 | (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
inst.setSrcImm(signExt(imeed, 13, b_immed_mask));
usedImm = true;
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
break;
case InstType::U_TYPE:
inst.setDestReg((code>>shift_rd) & reg_mask);
inst.setSrcImm(signExt(code>>shift_j_u_immed, 20, u_immed_mask));
usedImm = true;
trace_inst->valid_inst = true;
trace_inst->rd = ((code>>shift_rd) & reg_mask);
break;
case InstType::J_TYPE:
inst.setDestReg((code>>shift_rd) & reg_mask);
// [20 | 10:1 | 11 | 19:12]
unordered = code>>shift_j_u_immed;
bits_19_12 = unordered & 0xff;
bit_11 = (unordered>>8) & 0x1;
bits_10_1 = (unordered >> 9) & 0x3ff;
bit_20 = (unordered>>19) & 0x1;
imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
inst.setSrcImm(signExt(imeed, 20, j_immed_mask));
usedImm = true;
trace_inst->valid_inst = true;
trace_inst->rd = ((code>>shift_rd) & reg_mask);
break;
defualt:
cout << "Unrecognized argument class in word decoder.\n";
exit(1);
}
if (haveRefs && usedImm && refMap.find(idx-n/8) != refMap.end()) {
Ref *srcRef = refMap[idx-n/8];
/* Create a new ref tied to this instruction. */
Ref *r = new SimpleRef(srcRef->name, *(Addr*)inst.setSrcImm(),
inst.hasRelImm());
inst.setImmRef(*r);
}
D(2, "Decoded 0x" << hex << code << " into: " << inst << '\n');
return &inst;
}

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#ifndef __ARCHDEF_H
#define __ARCHDEF_H
#include <string>
#include <sstream>
#include <cstdlib>
#include <stdio.h>
#include "types.h"
namespace Harp {
class ArchDef {
public:
struct Undefined {};
ArchDef(const std::string &s) {
std::istringstream iss(s.c_str());
wordSize = 4;
encChar = 'w';
nRegs = 32;
nPRegs = 0;
nThds = 8;
nWarps = 8;
extent = EXT_WARPS;
// if (!iss) { extent = EXT_NULL; return; }
// iss >> encChar;
// if (!iss) { extent = EXT_WORDSIZE; return; }
// iss >> nRegs;
// if (!iss) { extent = EXT_ENC; return; }
// char sep;
// iss >> sep >> nPRegs;
// if (!iss || sep != '/') { extent = EXT_REGS; return; }
// iss >> sep >> nThds;
// if (!iss || sep != '/') { extent = EXT_PREGS; return; }
// iss >> sep >> nWarps;
// if (!iss || sep != '/') { extent = EXT_THDS; return; }
// extent = EXT_WARPS;
}
operator std::string () const {
if (extent == EXT_NULL) return "";
std::ostringstream oss;
if (extent >= EXT_WORDSIZE) oss << wordSize;
if (extent >= EXT_ENC ) oss << encChar;
if (extent >= EXT_REGS ) oss << nRegs;
if (extent >= EXT_PREGS ) oss << '/' << nPRegs;
if (extent >= EXT_THDS ) oss << '/' << nThds;
if (extent >= EXT_WARPS ) oss << '/' << nWarps;
return oss.str();
}
bool operator==(const ArchDef &r) const {
Extent minExtent(r.extent > extent ? extent : r.extent);
// Can't be equal if we can't specify a binary encoding at all.
if (minExtent < EXT_PREGS) return false;
if (minExtent >= EXT_WORDSIZE) { if (wordSize!=r.wordSize) return false; }
if (minExtent >= EXT_ENC ) { if (encChar != r.encChar) return false; }
if (minExtent >= EXT_REGS ) { if (nRegs != r.nRegs) return false; }
if (minExtent >= EXT_PREGS ) { if (nPRegs != r.nPRegs) return false; }
if (minExtent >= EXT_THDS ) { if (nThds != r.nThds) return false; }
if (minExtent >= EXT_WARPS ) { if (nWarps != r.nWarps) return false; }
return true;
}
bool operator!=(const ArchDef &r) const { return !(*this == r); }
Size getWordSize() const {
if (extent < EXT_WORDSIZE) throw Undefined(); else return wordSize;
}
char getEncChar() const {
if (extent<EXT_ENC||encChar=='x') throw Undefined(); else return encChar;
}
RegNum getNRegs() const {
if (extent < EXT_REGS) throw Undefined(); else return nRegs;
}
RegNum getNPRegs() const {
if (extent < EXT_PREGS) throw Undefined(); else return nPRegs;
}
ThdNum getNThds() const {
if (extent < EXT_THDS) throw Undefined(); else return nThds;
}
ThdNum getNWarps() const {
if (extent < EXT_WARPS) throw Undefined(); else return nWarps;
}
private:
enum Extent {
EXT_NULL, EXT_WORDSIZE, EXT_ENC, EXT_REGS, EXT_PREGS, EXT_THDS, EXT_WARPS
};
Extent extent;
Size wordSize;
ThdNum nThds, nWarps;
RegNum nRegs, nPRegs;
char encChar;
};
};
#endif

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#ifndef __ARGS_H
#define __ARGS_H
#include <iostream>
#include <string>
#include <sstream>
#include <map>
namespace HarpTools {
struct BadArg { BadArg(std::string s) : arg(s) {} std::string arg; };
class CommandLineArg {
public:
CommandLineArg(std::string s, std::string l, const char *helpText);
CommandLineArg(std::string l, const char *helpText);
virtual int read(int argc, char** argv) = 0;
static void readArgs(int argc, char **argv);
static void clearArgs();
static void showHelp(std::ostream &os);
private:
static std::string helpString;
static std::map<std::string, CommandLineArg *> longArgs;
static std::map<std::string, CommandLineArg *> shortArgs;
};
template <typename T> class CommandLineArgSetter : public CommandLineArg {
public:
CommandLineArgSetter(std::string s, std::string l, const char *ht, T &x) :
CommandLineArg(s, l, ht), x(x) {}
CommandLineArgSetter(std::string l, const char *ht, T &x) :
CommandLineArg(l, ht), x(x) {}
int read(int argc, char **argv) {
std::istringstream iss(argv[1]);
iss >> x;
return 1;
}
private:
T &x;
};
class CommandLineArgFlag : public CommandLineArg {
public:
CommandLineArgFlag(std::string s, std::string l, const char *ht, bool &x) :
CommandLineArg(s, l, ht), x(x) { x = false; }
CommandLineArgFlag(std::string l, const char *ht, bool &x) :
CommandLineArg(l, ht), x(x) { x = false; }
int read(int argc, char **argv) { x = true; return 0; }
private:
bool &x;
};
};
#endif

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#ifndef HARPTOOL_ASM_TOKENS
#define HARPTOOL_ASM_TOKENS
namespace HarpTools {
enum AsmTokens {
ASM_T_DIR_DEF = 1, ASM_T_DIR_PERM, ASM_T_DIR_BYTE, ASM_T_DIR_WORD,
ASM_T_DIR_SPACE, ASM_T_DIR_STRING, ASM_T_DIR_ALIGN, ASM_T_DIR_ENTRY,
ASM_T_DIR_GLOBAL, ASM_T_DIR_ARG_NUM, ASM_T_DIR_ARG_STRING,
ASM_T_DIR_ARG_SYM, ASM_T_DIR_ARG_R, ASM_T_DIR_ARG_W, ASM_T_DIR_ARG_X,
ASM_T_DIR_END, ASM_T_LABEL, ASM_T_PRED, ASM_T_INST,
ASM_T_PREG, ASM_T_REG, ASM_T_REG_RA, ASM_T_REG_SP,
ASM_T_REG_FP, ASM_T_LIT, ASM_T_SYM, ASM_T_PEXP
};
};
#endif

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#ifndef __CORE_H
#define __CORE_H
#include <string>
#include <vector>
#include <stack>
#include <map>
#include <set>
#include "types.h"
#include "archdef.h"
#include "enc.h"
#include "mem.h"
#include "debug.h"
#include "Vcache_simX.h"
#include "verilated.h"
#ifdef VCD_OUTPUT
#include <verilated_vcd_c.h>
#endif
#include "trace.h"
namespace Harp {
#ifdef EMU_INSTRUMENTATION
void reg_doWrite(Word cpuId, Word regNum);
void reg_doRead(Word cpuId, Word regNum);
#endif
template <typename T> class Reg {
public:
Reg(): cpuId(0), regNum(0), val(0) {}
Reg(Word c, Word n): cpuId(c), regNum(n), val(0) {}
Reg &operator=(T r) { if (regNum) {val = r; doWrite();} return *this; }
operator T() const { doRead(); return val; }
void trunc(Size s) {
Word mask((~0ull >> (sizeof(Word)-s)*8));
val &= mask;
}
private:
Word cpuId, regNum;
T val;
#ifdef EMU_INSTRUMENTATION
/* Access size here is 8, representing the register size of 64-bit cores. */
void doWrite() const { reg_doWrite(cpuId, regNum); }
void doRead() const { reg_doRead(cpuId, regNum); }
#else
void doWrite() const {}
void doRead() const {}
#endif
};
// Entry in the IPDOM Stack
struct DomStackEntry {
DomStackEntry(
unsigned p, const std::vector<std::vector<Reg<Word> > >& m,
std::vector<bool> &tm, Word pc
): pc(pc), fallThrough(false), uni(false)
{
std::cout << "DomStackEntry TMASK: ";
for (unsigned i = 0; i < m.size(); ++i)
{
std::cout << " " << (!bool(m[i][p]) && tm[i]);
tmask.push_back(!bool(m[i][p]) && tm[i]);
}
std::cout << "\n";
}
DomStackEntry(const std::vector<bool> &tmask):
tmask(tmask), fallThrough(true), uni(false) {}
bool fallThrough;
bool uni;
std::vector<bool> tmask;
Word pc;
};
class Warp;
class Core {
public:
Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id=0);
Vcache_simX * cache_simulator;
bool interrupt(Word r0);
bool running() const;
void fetch();
void decode();
void scheduler();
void gpr_read();
void execute_unit();
void load_store();
void step();
void printStats() const;
const ArchDef &a;
Decoder &iDec;
MemoryUnit &mem;
Word interruptEntry;
unsigned long steps;
std::vector<Warp> w;
std::map<Word, std::set<Warp *> > b; // Barriers
};
class Warp {
public:
Warp(Core *c, Word id=0);
void step(trace_inst_t *);
bool interrupt(Word r0);
bool running() const { return activeThreads; }
#ifdef EMU_INSTRUMENTATION
bool getSupervisorMode() const { return supervisorMode; }
#endif
void printStats() const;
struct MemAccess {
MemAccess(bool w, Word a): wr(w), addr(a) {}
bool wr;
Word addr;
};
std::vector<MemAccess> memAccesses;
// private:
Core *core;
Word pc, shadowPc, id;
Size activeThreads, shadowActiveThreads;
std::vector<std::vector<Reg<Word> > > reg;
std::vector<std::vector<Reg<bool> > > pred;
std::vector<Reg<uint16_t> > csr;
std::vector<bool> tmask, shadowTmask;
std::stack<DomStackEntry> domStack;
std::vector<Word> shadowReg;
std::vector<bool> shadowPReg;
bool interruptEnable, shadowInterruptEnable, supervisorMode,
shadowSupervisorMode, spawned;
unsigned long steps, insts, loads, stores;
friend class Instruction;
};
};
#endif

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/*******************************************************************************
HARPtools by Chad D. Kersey, Spring 2013
*******************************************************************************/
#ifndef __DEBUG_H
#define __DEBUG_H
// #define USE_DEBUG 9
#define USE_DEBUG -1
#ifdef USE_DEBUG
#include <iostream>
#define D(lvl, x) do { \
using namespace std; \
if ((lvl) <= USE_DEBUG) { \
cout << "DEBUG " << __FILE__ << ':' << dec << __LINE__ << ": " \
<< x << endl; \
} \
} while(0)
#define D_RAW(x) do { \
std::cout << x; \
} while (0)
#else
#define D(lvl, x) do {} while(0)
#endif
#endif

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#ifndef __ENC_H
#define __ENC_H
#include <map>
#include "types.h"
#include "instruction.h"
#include "obj.h"
#include "trace.h"
// } trace_inst_t;
namespace Harp {
class DataChunk;
class TextChunk;
class Ref;
class Encoder {
public:
Encoder() {}
virtual ~Encoder() {}
virtual Size encode(Ref *&ref, std::vector<Byte> &v, Size n,
Instruction &i) = 0;
void encodeChunk(DataChunk &dest, const TextChunk &src);
};
class Decoder {
public:
Decoder() : haveRefs(false) {}
Decoder(const std::vector<Ref*> &refVec) : haveRefs(true) {
setRefs(refVec);
}
virtual ~Decoder() {}
void setRefs(const std::vector<Ref*> &);
void clearRefs() { refMap.clear(); }
virtual Instruction *decode(const std::vector<Byte> &v, Size &n, trace_inst_t * trace_inst) = 0;
virtual Instruction *decode(const std::vector<Byte> &v, Size &n) = 0;
void decodeChunk(TextChunk &dest, const DataChunk &src);
protected:
bool haveRefs;
std::map <Size, Ref*> refMap;
};
class WordDecoder : public Decoder {
public:
WordDecoder(const ArchDef &);
virtual Instruction *decode(const std::vector<Byte> &v, Size &n, trace_inst_t * trace_inst);
virtual Instruction *decode(const std::vector<Byte> &v, Size &n) {printf("Not implemented\n");}
private:
Size n, o, r, p, i1, i2, i3;
Word oMask, rMask, pMask, i1Mask, i2Mask, i3Mask;
// FARES
Size inst_s, opcode_s, reg_s, func3_s;
Size shift_opcode, shift_rd, shift_rs1, shift_rs2, shift_func3, shift_func7;
Size shift_j_u_immed, shift_s_b_immed, shift_i_immed;
Word reg_mask, func3_mask, func7_mask, opcode_mask, i_immed_mask,
s_immed_mask, b_immed_mask, u_immed_mask, j_immed_mask;
};
};
#endif

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#include <math.h>
#include <stdlib.h>
#include "types.h"
#ifdef DEBUG
#include <iostream>
#define DEBUGMSG(x) do { \
std::cout << __FILE__ << ':' <<__LINE__ << ": " << x << '\n'; \
} while(0)
#else
#define DEBUGMSG(x) do { } while(0)
#endif
namespace Harp {
// This class serves to handle the strange-precision floating point that can
// crop up in HARP.
class Float {
public:
Float(Word_u bin, Size n): sz(n) {
DEBUGMSG("Float(0x" << std::hex << bin << ", " << std::dec << n << ')');
bool sign(bin >> (n*8 - 1));
Size expSz;
if (n < 4) {
expSz = 5;
} else if (n < 8) {
expSz = 8;
} else {
expSz = 11;
}
Size sigSz = n*8 - expSz - 1;
DEBUGMSG(" exp: " << std::dec << expSz <<
" bits, sig: " << std::dec << sigSz << " bits.");
int exp = (bin >> sigSz) & ((1<<expSz) - 1);
Word_u sig = bin & ((1llu<<sigSz) - 1);
DEBUGMSG(" sig=" << std::dec << sig << " exp=" << exp);
if (exp == 0) {
// Subnormal
d = sig / pow(2, ((1<<(expSz-1))-2)) / pow(2, sigSz);
DEBUGMSG(" Denorm.");
} else if (exp == ((1<<expSz) - 1)) {
// Infinity
d = HUGE_VAL;
DEBUGMSG(" Inf.");
} else {
// Normalized, implied 1.
exp -= (1<<(expSz - 1)) - 1;
d = pow(2.0, exp - int(sigSz)) * double((1ll << sigSz) + sig);
DEBUGMSG(" Norm, exp=" << exp);
}
if (sign) d = -d;
DEBUGMSG("Set to " << d);
}
Float(double d, Size n): sz(n), d(d) { DEBUGMSG("Float(double, size)"); }
operator Word_u() {
DEBUGMSG("Float -> Word_u: " << d);
Size expSz;
if (sz < 4) {
expSz = 5;
} else if (sz < 8) {
expSz = 8;
} else {
expSz = 11;
}
Size sigSz = 8*sz - expSz - 1;
bool sign(d < 0);
bool inf(isinf(d)), zero(d == 0.0);
int exp;
if (!inf && !zero) exp = floor(log2(fabs(d)));
Word_u rval;
if (inf) {
// Infinity
DEBUGMSG(" Inf.");
rval = ((1llu<<expSz)-1llu)<<sigSz;
} else if (!zero && abs(exp) < (1<<(expSz-1)) - 1) {
// Normalized with implied 1.
Word_u sig = (fabs(d) * pow(2.0, -exp) - 1.0) * pow(2.0, sigSz);
DEBUGMSG(" Norm, exp=" << exp << ", sig=" << sig);
rval = ((((exp + ((1llu<<(expSz-1)) - 1llu))
&((1llu<<expSz)-1llu)))<<sigSz) | sig;
} else if (!zero && exp > -(1<<(expSz-1)) - sigSz) {
// Subnormal number.
Word_u sig = round(fabs(d)*pow(2.0,((1<<(expSz-1))-2))*pow(2.0, sigSz));
DEBUGMSG(" Denorm, exp=" << exp << ", sig=" << sig);
rval = sig;
} else {
// Zero.
rval = 0;
}
if (sign) rval |= 1llu<<(sz*8 - 1);
DEBUGMSG(" Returning 0x" << std::hex << rval);
return rval;
}
operator double() { DEBUGMSG("Float->double " << d); return d; }
private:
double d;
Size sz;
};
};

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#ifndef __HELP_H
#define __HELP_H
/* Help messages. */
namespace HarpTools {
namespace Help {
const char *mainHelp =
"--help, -h, no arguments\n"
" Print this message.\n"
"-E, --emu; -A, --asm; -L, --ld; -D, --disasm\n"
" Invoke the emulator, assembler, linker, and disassembler, "
"respectively.\n"
"<mode> --help\n"
" Display contextual help.\n",
*emuHelp = "HARP Emulator command line arguments:\n"
" -c, --core <filename> RAM image\n"
" -a, --arch <arch string> Architecture string\n"
" -s, --stats Print stats on exit.\n"
" -b, --basic Disable virtual memory.\n"
" -i, --batch Disable console input.\n",
*asmHelp = "HARP Assembler command line arguments:\n"
" -a, --arch <arch string>\n"
" -o, --output <filename>\n",
*ldHelp = "HARP Linker command line arguments:\n"
" -o, --output <filename>\n"
" -a, --arch <filename>\n"
" -f, --format <foramt string>\n"
" --offset <bytes>\n",
*disasmHelp = "HARP Disassembler command line arguments:\n"
" -a, --arch <arch string> Architecture string.\n"
" -o, --output <filename> Output filename.\n";
};
};
#endif

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#ifndef __INSTRUCTION_H
#define __INSTRUCTION_H
#include <map>
#include <iostream>
#include "types.h"
namespace Harp {
class Warp;
class Ref;
enum Opcode
{
NOP = 0,
R_INST = 51,
L_INST = 3,
I_INST = 19,
S_INST = 35,
B_INST = 99,
LUI_INST = 55,
AUIPC_INST = 23,
JAL_INST = 111,
JALR_INST = 103,
SYS_INST = 115,
TRAP = 0x7f,
FENCE = 0x0f,
PJ_INST = 0x7b,
GPGPU = 0x6b
};
enum InstType { N_TYPE, R_TYPE, I_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE};
// We build a table of instruction information out of this.
struct InstTableEntry_t {
const char *opString;
bool controlFlow, relAddress, allSrcArgs, privileged;
InstType iType;
};
static std::map<int, struct InstTableEntry_t> instTable =
{
{Opcode::NOP, {"nop" , false, false, false, false, InstType::N_TYPE }},
{Opcode::R_INST, {"r_type", false, false, false, false, InstType::R_TYPE }},
{Opcode::L_INST, {"load" , false, false, false, false, InstType::I_TYPE }},
{Opcode::I_INST, {"i_type", false, false, false, false, InstType::I_TYPE }},
{Opcode::S_INST, {"store" , false, false, false, false, InstType::S_TYPE }},
{Opcode::B_INST, {"branch", true , false, false, false, InstType::B_TYPE }},
{Opcode::LUI_INST, {"lui" , false, false, false, false, InstType::U_TYPE }},
{Opcode::AUIPC_INST, {"auipc" , false, false, false, false, InstType::U_TYPE }},
{Opcode::JAL_INST, {"jal" , true , false, false, false, InstType::J_TYPE }},
{Opcode::JALR_INST, {"jalr" , true , false, false, false, InstType::I_TYPE }},
{Opcode::SYS_INST, {"SYS" , true , false, false, false, InstType::I_TYPE }},
{Opcode::TRAP, {"TRAP" , true , false, false, false, InstType::I_TYPE }},
{Opcode::FENCE, {"fence" , true , false, false, false, InstType::I_TYPE }},
{Opcode::PJ_INST, {"pred j", true , false, false, false, InstType::R_TYPE }},
{Opcode::GPGPU, {"gpgpu" , false, false, false, false, InstType::R_TYPE }}
};
static const Size MAX_REG_SOURCES(3);
static const Size MAX_PRED_SOURCES(2);
class Instruction;
struct DivergentBranchException {};
struct DomainException {};
std::ostream &operator<<(std::ostream &, Instruction &);
class Instruction {
public:
Instruction() :
predicated(false), nRsrc(0), nPsrc(0), immsrcPresent(false),
rdestPresent(false), pdestPresent(false), refLiteral(NULL)
{
}
void executeOn(Warp &warp);
friend std::ostream &operator<<(std::ostream &, Instruction &);
/* Setters used to "craft" the instruction. */
void setOpcode (Opcode opc) { op = opc; }
void setPred (RegNum pReg) { predicated = true; pred = pReg; }
void setDestReg (RegNum destReg) { rdestPresent = true; rdest = destReg; }
void setSrcReg (RegNum srcReg) { rsrc[nRsrc++] = srcReg; }
void setFunc3 (Word func3) { this->func3 = func3; }
void setFunc7 (Word func7) { this->func7 = func7; }
void setDestPReg(RegNum dPReg) { pdestPresent = true; pdest = dPReg; }
void setSrcPReg (RegNum srcPReg) { psrc[nPsrc++] = srcPReg; }
Word *setSrcImm () { immsrcPresent = true; immsrc = 0xa5; return &immsrc;}
void setSrcImm (Word srcImm) { immsrcPresent = true; immsrc = srcImm; }
void setImmRef (Ref &r) { refLiteral = &r; }
/* Getters used by encoders. */
Opcode getOpcode() const { return op; }
bool hasPred() const { return predicated; }
RegNum getPred() const { return pred; }
RegNum getNRSrc() const { return nRsrc; }
RegNum getRSrc(RegNum i) const { return rsrc[i]; }
RegNum getNPSrc() const { return nPsrc; }
RegNum getPSrc(RegNum i) const { return psrc[i]; }
bool hasRDest() const { return rdestPresent; }
RegNum getRDest() const { return rdest; }
bool hasPDest() const { return pdestPresent; }
RegNum getPDest() const { return pdest; }
bool hasImm() const { return immsrcPresent; }
Word getImm() const { return immsrc; }
bool hasRefLiteral() const { return refLiteral != NULL; }
Ref *getRefLiteral() const { return refLiteral; }
/* Getters used as table lookup. */
bool hasRelImm() const { return (*(instTable.find(op))).second.relAddress; }
private:
bool predicated;
RegNum pred;
Opcode op;
int nRsrc, nPsrc;
RegNum rsrc[MAX_REG_SOURCES], psrc[MAX_PRED_SOURCES];
bool immsrcPresent;
Word immsrc;
Word func3;
Word func7;
bool rdestPresent, pdestPresent;
RegNum rdest, pdest;
Ref *refLiteral;
public:
};
};
#endif
// static struct InstTableEntry {
// const char *opString;
// bool controlFlow, relAddress, allSrcArgs, privileged;
// InstType iType;
// };

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#ifndef __MEM_H
#define __MEM_H
#include <ostream>
#include <vector>
#include <queue>
#include <map>
#include <pthread.h>
#include "types.h"
namespace Harp {
void *consoleInputThread(void *);
struct BadAddress {};
class MemDevice {
public:
virtual ~MemDevice() {}
virtual Size size() const = 0;
virtual Word read(Addr) = 0;
virtual void write(Addr, Word) = 0;
virtual Byte *base() { return NULL; } /* Null if unavailable. */
};
class RamMemDevice : public MemDevice {
public:
RamMemDevice(Size size, Size wordSize);
RamMemDevice(const char* filename, Size wordSize);
~RamMemDevice() {}
virtual Size size() const { return contents.size(); };
virtual Word read(Addr);
virtual void write(Addr, Word);
virtual Byte *base() { return &contents[0]; }
protected:
Size wordSize;
std::vector<Byte> contents;
};
class RomMemDevice : public RamMemDevice {
public:
RomMemDevice(const char* filename, Size wordSize) :
RamMemDevice(filename, wordSize) {}
RomMemDevice(Size size, Size wordSize) :
RamMemDevice(size, wordSize) {}
~RomMemDevice();
virtual void write(Addr, Word);
};
class Core;
class ConsoleMemDevice : public MemDevice {
public:
ConsoleMemDevice(Size wS, std::ostream &o, Core &core, bool batch = false);
~ConsoleMemDevice() {}
//virtual Size wordSize() const { return wordSize; }
virtual Size size() const { return wordSize; }
virtual Word read(Addr) { pthread_mutex_lock(&cBufLock);
char c = cBuf.front();
cBuf.pop();
pthread_mutex_unlock(&cBufLock);
return Word(c); }
virtual void write(Addr a, Word w) { output << char(w); }
void poll();
friend void *Harp::consoleInputThread(void *);
private:
std::ostream &output;
Size wordSize;
Core &core;
std::queue<char> cBuf;
pthread_mutex_t cBufLock;
};
class DiskControllerMemDevice : public MemDevice {
public:
DiskControllerMemDevice(Size wordSize, Size blockSize, Core &c) :
wordSize(wordSize), blockSize(blockSize), core(c), disks() {}
void addDisk(Byte *file, Size n) { disks.push_back(Disk(file, n)); }
virtual Size size() const { return wordSize * 6; }
virtual Word read(Addr);
virtual void write(Addr, Word);
private:
Word curDisk, curBlock, nBlocks, physAddr, command, status;
enum Status { OK = 0, INVALID_DISK, INVALID_BLOCK };
struct Disk {
Disk(Byte *f, Size n): file(f), blocks(n) {}
Byte *file;
Size blocks;
};
std::vector <Disk> disks;
Core &core;
Size wordSize, blockSize;;
};
class MemoryUnit {
public:
MemoryUnit(Size pageSize, Size addrBytes, bool disableVm = false) :
pageSize(pageSize), addrBytes(addrBytes), ad(), disableVm(disableVm)
{
if (!disableVm)
tlb[0] = TLBEntry(0, 077);
}
void attach(MemDevice &m, Addr base);
//Size wordSize();
struct PageFault {
PageFault(Addr a, bool nf) : faultAddr(a), notFound(nf) {}
Addr faultAddr;
bool notFound;
}; /* Thrown on page fault. */
Word read(Addr, bool sup); /* For data accesses. */
Word fetch(Addr, bool sup); /* For instruction accesses. */
Byte *getPtr(Addr, Size);
void write(Addr, Word, bool sup, Size);
void tlbAdd(Addr virt, Addr phys, Word flags);
void tlbRm(Addr va);
void tlbFlush() { tlb.clear(); }
#ifdef EMU_INSTRUMENTATION
Addr virtToPhys(Addr va);
#endif
private:
class ADecoder {
public:
ADecoder() : zeroChild(NULL), oneChild(NULL), range(0) {}
ADecoder(MemDevice &md, Size range) :
zeroChild(NULL), oneChild(NULL), range(range), md(&md) {}
Byte *getPtr(Addr a, Size sz, Size wordSize);
Word read(Addr a, bool sup, Size wordSize);
void write(Addr a, Word w, bool sup, Size wordSize);
void map(Addr a, MemDevice &md, Size range, Size bit);
private:
MemDevice &doLookup(Addr a, Size &bit);
ADecoder *zeroChild, *oneChild;
MemDevice *md;
Size range;
};
ADecoder ad;
struct TLBEntry {
TLBEntry() {}
TLBEntry(Word pfn, Word flags): pfn(pfn), flags(flags) {}
Word flags;
Word pfn;
};
std::map<Addr, TLBEntry> tlb;
TLBEntry tlbLookup(Addr vAddr, Word flagMask);
Size pageSize, addrBytes;
bool disableVm;
};
class RAM : public MemDevice {
public:
uint8_t* mem[1 << 12];
RAM(){
for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL;
}
~RAM(){
for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i];
}
void clear(){
for(uint32_t i = 0;i < (1 << 12);i++)
{
if(mem[i])
{
delete mem[i];
mem[i] = NULL;
}
}
}
uint8_t* get(uint32_t address){
if(mem[address >> 20] == NULL) {
uint8_t* ptr = new uint8_t[1024*1024];
for(uint32_t i = 0;i < 1024*1024;i+=4) {
ptr[i + 0] = 0xaa;
ptr[i + 1] = 0xbb;
ptr[i + 2] = 0xcc;
ptr[i + 3] = 0xdd;
}
mem[address >> 20] = ptr;
}
return &mem[address >> 20][address & 0xFFFFF];
}
void read(uint32_t address,uint32_t length, uint8_t *data){
for(unsigned i = 0;i < length;i++){
data[i] = (*this)[address + i];
}
}
void write(uint32_t address,uint32_t length, uint8_t *data){
for(unsigned i = 0;i < length;i++){
(*this)[address + i] = data[i];
}
}
virtual Size size() const { return (1<<31); };
void getBlock(uint32_t address, uint8_t *data)
{
uint32_t block_number = address & 0xffffff00; // To zero out block offset
uint32_t bytes_num = 256;
this->read(block_number, bytes_num, data);
}
void getWord(uint32_t address, uint32_t * data)
{
data[0] = 0;
uint8_t first = *get(address + 0);
uint8_t second = *get(address + 1);
uint8_t third = *get(address + 2);
uint8_t fourth = *get(address + 3);
// std::cout << std::hex;
// std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << (uint32_t) first << "\n";
// std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << (uint32_t) second << "\n";
// std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << (uint32_t) third << "\n";
// std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << (uint32_t) fourth << "\n";
data[0] = (data[0] << 0) | fourth;
data[0] = (data[0] << 8) | third;
data[0] = (data[0] << 8) | second;
data[0] = (data[0] << 8) | first;
// data[0] = (data[0] << 0) | first;
// data[0] = (data[0] << 8) | second;
// data[0] = (data[0] << 8) | third;
// data[0] = (data[0] << 8) | fourth;
// std::cout << "FINAL DATA: " << data[0] << "\n";
}
void writeWord(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 4; i++)
{
// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeHalf(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 2; i++)
{
// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeByte(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
(*this)[address] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
uint8_t& operator [](uint32_t address) {
return *get(address);
}
virtual void write(Addr addr, Word w)
{
uint32_t word = (uint32_t) w;
writeWord(addr, &word);
}
virtual Word read(Addr addr)
{
uint32_t w;
getWord(addr, &w);
// std::cout << "RAM: read -> " << w << " at addr: " << addr << "\n";
return (Word) w;
}
virtual Byte *base()
{
return (Byte *) this->get(0);
}
// MEMORY UTILS
uint32_t hti_old(char c) {
if (c >= 'A' && c <= 'F')
return c - 'A' + 10;
if (c >= 'a' && c <= 'f')
return c - 'a' + 10;
return c - '0';
}
uint32_t hToI_old(char *c, uint32_t size) {
uint32_t value = 0;
for (uint32_t i = 0; i < size; i++) {
value += hti_old(c[i]) << ((size - i - 1) * 4);
}
return value;
}
void loadHexImpl(std::string path) {
this->clear();
FILE *fp = fopen(&path[0], "r");
if(fp == 0){
std::cout << path << " not found" << std::endl;
}
//Preload 0x0 <-> 0x80000000 jumps
((uint32_t*)this->get(0))[0] = 0xf1401073;
((uint32_t*)this->get(0))[1] = 0xf1401073;
// ((uint32_t*)this->get(0))[1] = 0xf1401073;
((uint32_t*)this->get(0))[2] = 0x30101073;
((uint32_t*)this->get(0))[3] = 0x800000b7;
((uint32_t*)this->get(0))[4] = 0x000080e7;
((uint32_t*)this->get(0x80000000))[0] = 0x00000097;
((uint32_t*)this->get(0xb0000000))[0] = 0x01C02023;
// F00FFF10
((uint32_t*)this->get(0xf00fff10))[0] = 0x12345678;
fseek(fp, 0, SEEK_END);
uint32_t size = ftell(fp);
fseek(fp, 0, SEEK_SET);
char* content = new char[size];
int x = fread(content, 1, size, fp);
if (!x) { std::cout << "COULD NOT READ FILE\n"; exit(1);}
int offset = 0;
char* line = content;
// std::cout << "WHTA\n";
while (1) {
if (line[0] == ':') {
uint32_t byteCount = hToI_old(line + 1, 2);
uint32_t nextAddr = hToI_old(line + 3, 4) + offset;
uint32_t key = hToI_old(line + 7, 2);
switch (key) {
case 0:
for (uint32_t i = 0; i < byteCount; i++) {
unsigned add = nextAddr + i;
*(this->get(add)) = hToI_old(line + 9 + i * 2, 2);
// std::cout << "lhi: Address: " << std::hex <<(add) << "\tValue: " << std::hex << hToI_old(line + 9 + i * 2, 2) << std::endl;
}
break;
case 2:
// cout << offset << endl;
offset = hToI_old(line + 9, 4) << 4;
break;
case 4:
// cout << offset << endl;
offset = hToI_old(line + 9, 4) << 16;
break;
default:
// cout << "??? " << key << endl;
break;
}
}
while (*line != '\n' && size != 0) {
line++;
size--;
}
if (size <= 1)
break;
line++;
size--;
}
if (content) delete[] content;
}
};
};
#endif

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#ifndef __OBJ_H
#define __OBJ_H
#include <iostream>
#include <string>
#include <vector>
#include <list>
#include <stdlib.h>
#include "types.h"
#include "archdef.h"
#include "instruction.h"
#include "enc.h"
#include "asm-tokens.h"
namespace Harp {
class Decoder;
class Encoder;
class Ref {
public:
std::string name;
Ref(const std::string &n, bool r, Size ib = 0):
name(n), bound(false), relative(r), ibase(ib) { }
virtual ~Ref() { }
virtual void bind(Addr addr, Addr base = 0) = 0;
virtual Addr getAddr() const = 0;
bool bound, relative;
Size ibase;
};
/* Used in not-yet-encoded code objects, plain old data. */
class SimpleRef : public Ref {
public:
SimpleRef(const std::string &name, Addr &addr, bool rel = false) :
Ref(name, rel), addr(addr) { }
virtual void bind(Addr addr, Addr base = 0) {
std::cout << "Attempted to bind a SimpleRef.\n";
exit(1);
}
virtual Addr getAddr() const { return this->addr; }
Byte *getAddrPtr() { return (Byte*)&addr; }
private:
Addr &addr;
};
// /* Used in already-encoded code objects. */
// class OffsetRef : public Ref {
// public:
// OffsetRef(
// const std::string &name, std::vector<Byte> &v, Size offset, Size bits,
// Size ws, bool rel = false, Size ibase = 0
// ) : Ref(name, rel, ibase), data(v), offset(offset), bits(bits), wordSize(ws)
// {}
// virtual void bind(Addr addr, Addr base = 0) {
// Size bytes(bits/8), remainder(bits%8);
// if (relative) {
// addr = addr - base;
// Word_s addr_s(addr);
// if ((addr_s >> bits) != ~0ull && (addr_s >> bits) != 0) goto noFit;
// } else {
// Addr mask = (1ull<<bits)-1;
// if (addr > mask) goto noFit;
// }
// { Byte mask((1ull<<remainder) - 1);
// Size i;
// for (i = 0; i < bytes; i++) {
// data[offset+i] = addr & 0xff;
// addr >>= 8;
// }
// data[offset+i] &= ~mask;
// data[offset+i] |= (addr&mask);
// bound = true;
// }
// return;
// noFit:
// std::cout << "Attempt to bind a " << bits << "-bit "
// << (relative?"":"non-") << "relative symbol to an address"
// " it cannot reach.\n";
// exit(1);
// }
// virtual Addr getAddr() const {
// Size bytes = bits/8, remainder = bits%8;
// Byte mask((1<<remainder)-1);
// Addr a(data[offset]&mask);
// for (Size i = 0; i < bytes-1; i++) {
// a |= data[offset + bytes - i - 1];
// a <<= 8;
// }
// return a;
// }
// Size getOffset() const { return offset; }
// Size getBits() const { return bits; }
// private:
// std::vector<Byte> &data;
// Size offset, bits, wordSize;
// };
// class Chunk {
// public:
// Chunk(std::string n, Size a = 0, Word f = 0) :
// name(n), alignment(a), bound(false), flags(f), global(false) {}
// virtual ~Chunk() { for (Size i = 0; i < refs.size(); i++) delete refs[i]; }
// void bind(Addr a) { address = a; bound = true; }
// void setGlobal() { global = true; }
// bool isGlobal() const { return global; }
// std::string name;
// Size alignment;
// bool bound, global;
// Addr address;
// Word flags;
// std::vector<Ref*> refs;
// };
// class TextChunk : public Chunk {
// public:
// TextChunk(std::string n, Size a = 0, Word f = 0)
// : Chunk(n, a, f), instructions() {}
// ~TextChunk() {
// for (Size i = 0; i < instructions.size(); i++) delete instructions[i];
// }
// std::vector<Instruction*> instructions;
// };
// class DataChunk : public Chunk {
// public:
// DataChunk(std::string n, Size a = 0, Word f = 0)
// : Chunk(n, a, f), size(0), contents() {}
// Size size;
// std::vector<Byte> contents; /* 0 to size bytes in length. */
// };
// class Obj {
// public:
// ~Obj() { for (Size i = 0; i < chunks.size(); i++) delete chunks[i]; }
// std::vector<Chunk*> chunks;
// Size entry;
// };
// class DynObj : public Obj {
// public:
// std::vector<std::string> deps;
// };
// class ObjReader {
// public:
// virtual Obj *read(std::istream &input) = 0;
// private:
// };
// class ObjWriter {
// public:
// virtual void write(std::ostream &output, const Obj &o) = 0;
// private:
// };
// class AsmReader : public ObjReader {
// public:
// AsmReader(ArchDef arch) :
// wordSize(arch.getWordSize()), nRegs(arch.getNRegs()) {}
// virtual Obj *read(std::istream &input);
// private:
// Size wordSize, nRegs;
// // Operand type sequences indexed by argument class
// enum ArgType {AT_END, AT_REG, AT_PREG, AT_LIT};
// static ArgType operandtype_table[][4]; // ArgClass -> ArgType[arg_idx]
// };
// class HOFReader : public ObjReader {
// public:
// HOFReader(ArchDef &arch) : arch(arch) {}
// Obj *read(std::istream &input);
// private:
// const ArchDef &arch;
// };
// class AsmWriter : public ObjWriter {
// public:
// AsmWriter(ArchDef arch): wordSize(arch.getWordSize()) {}
// virtual void write(std::ostream &output, const Obj &obj);
// private:
// Size wordSize;
// };
// class HOFWriter : public ObjWriter {
// public:
// HOFWriter(ArchDef &arch) : arch(arch) {}
// virtual void write(std::ostream &output, const Obj &obj);
// private:
// const ArchDef &arch;
// };
};
#endif

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#ifndef EMU_INSTRUMENTATION
#define EMU_INSTRUMENTATION
#endif
#ifndef __QSIM_HARP_H
#define __QSIM_HARP_H
#include "types.h"
#include "core.h"
#include "enc.h"
#include "instruction.h"
#include "mem.h"
#include "obj.h"
#include "archdef.h"
#include <stdint.h>
#include <iostream>
#include <vector>
#include <string>
#include <qsim.h>
namespace Harp {
class OSDomain {
public:
OSDomain(Harp::ArchDef &arch, std::string imgFile);
bool idle(unsigned i) const { return cpus[i].idle(); }
int get_tid(unsigned i) const { return cpus[i].get_tid(); }
bool get_prot(unsigned i) const { return cpus[i].get_prot(); }
int get_n() const { return cpus.size(); }
uint64_t run(unsigned i, uint64_t n) { return cpus[i].run(n); }
void connect_console(std::ostream &s);
void timer_interrupt() { /* TODO: timer convention */ }
void interrupt(unsigned i, int vec) { cpus[i].interrupt(vec); }
bool booted(unsigned i) const { return cpus[i].booted(); }
void save_state(const char* state_file);
template <typename T>
void set_atomic_cb
(T *p, typename Qsim::OSDomain::atomic_cb_obj<T>::atomic_cb_t f)
{
atomic_cbs.push_back(new Qsim::OSDomain::atomic_cb_obj<T>(p, f));
}
template <typename T>
void set_inst_cb
(T* p, typename Qsim::OSDomain::inst_cb_obj<T>::inst_cb_t f)
{
inst_cbs.push_back(new Qsim::OSDomain::inst_cb_obj<T>(p, f));
}
template <typename T>
void set_int_cb
(T *p, typename Qsim::OSDomain::int_cb_obj<T>::int_cb_t f)
{
int_cbs.push_back(new Qsim::OSDomain::int_cb_obj<T>(p, f));
}
template <typename T>
void set_mem_cb
(T *p, typename Qsim::OSDomain::mem_cb_obj<T>::mem_cb_t f)
{
mem_cbs.push_back(new Qsim::OSDomain::mem_cb_obj<T>(p, f));
}
template <typename T>
void set_magic_cb
(T *p, typename Qsim::OSDomain::magic_cb_obj<T>::magic_cb_t f)
{
magic_cbs.push_back(new Qsim::OSDomain::magic_cb_obj<T>(p, f));
}
template <typename T>
void set_io_cb
(T *p, typename Qsim::OSDomain::io_cb_obj<T>::io_cb_t f)
{ /* Do nothing. We have no separate IO address space. */ }
template <typename T>
void set_reg_cb
(T *p, typename Qsim::OSDomain::reg_cb_obj<T>::reg_cb_t f)
{
reg_cbs.push_back(new Qsim::OSDomain::reg_cb_obj<T>(p, f));
}
template <typename T> void mem_rd(T& d, uint64_t paddr);
template <typename T> void mem_rd_virt(unsigned i, T& d, uint64_t vaddr);
template <typename T> void mem_wr(T& d, uint64_t paddr);
template <typename T> void mem_wr_virt(unsigned i, T& d, uint64_t vaddr);
static OSDomain *osDomain;
bool do_atomic(unsigned c) {
bool rval(false);
for (unsigned i = 0; i < atomic_cbs.size(); ++i)
if ((*atomic_cbs[i])(c)) rval = true;
return rval;
}
void do_inst(unsigned c, uint64_t va, uint64_t pa, uint8_t l,
const uint8_t *b, enum inst_type t)
{
for (unsigned i = 0; i < inst_cbs.size(); ++i)
(*inst_cbs[i])(c, va, pa, l, b, t);
}
void do_int(unsigned c, int v) {
for (unsigned i = 0; i < int_cbs.size(); ++i)
(*int_cbs[i])(c, v);
}
void do_mem(unsigned c, uint64_t va, uint64_t pa, uint8_t s, bool w) {
for (unsigned i = 0; i < mem_cbs.size(); ++i)
(*mem_cbs[i])(c, va, pa, s, w);
}
bool do_magic(unsigned c, uint64_t r0) {
bool rval(false);
for (unsigned i = 0; i < magic_cbs.size(); ++i)
if ((*magic_cbs[i])(c, r0)) rval = true;
return rval;
}
void do_reg(unsigned c, int r, uint8_t s, bool w) {
for (unsigned i = 0; i < reg_cbs.size(); ++i)
(*reg_cbs[i])(c, r, s, w);
}
private:
class Cpu {
public:
Cpu(Harp::OSDomain &osd);
Cpu(): dec(NULL), core(NULL) {}
~Cpu() { if (dec) delete dec; if (core) delete core; }
bool idle() const { return false; }
int get_tid() const { return 0; }
bool get_prot() const { return core->getSupervisorMode(); }
uint64_t run(uint64_t n);
void interrupt(int vec) { core->interrupt(vec); }
bool booted() const { return core->running(); }
Harp::OSDomain *osd;
Harp::Decoder *dec;
Harp::Core *core;
};
Harp::ArchDef arch;
Harp::MemoryUnit mu;
Harp::RamMemDevice ram;
Harp::ConsoleMemDevice *console;
std::vector <Harp::OSDomain::Cpu> cpus;
std::vector <Qsim::OSDomain::atomic_cb_obj_base*> atomic_cbs;
std::vector <Qsim::OSDomain::inst_cb_obj_base*> inst_cbs;
std::vector <Qsim::OSDomain::int_cb_obj_base*> int_cbs;
std::vector <Qsim::OSDomain::mem_cb_obj_base*> mem_cbs;
std::vector <Qsim::OSDomain::magic_cb_obj_base*> magic_cbs;
std::vector <Qsim::OSDomain::reg_cb_obj_base*> reg_cbs;
};
};
#endif

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#pragma once
namespace Harp {
typedef struct
{
// Warp step
bool valid_inst;
unsigned pc;
// Core scheduler
int wid;
// Encoder
int rs1;
int rs2;
int rd;
// Instruction execute
bool is_lw;
bool is_sw;
unsigned * mem_addresses;
// dmem interface
int mem_stall_cycles;
int fetch_stall_cycles;
// Instruction execute
bool stall_warp;
} trace_inst_t;
}

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#ifndef __TYPES_H
#define __TYPES_H
#include <stdint.h>
namespace Harp {
typedef uint8_t Byte;
typedef uint32_t Word;
typedef uint32_t Word_u;
typedef int32_t Word_s;
typedef Word_u Addr;
typedef Word_u Size;
typedef unsigned RegNum;
typedef unsigned ThdNum;
enum MemFlags {RD_USR = 1, WR_USR = 2, EX_USR = 4,
RD_SUP = 8, WR_SUP = 16, EX_SUP = 32};
};
#endif

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#ifndef __UTIL_H
#define __UTIL_H
#include <vector>
#include "types.h"
namespace Harp {
Word_u bytesToWord(const Byte *b, Size wordSize);
void wordToBytes(Byte *b, Word_u w, Size wordSize);
Word_u flagsToWord(bool r, bool w, bool x);
void wordToFlags(bool &r, bool &w, bool &x, Word_u f);
class OutOfBytes {};
Byte readByte(const std::vector<Byte> &b, Size &n);
Word_u readWord(const std::vector<Byte> &b, Size &n, Size wordSize);
void writeByte(std::vector<Byte> &p, Size &n, Byte b);
void writeWord(std::vector<Byte> &p, Size &n, Size wordSize, Word w);
};
#endif

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#include <iostream>
#include <stdlib.h>
#include "include/instruction.h"
#include "include/obj.h"
#include "include/core.h"
#include "include/harpfloat.h"
#include "include/debug.h"
#ifdef EMU_INSTRUMENTATION
#include "include/qsim-harp.h"
#endif
using namespace Harp;
using namespace std;
/* It is important that this stays consistent with the Harp::Instruction::Opcode
enum. */
ostream &Harp::operator<<(ostream& os, Instruction &inst) {
os << dec;
// if (inst.predicated) {
// os << "@p" << dec << inst.pred << " ? ";
// }
// os << inst.instTable[inst.op].opString << ' ';
// if (inst.rdestPresent) os << "%r" << dec << inst.rdest << ' ';
// if (inst.pdestPresent) os << "@p" << inst.pdest << ' ';
// for (int i = 0; i < inst.nRsrc; i++) {
// os << "%r" << dec << inst.rsrc[i] << ' ';
// }
// for (int i = 0; i < inst.nPsrc; i++) {
// os << "@p" << dec << inst.psrc[i] << ' ';
// }
// if (inst.immsrcPresent) {
// if (inst.refLiteral) os << inst.refLiteral->name;
// else os << "#0x" << hex << inst.immsrc;
// }
os << instTable[inst.op].opString;
os << ';';
return os;
}
bool checkUnanimous(unsigned p, const std::vector<std::vector<Reg<Word> > >& m,
const std::vector<bool> &tm) {
bool same;
unsigned i;
for (i = 0; i < m.size(); ++i) {
if (tm[i]) {
same = m[i][p];
break;
}
}
if (i == m.size()) throw DivergentBranchException();
//std::cout << "same: " << same << " with -> ";
for (; i < m.size(); ++i) {
if (tm[i]) {
//std::cout << " " << (bool(m[i][p]));
if (same != (bool(m[i][p]))) {
//std::cout << " FALSE\n";
return false;
}
}
}
//std::cout << " TRUE\n";
return true;
}
Word signExt(Word w, Size bit, Word mask) {
if (w>>(bit-1)) w |= ~mask;
return w;
}
void Instruction::executeOn(Warp &c) {
D(3, "Begin instruction execute.");
/* If I try to execute a privileged instruction in user mode, throw an
exception 3. */
if (instTable[op].privileged && !c.supervisorMode) {
std::cout << "INTERRUPT SUPERVISOR\n";
c.interrupt(3);
return;
}
// /* Also throw exceptions on non-masked divergent branches. */
// if (instTable[op].controlFlow) {
// Size t, count, active;
// for (t = 0, count = 0, active = 0; t < c.activeThreads; ++t) {
// if ((!predicated || c.pred[t][pred]) && c.tmask[t]) ++count;
// if (c.tmask[t]) ++active;
// }
// if (count != 0 && count != active)
// throw DivergentBranchException();
// }
Size nextActiveThreads = c.activeThreads;
Size wordSz = c.core->a.getWordSize();
Word nextPc = c.pc;
c.memAccesses.clear();
// If we have a load, overwriting a register's contents, we have to make sure
// ahead of time it will not fault. Otherwise we may perform an indirect load
// by mistake.
// if (op == L_INST && rdest == rsrc[0]) {
// for (Size t = 0; t < c.activeThreads; t++) {
// if ((!predicated || c.pred[t][pred]) && c.tmask[t]) {
// Word memAddr = c.reg[t][rsrc[0]] + immsrc;
// c.core->mem.read(memAddr, c.supervisorMode);
// }
// }
// }
bool sjOnce(true), // Has not yet split or joined once.
pcSet(false); // PC has already been set
for (Size t = 0; t < c.activeThreads; t++) {
vector<Reg<Word> > &reg(c.reg[t]);
vector<Reg<bool> > &pReg(c.pred[t]);
stack<DomStackEntry> &domStack(c.domStack);
//std::cout << std::hex << "opcode: " << op << " func3: " << func3 << "\n";
//if (op == GPGPU) //std::cout << "OPCODE MATCHED GPGPU\n";
// If this thread is masked out, don't execute the instruction, unless it's
// a split or join.
// if (((predicated && !pReg[pred]) || !c.tmask[t]) &&
// op != SPLIT && op != JOIN) continue;
bool split = (op == GPGPU) && (func3 == 2);
bool join = (op == GPGPU) && (func3 == 3);
// predicated = (op == GPGPU) && ((func3 == 7) || (func3 == 2));
// bool is_branch = (op == B_INST);
// bool is_jump = (op == JAL_INST) || (op == JALR_INST);
bool is_gpgpu = (op == GPGPU);
bool is_tmc = is_gpgpu && (func3 == 0);
bool is_wspawn = is_gpgpu && (func3 == 1);
bool is_barrier = is_gpgpu && (func3 == 4);
bool is_split = is_gpgpu && (func3 == 2);
bool is_join = is_gpgpu && (func3 == 3);
bool gpgpu_zero = (is_tmc || is_barrier || is_wspawn) && (t != 0);
bool not_active = !c.tmask[t];
if (not_active || gpgpu_zero)
{
continue;
}
// printf("Predicated: %d, split: %d, join: %d\n",predicated, split, join );
// printf("%d && ((%d) || (%d))\n",(op == GPGPU), (func3 == 7), (func3 == 2) );
// cout << "before " << op << " = " << GPGPU << "\n";
// if (((predicated && !reg[pred]) || !c.tmask[t]) && !split && !join)
// {
// // cout << "about to continue\n";
// continue;
// }
// cout << "after\n";
++c.insts;
Word memAddr;
Word shift_by;
Word shamt;
Word temp;
Word data_read;
int op1, op2;
bool m_exten;
// std::cout << "op = " << op << "\n";
// std::cout << "R_INST: " << R_INST << "\n";
int num_to_wspawn;
switch (op) {
case NOP:
//std::cout << "NOP_INST\n";
break;
case R_INST:
// std::cout << "R_INST\n";
m_exten = func7 & 0x1;
if (m_exten)
{
// std::cout << "FOUND A MUL/DIV\n";
switch (func3)
{
case 0:
// MUL
// cout << "MUL\n";
reg[rdest] = ((int) reg[rsrc[0]]) * ((int) reg[rsrc[1]]);
break;
case 1:
// MULH
{
int64_t first = (int64_t) reg[rsrc[0]];
if (reg[rsrc[0]] & 0x80000000)
{
first = first | 0xFFFFFFFF00000000;
}
int64_t second = (int64_t) reg[rsrc[1]];
if (reg[rsrc[1]] & 0x80000000)
{
second = second | 0xFFFFFFFF00000000;
}
// cout << "mulh: " << std::dec << first << " * " << second;
uint64_t result = first * second;
reg[rdest] = ( result >> 32) & 0xFFFFFFFF;
// cout << " = " << result << " or " << reg[rdest] << "\n";
}
break;
case 2:
// MULHSU
{
int64_t first = (int64_t) reg[rsrc[0]];
if (reg[rsrc[0]] & 0x80000000)
{
first = first | 0xFFFFFFFF00000000;
}
int64_t second = (int64_t) reg[rsrc[1]];
reg[rdest] = (( first * second ) >> 32) & 0xFFFFFFFF;
}
break;
case 3:
// MULHU
{
uint64_t first = (uint64_t) reg[rsrc[0]];
uint64_t second = (uint64_t) reg[rsrc[1]];
// cout << "MULHU\n";
reg[rdest] = (( first * second) >> 32) & 0xFFFFFFFF;
}
break;
case 4:
// DIV
if (reg[rsrc[1]] == 0)
{
reg[rdest] = -1;
break;
}
// cout << "dividing: " << dec << ((int) reg[rsrc[0]]) << " / " << ((int) reg[rsrc[1]]);
reg[rdest] = ( (int) reg[rsrc[0]]) / ( (int) reg[rsrc[1]]);
// cout << " = " << ((int) reg[rdest]) << "\n";
break;
case 5:
// DIVU
if (reg[rsrc[1]] == 0)
{
reg[rdest] = -1;
break;
}
reg[rdest] = ((uint32_t) reg[rsrc[0]]) / ((uint32_t) reg[rsrc[1]]);
break;
case 6:
// REM
if (reg[rsrc[1]] == 0)
{
reg[rdest] = reg[rsrc[0]];
break;
}
reg[rdest] = ((int) reg[rsrc[0]]) % ((int) reg[rsrc[1]]);
break;
case 7:
// REMU
if (reg[rsrc[1]] == 0)
{
reg[rdest] = reg[rsrc[0]];
break;
}
reg[rdest] = ((uint32_t) reg[rsrc[0]]) % ((uint32_t) reg[rsrc[1]]);
break;
default:
cout << "unsupported MUL/DIV instr\n";
exit(1);
}
}
else
{
// std::cout << "NORMAL R-TYPE\n";
switch (func3)
{
case 0:
if (func7)
{
reg[rdest] = reg[rsrc[0]] - reg[rsrc[1]];
reg[rdest].trunc(wordSz);
}
else
{
reg[rdest] = reg[rsrc[0]] + reg[rsrc[1]];
reg[rdest].trunc(wordSz);
}
break;
case 1:
reg[rdest] = reg[rsrc[0]] << reg[rsrc[1]];
reg[rdest].trunc(wordSz);
break;
case 2:
if ( int(reg[rsrc[0]]) < int(reg[rsrc[1]]))
{
reg[rdest] = 1;
}
else
{
reg[rdest] = 0;
}
break;
case 3:
if ( Word_u(reg[rsrc[0]]) < Word_u(reg[rsrc[1]]))
{
reg[rdest] = 1;
}
else
{
reg[rdest] = 0;
}
break;
case 4:
reg[rdest] = reg[rsrc[0]] ^ reg[rsrc[1]];
break;
case 5:
if (func7)
{
reg[rdest] = int(reg[rsrc[0]]) >> int(reg[rsrc[1]]);
reg[rdest].trunc(wordSz);
}
else
{
reg[rdest] = Word_u(reg[rsrc[0]]) >> Word_u(reg[rsrc[1]]);
reg[rdest].trunc(wordSz);
}
break;
case 6:
reg[rdest] = reg[rsrc[0]] | reg[rsrc[1]];
break;
case 7:
reg[rdest] = reg[rsrc[0]] & reg[rsrc[1]];
break;
default:
cout << "ERROR: UNSUPPORTED R INST\n";
exit(1);
}
}
break;
case L_INST:
//std::cout << "L_INST\n";
memAddr = ((reg[rsrc[0]] + immsrc) & 0xFFFFFFFC);
shift_by = ((reg[rsrc[0]] + immsrc) & 0x00000003) * 8;
data_read = c.core->mem.read(memAddr, c.supervisorMode);
// //std::cout <<std::hex<< "EXECUTE: " << reg[rsrc[0]] << " + " << immsrc << " = " << memAddr << " -> data_read: " << data_read << "\n";
#ifdef EMU_INSTRUMENTATION
Harp::OSDomain::osDomain->
do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
#endif
switch (func3)
{
case 0:
// LB
reg[rdest] = signExt((data_read >> shift_by) & 0xFF, 8, 0xFF);
break;
case 1:
// LH
// //std::cout << "shifting by: " << shift_by << " final data: " << ((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF) << "\n";
reg[rdest] = signExt((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF);
break;
case 2:
reg[rdest] = int(data_read & 0xFFFFFFFF);
break;
case 4:
// LBU
reg[rdest] = unsigned((data_read >> shift_by) & 0xFF);
break;
case 5:
reg[rdest] = unsigned((data_read >> shift_by) & 0xFFFF);
break;
default:
cout << "ERROR: UNSUPPORTED L INST\n";
exit(1);
c.memAccesses.push_back(Warp::MemAccess(false, memAddr));
}
break;
case I_INST:
//std::cout << "I_INST\n";
switch (func3)
{
case 0:
// ADDI
reg[rdest] = reg[rsrc[0]] + immsrc;
reg[rdest].trunc(wordSz);
break;
case 2:
// SLTI
if ( int(reg[rsrc[0]]) < int(immsrc))
{
reg[rdest] = 1;
}
else
{
reg[rdest] = 0;
}
break;
case 3:
// SLTIU
op1 = (unsigned) reg[rsrc[0]];
if ( unsigned(reg[rsrc[0]]) < unsigned(immsrc))
{
reg[rdest] = 1;
}
else
{
reg[rdest] = 0;
}
break;
case 4:
// XORI
reg[rdest] = reg[rsrc[0]] ^ immsrc;
break;
case 6:
// ORI;
reg[rdest] = reg[rsrc[0]] | immsrc;
break;
case 7:
// ANDI
reg[rdest] = reg[rsrc[0]] & immsrc;
break;
case 1:
// SLLI
reg[rdest] = reg[rsrc[0]] << immsrc;
reg[rdest].trunc(wordSz);
break;
case 5:
if ((func7 == 0))
{
// SRLI
// //std::cout << "WTF\n";
bool isNeg = ((0x80000000 & reg[rsrc[0]])) > 0;
Word result = Word_u(reg[rsrc[0]]) >> Word_u(immsrc);
// if (isNeg)
// {
// Word mask = 0x80000000;
// for (int i = 32; i < Word_u(immsrc); i++)
// {
// result |= mask;
// mask = mask >> 1;
// }
// }
reg[rdest] = result;
reg[rdest].trunc(wordSz);
}
else
{
// SRAI
// //std::cout << "WOHOOOOO\n";
op1 = reg[rsrc[0]];
op2 = immsrc;
reg[rdest] = op1 >> op2;
reg[rdest].trunc(wordSz);
}
break;
default:
cout << "ERROR: UNSUPPORTED L INST\n";
exit(1);
}
break;
case S_INST:
//std::cout << "S_INST\n";
++c.stores;
memAddr = reg[rsrc[0]] + immsrc;
std::cout << "STORE MEM ADDRESS: " << std::hex << reg[rsrc[0]] << " + " << immsrc << "\n";
// //std::cout << "FUNC3: " << func3 << "\n";
if ((memAddr == 0x00010000) && (t == 0))
{
unsigned num = reg[rsrc[1]];
fprintf(stderr, "%c", (char) reg[rsrc[1]]);
break;
}
switch (func3)
{
case 0:
// //std::cout << "SB\n";
c.core->mem.write(memAddr, reg[rsrc[1]] & 0x000000FF, c.supervisorMode, 1);
break;
case 1:
// //std::cout << "SH\n";
c.core->mem.write(memAddr, reg[rsrc[1]], c.supervisorMode, 2);
break;
case 2:
// //std::cout << std::hex << "SW: about to write: " << reg[rsrc[1]] << " to " << memAddr << "\n";
c.core->mem.write(memAddr, reg[rsrc[1]], c.supervisorMode, 4);
break;
default:
cout << "ERROR: UNSUPPORTED S INST\n";
exit(1);
}
c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
#ifdef EMU_INSTRUMENTATION
Harp::OSDomain::osDomain->
do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
#endif
break;
case B_INST:
//std::cout << "B_INST\n";
switch (func3)
{
case 0:
// BEQ
if (int(reg[rsrc[0]]) == int(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
case 1:
// BNE
if (int(reg[rsrc[0]]) != int(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
case 4:
// BLT
if (int(reg[rsrc[0]]) < int(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
case 5:
// BGE
if (int(reg[rsrc[0]]) >= int(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
case 6:
// BLTU
if (Word_u(reg[rsrc[0]]) < Word_u(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
case 7:
// BGEU
if (Word_u(reg[rsrc[0]]) >= Word_u(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
}
break;
case LUI_INST:
//std::cout << "LUI_INST\n";
reg[rdest] = (immsrc << 12) & 0xfffff000;
break;
case AUIPC_INST:
//std::cout << "AUIPC_INST\n";
reg[rdest] = ((immsrc << 12) & 0xfffff000) + (c.pc - 4);
break;
case JAL_INST:
//std::cout << "JAL_INST\n";
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
if (!pcSet) {/*std::cout << "JAL... SETTING PC: " << nextPc << "\n"; */}
if (rdest != 0)
{
reg[rdest] = c.pc;
}
pcSet = true;
break;
case JALR_INST:
std::cout << "JALR_INST\n";
if (!pcSet) nextPc = reg[rsrc[0]] + immsrc;
if (!pcSet) {/*std::cout << "JALR... SETTING PC: " << nextPc << "\n";*/ }
if (rdest != 0)
{
reg[rdest] = c.pc;
}
pcSet = true;
break;
case SYS_INST:
//std::cout << "SYS_INST\n";
temp = reg[rsrc[0]];
if (immsrc == 0x20) // ThreadID
{
reg[rdest] = t;
D(2, "CSR Reading tid " << hex << immsrc << dec << " and returning " << reg[rdest]);
} else if (immsrc == 0x21) // WarpID
{
reg[rdest] = c.id;
D(2, "CSR Reading wid " << hex << immsrc << dec << " and returning " << reg[rdest]);
}
// switch (func3)
// {
// case 1:
// // printf("Case 1\n");
// if (rdest != 0)
// {
// reg[rdest] = c.csr[immsrc & 0x00000FFF];
// }
// c.csr[immsrc & 0x00000FFF] = temp;
// break;
// case 2:
// // printf("Case 2\n");
// if (rdest != 0)
// {
// // printf("Reading from CSR: %d = %d\n", (immsrc & 0x00000FFF), c.csr[immsrc & 0x00000FFF]);
// reg[rdest] = c.csr[immsrc & 0x00000FFF];
// }
// // printf("Writing to CSR --> %d = %d\n", immsrc, (temp | c.csr[immsrc & 0x00000FFF]));
// c.csr[immsrc & 0x00000FFF] = temp | c.csr[immsrc & 0x00000FFF];
// break;
// case 3:
// // printf("Case 3\n");
// if (rdest != 0)
// {
// reg[rdest] = c.csr[immsrc & 0x00000FFF];
// }
// c.csr[immsrc & 0x00000FFF] = temp & (~c.csr[immsrc & 0x00000FFF]);
// break;
// case 5:
// // printf("Case 5\n");
// if (rdest != 0)
// {
// reg[rdest] = c.csr[immsrc & 0x00000FFF];
// }
// c.csr[immsrc & 0x00000FFF] = rsrc[0];
// break;
// case 6:
// // printf("Case 6\n");
// if (rdest != 0)
// {
// reg[rdest] = c.csr[immsrc & 0x00000FFF];
// }
// c.csr[immsrc & 0x00000FFF] = rsrc[0] | c.csr[immsrc & 0x00000FFF];
// break;
// case 7:
// // printf("Case 7\n");
// if (rdest != 0)
// {
// reg[rdest] = c.csr[immsrc & 0x00000FFF];
// }
// c.csr[immsrc & 0x00000FFF] = rsrc[0] & (~c.csr[immsrc & 0x00000FFF]);
// break;
// case 0:
// if (immsrc < 2)
// {
// //std::cout << "INTERRUPT ECALL/EBREAK\n";
// nextActiveThreads = 0;
// c.spawned = false;
// // c.interrupt(0);
// }
// break;
// default:
// break;
// }
break;
case TRAP:
//std::cout << "INTERRUPT TRAP\n";
nextActiveThreads = 0;
c.interrupt(0);
break;
case FENCE:
//std::cout << "FENCE_INST\n";
break;
case PJ_INST:
// pred jump reg
//std::cout << "pred jump... src: " << rsrc[0] << std::hex << " val: " << reg[rsrc[0]] << " dest: " << reg[rsrc[1]] << "\n";
if (reg[rsrc[0]])
{
if (!pcSet) nextPc = reg[rsrc[1]];
pcSet = true;
}
break;
case GPGPU:
//std::cout << "GPGPU\n";
switch(func3)
{
case 1:
// WSPAWN
std::cout << "WSPAWN\n";
if (sjOnce)
{
sjOnce = false;
// //std::cout << "SIZE: " << c.core->w.size() << "\n";
num_to_wspawn = reg[rsrc[0]];
D(0, "Spawning " << num_to_wspawn << " new warps at PC: " << hex << reg[rsrc[1]]);
for (unsigned i = 1; i < num_to_wspawn; ++i)
{
// std::cout << "SPAWNING WARP\n";
Warp &newWarp(c.core->w[i]);
// //std::cout << "STARTING\n";
// if (newWarp.spawned == false)
{
// //std::cout << "ABOUT TO START\n";
newWarp.pc = reg[rsrc[1]];
// newWarp.reg[0] = reg;
// newWarp.csr = c.csr;
for (int kk = 0; kk < newWarp.tmask.size(); kk++)
{
if (kk == 0)
{
newWarp.tmask[kk] = true;
}
else
{
newWarp.tmask[kk] = false;
}
}
newWarp.activeThreads = 1;
newWarp.supervisorMode = false;
newWarp.spawned = true;
}
}
break;
}
break;
case 2:
{
// SPLIT
//std::cout << "SPLIT\n";
if (sjOnce)
{
sjOnce = false;
if (checkUnanimous(pred, c.reg, c.tmask)) {
std::cout << "Unanimous pred: " << pred << " val: " << reg[pred] << "\n";
DomStackEntry e(c.tmask);
e.uni = true;
c.domStack.push(e);
break;
}
cout << "Split: Original TM: ";
for (auto y : c.tmask) cout << y << " ";
cout << "\n";
DomStackEntry e(pred, c.reg, c.tmask, c.pc);
c.domStack.push(c.tmask);
c.domStack.push(e);
for (unsigned i = 0; i < e.tmask.size(); ++i)
{
c.tmask[i] = !e.tmask[i] && c.tmask[i];
}
cout << "Split: New TM\n";
for (auto y : c.tmask) cout << y << " ";
cout << "\n";
cout << "Split: Pushed TM PC: " << hex << e.pc << dec << "\n";
for (auto y : e.tmask) cout << y << " ";
cout << "\n";
}
break;
}
case 3:
// JOIN
//std::cout << "JOIN\n";
D(3, "JOIN INSTRUCTION");
if (sjOnce)
{
sjOnce = false;
if (!c.domStack.empty() && c.domStack.top().uni) {
D(2, "Uni branch at join");
printf("NEW DOMESTACK: \n");
c.tmask = c.domStack.top().tmask;
c.domStack.pop();
break;
}
if (!c.domStack.top().fallThrough) {
if (!pcSet) {
nextPc = c.domStack.top().pc;
cout << "join: NOT FALLTHROUGH PC: " << hex << nextPc << dec << '\n';
}
pcSet = true;
}
cout << "Join: Old TM: ";
for (auto y : c.tmask) cout << y << " ";
cout << "\n";
c.tmask = c.domStack.top().tmask;
cout << "Join: New TM: " << '\n';
for (auto y : c.tmask) cout << y << " ";
cout << "\n";
c.domStack.pop();
}
break;
case 4:
// is_barrier
break;
case 0:
// TMC
//std::cout << "JALRS\n";
nextActiveThreads = reg[rsrc[0]];
{
for (int ff = 0; ff < c.tmask.size(); ff++)
{
if (ff < nextActiveThreads)
{
c.tmask[ff] = true;
}
else
{
c.tmask[ff] = false;
}
}
}
if (nextActiveThreads == 0)
{
c.spawned = false;
}
// reg[rdest] = c.pc;
// if (!pcSet) nextPc = reg[rsrc[0]];
// pcSet = true;
// //std::cout << "ACTIVE_THREDS: " << rsrc[1] << " val: " << reg[rsrc[1]] << "\n";
// //std::cout << "nextPC: " << rsrc[0] << " val: " << std::hex << reg[rsrc[0]] << "\n";
break;
default:
cout << "ERROR: UNSUPPORTED GPGPU INSTRUCTION " << *this << "\n";
}
break;
default:
cout << "pc: " << hex << (c.pc) << "\n";
cout << "aERROR: Unsupported instruction: " << *this << "\n" << flush;
exit(1);
}
}
D(3, "End instruction execute.");
c.activeThreads = nextActiveThreads;
// if (nextActiveThreads != 0)
// {
// for (int i = 7; i >= c.activeThreads; i--)
// {
// c.tmask[i] = c.tmask[i] && false;
// }
// }
// //std::cout << "new thread mask: ";
// for (int i = 0; i < c.tmask.size(); ++i) //std::cout << " " << c.tmask[i];
// //std::cout << "\n";
// This way, if pc was set by a side effect (such as interrupt), it will
// retain its new value.
if (pcSet)
{
c.pc = nextPc;
cout << "Next PC: " << hex << nextPc << dec << "\n";
}
if (nextActiveThreads > c.reg.size()) {
cerr << "Error: attempt to spawn " << nextActiveThreads << " threads. "
<< c.reg.size() << " available.\n";
abort();
}
}

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/*******************************************************************************
HARPtools by Chad D. Kersey, Summer 2011
*******************************************************************************/
#include <fstream>
#include <iostream>
#include <iomanip>
#include <string>
#include <vector>
#include <stdlib.h>
#include <pthread.h>
#include "include/debug.h"
#include "include/types.h"
#include "include/util.h"
#include "include/mem.h"
#include "include/core.h"
using namespace std;
using namespace Harp;
RamMemDevice::RamMemDevice(const char *filename, Size wordSize) :
wordSize(wordSize), contents()
{
ifstream input(filename);
if (!input) {
cout << "Error reading file \"" << filename << "\" into RamMemDevice.\n";
exit(1);
}
do { contents.push_back(input.get()); } while (input);
while (contents.size() % wordSize) contents.push_back(0x00);
}
RamMemDevice::RamMemDevice(Size size, Size wordSize) :
contents(size), wordSize(wordSize) {}
void RomMemDevice::write(Addr, Word) {
cout << "Attempt to write to ROM.\n";
exit(1);
}
Word RamMemDevice::read(Addr addr) {
D(2, "RAM read, addr=0x" << hex << addr);
Word w = readWord(contents, addr, wordSize - addr%wordSize);
return w;
}
void RamMemDevice::write(Addr addr, Word w) {
D(2, "RAM write, addr=0x" << hex << addr);
writeWord(contents, addr, wordSize - addr%wordSize, w);
}
MemDevice &MemoryUnit::ADecoder::doLookup(Addr a, Size &bit) {
if (range == 0 || (a&((1ll<<bit)-1)) >= range) {
ADecoder *p(((a>>bit)&1)?oneChild:zeroChild);
if (p) { bit--; return p->doLookup(a, bit); }
else {cout << "lookup of 0x" << hex << a << " failed.\n";
throw BadAddress();}
} else {
return *md;
}
}
void MemoryUnit::ADecoder::map(Addr a, MemDevice &m, Size r, Size bit)
{
if ((1llu << bit) <= r) {
md = &m;
range = m.size();
} else {
ADecoder *&child(((a>>bit)&1)?oneChild:zeroChild);
if (!child) child = new ADecoder();
child->map(a, m, r, bit-1);
}
}
Byte *MemoryUnit::ADecoder::getPtr(Addr a, Size sz, Size wordSize) {
Size bit = wordSize - 1;
MemDevice &m(doLookup(a, bit));
a &= (2<<bit)-1;
if (a + sz <= m.size()) return m.base() + a;
return NULL;
}
Word MemoryUnit::ADecoder::read(Addr a, bool sup, Size wordSize) {
Size bit = wordSize - 1;
MemDevice &m(doLookup(a, bit));
a &= (2<<bit)-1;
// std::cout << std::hex << "ADecoder::read(Addr " << a << ", sup " << sup << ", wordSize " << wordSize << " -> ";
// std::cout << "Data: " << m.read(a) << "\n";
return m.read(a);
}
void MemoryUnit::ADecoder::write(Addr a, Word w, bool sup, Size wordSize) {
Size bit = wordSize - 1;
MemDevice &m(doLookup(a, bit));
RAM & r = (RAM &) m;
// a &= (2<<bit)-1;
// std::cout << std::hex << "ADecoder::write(Addr " << a << ", w " << w << ", sup " << sup << ", wordSize " << wordSize << "\n";
Word before = m.read(a);
Word new_word = w;
// if (a == 0x00010000)
// {
// fprintf(stderr, "%c", w);
// }
if (wordSize == 8)
{
r.writeByte(a, &w);
}
else if (wordSize == 16)
{
r.writeHalf(a, &w);
}
else
{
r.writeWord(a, &w);
}
// m.write(a, new_word);
}
Byte *MemoryUnit::getPtr(Addr a, Size s) {
return ad.getPtr(a, s, addrBytes*8);
}
void MemoryUnit::attach(MemDevice &m, Addr base) {
ad.map(base, m, m.size(), addrBytes*8 - 1);
}
MemoryUnit::TLBEntry MemoryUnit::tlbLookup(Addr vAddr, Word flagMask) {
map<Addr, MemoryUnit::TLBEntry>::iterator i;
if ((i = tlb.find(vAddr/pageSize)) != tlb.end()) {
TLBEntry &t = i->second;
if (t.flags & flagMask) return t;
else {
D(2, "Page fault on addr 0x" << hex << vAddr << "(bad flags)");
throw PageFault(vAddr, false);
}
} else {
D(2, "Page fault on addr 0x" << hex << vAddr << "(not in TLB)");
throw PageFault(vAddr, true);
}
}
#ifdef EMU_INSTRUMENTATION
Addr MemoryUnit::virtToPhys(Addr vAddr) {
TLBEntry t = tlbLookup(vAddr, 077);
return t.pfn*pageSize + vAddr%pageSize;
}
#endif
Word MemoryUnit::read(Addr vAddr, bool sup) {
Addr pAddr;
if (disableVm) {
pAddr = vAddr;
} else {
Word flagMask = sup?8:1;
TLBEntry t = tlbLookup(vAddr, flagMask);
pAddr = t.pfn*pageSize + vAddr%pageSize;
}
// std::cout << "MU::write: About to read: " << std::hex << pAddr << " = " << (ad.read(pAddr, sup, 8*addrBytes)) << " with " << std::dec << (8*addrBytes) << "\n";
return ad.read(pAddr, sup, 8*addrBytes);
}
Word MemoryUnit::fetch(Addr vAddr, bool sup) {
Addr pAddr;
if (disableVm) {
pAddr = vAddr;
} else {
Word flagMask = sup?32:4;
TLBEntry t = tlbLookup(vAddr, flagMask);
pAddr = t.pfn*pageSize + vAddr%pageSize;
}
Word instruction = ad.read(pAddr, sup, 8*addrBytes);
return instruction;
}
void MemoryUnit::write(Addr vAddr, Word w, bool sup, Size bytes) {
Addr pAddr;
if (disableVm) {
pAddr = vAddr;
} else {
Word flagMask = sup?16:2;
TLBEntry t = tlbLookup(vAddr, flagMask);
pAddr = t.pfn*pageSize + vAddr%pageSize;
}
// std::cout << "MU::write: About to write: " << std::hex << pAddr << " = " << w << " with " << std::dec << 8*bytes << "\n";
ad.write(pAddr, w, sup, 8*bytes);
// std::cout << std::hex << "reading same address: " << (this->read(vAddr, sup)) << "\n";
}
void MemoryUnit::tlbAdd(Addr virt, Addr phys, Word flags) {
D(1, "tlbAdd(0x" << hex << virt << ", 0x" << phys << ", 0x" << flags << ')');
tlb[virt/pageSize] = TLBEntry(phys/pageSize, flags);
}
void MemoryUnit::tlbRm(Addr va) {
if (tlb.find(va/pageSize) != tlb.end()) tlb.erase(tlb.find(va/pageSize));
}
void *Harp::consoleInputThread(void* arg_vp) {
ConsoleMemDevice *arg = (ConsoleMemDevice *)arg_vp;
char c;
while (cin) {
c = cin.get();
pthread_mutex_lock(&arg->cBufLock);
arg->cBuf.push(c);
pthread_mutex_unlock(&arg->cBufLock);
}
cout << "Console input ended. Exiting.\n";
exit(4);
}
ConsoleMemDevice::ConsoleMemDevice(Size wS, std::ostream &o, Core &core,
bool batch) :
wordSize(wS), output(o), core(core), cBuf()
{
// Create a console input thread if we are running in interactive mode.
if (!batch) {
pthread_t *thread = new pthread_t;
pthread_create(thread, NULL, consoleInputThread, (void*)this);
}
pthread_mutex_init(&cBufLock, NULL);
}
void ConsoleMemDevice::poll() {
pthread_mutex_lock(&cBufLock);
if (!cBuf.empty()) core.interrupt(8);
pthread_mutex_unlock(&cBufLock);
}
Word DiskControllerMemDevice::read(Addr a) {
switch (a/8) {
case 0: return curDisk;
case 1: return curBlock;
case 2: return disks[curDisk].blocks * blockSize;
case 3: return physAddr;
case 4: return command;
case 5: return status;
default:
cout << "Attempt to read invalid disk controller register.\n";
exit(1);
}
}
void DiskControllerMemDevice::write(Addr a, Word w) {
switch (a/8) {
case 0: if (w <= disks.size()) {
curDisk = w;
status = OK;
} else {
status = INVALID_DISK;
}
break;
case 1: if (w < disks[curDisk].blocks) {
curBlock = w;
} else {
status = INVALID_BLOCK;
}
break;
case 2: nBlocks = w >= disks[curDisk].blocks?disks[curDisk].blocks - 1 : w;
status = OK;
break;
case 3: physAddr = w;
status = OK;
break;
case 4: if (w == 0) {
} else {
}
cout << "TODO: Implement disk read and write!\n";
break;
}
}

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