github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-22 21:09:15 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

minor update

Browse source
This commit is contained in:
Blaise Tine 2020-12-09 05:49:02 -08:00
parent e0905f8352
commit fe07ca9aee
3 changed files with 62 additions and 51 deletions
Download patch file Download diff file Expand all files Collapse all files

60
hw/rtl/VX_csr_data.v
View file

@ -140,37 +140,37 @@ module VX_csr_data #(
`CSR_MPM_GPU_ST : read_data_r = perf_pipeline_if.gpu_stalls[31:0];
`CSR_MPM_GPU_ST_H : read_data_r = perf_pipeline_if.gpu_stalls[63:32];
// PERF: icache
`CSR_MPM_ICACHE_MISS_R : read_data_r = perf_memsys_if.icache_if.read_misses[31:0];
`CSR_MPM_ICACHE_MISS_R_H : read_data_r = perf_memsys_if.icache_if.read_misses[63:32];
`CSR_MPM_ICACHE_DREQ_ST : read_data_r = perf_memsys_if.icache_if.dreq_stalls[31:0];
`CSR_MPM_ICACHE_DREQ_ST_H : read_data_r = perf_memsys_if.icache_if.dreq_stalls[63:32];
`CSR_MPM_ICACHE_CRSP_ST : read_data_r = perf_memsys_if.icache_if.crsp_stalls[31:0];
`CSR_MPM_ICACHE_CRSP_ST_H : read_data_r = perf_memsys_if.icache_if.crsp_stalls[63:32];
`CSR_MPM_ICACHE_MSHR_ST : read_data_r = perf_memsys_if.icache_if.mshr_stalls[31:0];
`CSR_MPM_ICACHE_MSHR_ST_H : read_data_r = perf_memsys_if.icache_if.mshr_stalls[63:32];
`CSR_MPM_ICACHE_PIPE_ST : read_data_r = perf_memsys_if.icache_if.pipe_stalls[31:0];
`CSR_MPM_ICACHE_PIPE_ST_H : read_data_r = perf_memsys_if.icache_if.pipe_stalls[63:32];
`CSR_MPM_ICACHE_READS : read_data_r = perf_memsys_if.icache_if.reads[31:0];
`CSR_MPM_ICACHE_READS_H : read_data_r = perf_memsys_if.icache_if.reads[63:32];
`CSR_MPM_ICACHE_MISS_R : read_data_r = perf_memsys_if.icache_read_misses[31:0];
`CSR_MPM_ICACHE_MISS_R_H : read_data_r = perf_memsys_if.icache_read_misses[63:32];
`CSR_MPM_ICACHE_DREQ_ST : read_data_r = perf_memsys_if.icache_dreq_stalls[31:0];
`CSR_MPM_ICACHE_DREQ_ST_H : read_data_r = perf_memsys_if.icache_dreq_stalls[63:32];
`CSR_MPM_ICACHE_CRSP_ST : read_data_r = perf_memsys_if.icache_crsp_stalls[31:0];
`CSR_MPM_ICACHE_CRSP_ST_H : read_data_r = perf_memsys_if.icache_crsp_stalls[63:32];
`CSR_MPM_ICACHE_MSHR_ST : read_data_r = perf_memsys_if.icache_mshr_stalls[31:0];
`CSR_MPM_ICACHE_MSHR_ST_H : read_data_r = perf_memsys_if.icache_mshr_stalls[63:32];
`CSR_MPM_ICACHE_PIPE_ST : read_data_r = perf_memsys_if.icache_pipe_stalls[31:0];
`CSR_MPM_ICACHE_PIPE_ST_H : read_data_r = perf_memsys_if.icache_pipe_stalls[63:32];
`CSR_MPM_ICACHE_READS : read_data_r = perf_memsys_if.icache_reads[31:0];
`CSR_MPM_ICACHE_READS_H : read_data_r = perf_memsys_if.icache_reads[63:32];
// PERF: dcache
`CSR_MPM_DCACHE_MISS_R : read_data_r = perf_memsys_if.dcache_if.read_misses[31:0];
`CSR_MPM_DCACHE_MISS_R_H : read_data_r = perf_memsys_if.dcache_if.read_misses[63:32];
`CSR_MPM_DCACHE_MISS_W : read_data_r = perf_memsys_if.dcache_if.write_misses[31:0];
`CSR_MPM_DCACHE_MISS_W_H : read_data_r = perf_memsys_if.dcache_if.write_misses[63:32];
`CSR_MPM_DCACHE_DREQ_ST : read_data_r = perf_memsys_if.dcache_if.dreq_stalls[31:0];
`CSR_MPM_DCACHE_DREQ_ST_H : read_data_r = perf_memsys_if.dcache_if.dreq_stalls[63:32];
`CSR_MPM_DCACHE_CRSP_ST : read_data_r = perf_memsys_if.dcache_if.crsp_stalls[31:0];
`CSR_MPM_DCACHE_CRSP_ST_H : read_data_r = perf_memsys_if.dcache_if.crsp_stalls[63:32];
`CSR_MPM_DCACHE_MSHR_ST : read_data_r = perf_memsys_if.dcache_if.mshr_stalls[31:0];
`CSR_MPM_DCACHE_MSHR_ST_H : read_data_r = perf_memsys_if.dcache_if.mshr_stalls[63:32];
`CSR_MPM_DCACHE_PIPE_ST : read_data_r = perf_memsys_if.dcache_if.pipe_stalls[31:0];
`CSR_MPM_DCACHE_PIPE_ST_H : read_data_r = perf_memsys_if.dcache_if.pipe_stalls[63:32];
`CSR_MPM_DCACHE_READS : read_data_r = perf_memsys_if.dcache_if.reads[31:0];
`CSR_MPM_DCACHE_READS_H : read_data_r = perf_memsys_if.dcache_if.reads[63:32];
`CSR_MPM_DCACHE_WRITES : read_data_r = perf_memsys_if.dcache_if.writes[31:0];
`CSR_MPM_DCACHE_WRITES_H : read_data_r = perf_memsys_if.dcache_if.writes[63:32];
`CSR_MPM_DCACHE_EVICTS : read_data_r = perf_memsys_if.dcache_if.evictions[31:0];
`CSR_MPM_DCACHE_EVICTS_H : read_data_r = perf_memsys_if.dcache_if.evictions[63:32];
`CSR_MPM_DCACHE_MISS_R : read_data_r = perf_memsys_if.dcache_read_misses[31:0];
`CSR_MPM_DCACHE_MISS_R_H : read_data_r = perf_memsys_if.dcache_read_misses[63:32];
`CSR_MPM_DCACHE_MISS_W : read_data_r = perf_memsys_if.dcache_write_misses[31:0];
`CSR_MPM_DCACHE_MISS_W_H : read_data_r = perf_memsys_if.dcache_write_misses[63:32];
`CSR_MPM_DCACHE_DREQ_ST : read_data_r = perf_memsys_if.dcache_dreq_stalls[31:0];
`CSR_MPM_DCACHE_DREQ_ST_H : read_data_r = perf_memsys_if.dcache_dreq_stalls[63:32];
`CSR_MPM_DCACHE_CRSP_ST : read_data_r = perf_memsys_if.dcache_crsp_stalls[31:0];
`CSR_MPM_DCACHE_CRSP_ST_H : read_data_r = perf_memsys_if.dcache_crsp_stalls[63:32];
`CSR_MPM_DCACHE_MSHR_ST : read_data_r = perf_memsys_if.dcache_mshr_stalls[31:0];
`CSR_MPM_DCACHE_MSHR_ST_H : read_data_r = perf_memsys_if.dcache_mshr_stalls[63:32];
`CSR_MPM_DCACHE_PIPE_ST : read_data_r = perf_memsys_if.dcache_pipe_stalls[31:0];
`CSR_MPM_DCACHE_PIPE_ST_H : read_data_r = perf_memsys_if.dcache_pipe_stalls[63:32];
`CSR_MPM_DCACHE_READS : read_data_r = perf_memsys_if.dcache_reads[31:0];
`CSR_MPM_DCACHE_READS_H : read_data_r = perf_memsys_if.dcache_reads[63:32];
`CSR_MPM_DCACHE_WRITES : read_data_r = perf_memsys_if.dcache_writes[31:0];
`CSR_MPM_DCACHE_WRITES_H : read_data_r = perf_memsys_if.dcache_writes[63:32];
`CSR_MPM_DCACHE_EVICTS : read_data_r = perf_memsys_if.dcache_evictions[31:0];
`CSR_MPM_DCACHE_EVICTS_H : read_data_r = perf_memsys_if.dcache_evictions[63:32];
// PERF: memory
`CSR_MPM_DRAM_LAT : read_data_r = perf_memsys_if.dram_latency[31:0];
`CSR_MPM_DRAM_LAT_H : read_data_r = perf_memsys_if.dram_latency[63:32];

35
hw/rtl/VX_mem_unit.v
View file

@ -363,26 +363,23 @@ module VX_mem_unit # (
`ifdef PERF_ENABLE
assign perf_memsys_if.icache_if.read_misses = perf_icache_if.read_misses;
assign perf_memsys_if.icache_if.write_misses = perf_icache_if.write_misses;
assign perf_memsys_if.icache_if.mshr_stalls = perf_icache_if.mshr_stalls;
assign perf_memsys_if.icache_if.crsp_stalls = perf_icache_if.crsp_stalls;
assign perf_memsys_if.icache_if.dreq_stalls = perf_icache_if.dreq_stalls;
assign perf_memsys_if.icache_if.pipe_stalls = perf_icache_if.pipe_stalls;
assign perf_memsys_if.icache_if.reads = perf_icache_if.reads;
assign perf_memsys_if.icache_if.writes = perf_icache_if.writes;
assign perf_memsys_if.icache_if.evictions = perf_icache_if.evictions;
assign perf_memsys_if.dcache_if.read_misses = perf_dcache_if.read_misses;
assign perf_memsys_if.dcache_if.write_misses = perf_dcache_if.write_misses;
assign perf_memsys_if.dcache_if.mshr_stalls = perf_dcache_if.mshr_stalls;
assign perf_memsys_if.dcache_if.crsp_stalls = perf_dcache_if.crsp_stalls;
assign perf_memsys_if.dcache_if.dreq_stalls = perf_dcache_if.dreq_stalls;
assign perf_memsys_if.dcache_if.pipe_stalls = perf_dcache_if.pipe_stalls;
assign perf_memsys_if.dcache_if.reads = perf_dcache_if.reads;
assign perf_memsys_if.dcache_if.writes = perf_dcache_if.writes;
assign perf_memsys_if.dcache_if.evictions = perf_dcache_if.evictions;
assign perf_memsys_if.icache_reads = perf_icache_if.reads;
assign perf_memsys_if.icache_read_misses = perf_icache_if.read_misses;
assign perf_memsys_if.icache_mshr_stalls = perf_icache_if.mshr_stalls;
assign perf_memsys_if.icache_crsp_stalls = perf_icache_if.crsp_stalls;
assign perf_memsys_if.icache_dreq_stalls = perf_icache_if.dreq_stalls;
assign perf_memsys_if.icache_pipe_stalls = perf_icache_if.pipe_stalls;
assign perf_memsys_if.dcache_reads = perf_dcache_if.reads;
assign perf_memsys_if.dcache_writes = perf_dcache_if.writes;
assign perf_memsys_if.dcache_read_misses = perf_dcache_if.read_misses;
assign perf_memsys_if.dcache_write_misses = perf_dcache_if.write_misses;
assign perf_memsys_if.dcache_evictions = perf_dcache_if.evictions;
assign perf_memsys_if.dcache_mshr_stalls = perf_dcache_if.mshr_stalls;
assign perf_memsys_if.dcache_crsp_stalls = perf_dcache_if.crsp_stalls;
assign perf_memsys_if.dcache_dreq_stalls = perf_dcache_if.dreq_stalls;
assign perf_memsys_if.dcache_pipe_stalls = perf_dcache_if.pipe_stalls;
reg [63:0] perf_dram_lat_per_cycle;
always @(posedge clk) begin

18
hw/rtl/interfaces/VX_perf_memsys_if.v
View file

@ -5,8 +5,22 @@
interface VX_perf_memsys_if ();
VX_perf_cache_if dcache_if;
VX_perf_cache_if icache_if;
wire [63:0] icache_reads;
wire [63:0] icache_read_misses;
wire [63:0] icache_mshr_stalls;
wire [63:0] icache_crsp_stalls;
wire [63:0] icache_dreq_stalls;
wire [63:0] icache_pipe_stalls;
wire [63:0] dcache_reads;
wire [63:0] dcache_writes;
wire [63:0] dcache_read_misses;
wire [63:0] dcache_write_misses;
wire [63:0] dcache_evictions;
wire [63:0] dcache_mshr_stalls;
wire [63:0] dcache_crsp_stalls;
wire [63:0] dcache_dreq_stalls;
wire [63:0] dcache_pipe_stalls;
wire [63:0] dram_latency;
wire [63:0] dram_requests;