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https://github.com/vortexgpgpu/vortex.git
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minor update
This commit is contained in:
Blaise Tine
parent
fa2d84831e
commit
fff3fb18fb
4 changed files with 99 additions and 76 deletions
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@ -35,17 +35,17 @@ module VX_tex_addr #(
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// outputs
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output wire mem_req_valid,
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output wire [`NW_BITS-1:0] mem_req_wid,
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output wire [`NUM_THREADS-1:0] mem_req_tmask,
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output wire [31:0] mem_req_PC,
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output wire [`TEX_FILTER_BITS-1:0] mem_req_filter,
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output wire [`TEX_STRIDE_BITS-1:0] mem_req_stride,
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output wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr,
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output wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_u,
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output wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_v,
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output wire [REQ_INFO_WIDTH-1:0] mem_req_info,
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input wire mem_req_ready
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output wire rsp_valid,
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output wire [`NW_BITS-1:0] rsp_wid,
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output wire [`NUM_THREADS-1:0] rsp_tmask,
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output wire [31:0] rsp_PC,
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output wire [`TEX_FILTER_BITS-1:0] rsp_filter,
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output wire [`TEX_STRIDE_BITS-1:0] rsp_stride,
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output wire [`NUM_THREADS-1:0][3:0][31:0] rsp_addr,
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output wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] rsp_blend_u,
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output wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] rsp_blend_v,
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output wire [REQ_INFO_WIDTH-1:0] rsp_info,
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input wire rsp_ready
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);
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`UNUSED_PARAM (CORE_ID)
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@ -130,34 +130,34 @@ module VX_tex_addr #(
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assign addr[i][3] = base_addr + 32'(mip_offsets[i]) + (32'(x[1]) + (32'(y[1]) << log_widths[i])) << log_stride;
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end
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wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] u0, v0;
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wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] blend_u, blend_v;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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assign u0[i] = clamped_u[i][0];
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assign v0[i] = clamped_v[i][0];
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assign blend_u[i] = clamped_u[i][0][`BLEND_FRAC-1:0];
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assign blend_v[i] = clamped_v[i][0][`BLEND_FRAC-1:0];
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end
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wire stall_out = mem_req_valid && ~mem_req_ready;
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wire stall_out = rsp_valid && ~rsp_ready;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (`NUM_THREADS * 4 * 32) + (2*`NUM_THREADS * `FIXED_FRAC) + REQ_INFO_WIDTH),
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (`NUM_THREADS * 4 * 32) + (2*`NUM_THREADS * `BLEND_FRAC) + REQ_INFO_WIDTH),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({valid_in, req_wid, req_tmask, req_PC, filter, log_stride, addr, u0, v0, req_info}),
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.data_out ({mem_req_valid, mem_req_wid, mem_req_tmask, mem_req_PC, mem_req_filter, mem_req_stride, mem_req_addr, mem_req_u, mem_req_v, mem_req_info})
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.data_in ({valid_in, req_wid, req_tmask, req_PC, filter, log_stride, addr, blend_u, blend_v, req_info}),
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.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_filter, rsp_stride, rsp_addr, rsp_blend_u, rsp_blend_v, rsp_info})
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);
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assign ready_in = ~stall_out;
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`ifdef DBG_PRINT_TEX
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always @(posedge clk) begin
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if (mem_req_valid && mem_req_ready) begin
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if (rsp_valid && rsp_ready) begin
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$write("%t: core%0d-tex-addr: wid=%0d, PC=%0h, tmask=%b, filter=%0d, tride=%0d, addr=",
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$time, CORE_ID, mem_req_wid, mem_req_PC, mem_req_tmask, mem_req_filter, mem_req_stride);
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`PRINT_ARRAY2D(mem_req_addr, 4, `NUM_THREADS);
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$time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask, rsp_filter, rsp_stride);
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`PRINT_ARRAY2D(rsp_addr, 4, `NUM_THREADS);
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$write("\n");
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end
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end
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@ -273,9 +273,15 @@ module VX_tex_memory #(
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`PRINT_ARRAY1D(rsp_data_qual, `NUM_THREADS);
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$write("\n");
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end
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if (req_valid && req_ready) begin
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$write("%t: core%0d-tex-mem-req: wid=%0d, PC=%0h, tmask=%b, filter=%0d, stride=%0d, addr=",
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$time, CORE_ID, req_wid, req_PC, req_tmask, req_filter, req_stride);
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`PRINT_ARRAY2D(req_addr, 4, `NUM_THREADS);
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$write("\n");
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end
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if (rsp_valid && rsp_ready) begin
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$write("%t: core%0d-tex-mem-rsp: wid=%0d, PC=%0h, filter=%0d, data=",
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$time, CORE_ID, rsp_wid, rsp_PC, rsp_filter);
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$write("%t: core%0d-tex-mem-rsp: wid=%0d, PC=%0h, tmask=%b, filter=%0d, data=",
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$time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask, rsp_filter);
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`PRINT_ARRAY2D(rsp_data, 4, `NUM_THREADS);
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$write("\n");
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end
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@ -15,9 +15,9 @@ module VX_tex_sampler #(
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input wire req_wb,
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input wire [`TEX_FILTER_BITS-1:0] req_filter,
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input wire [`TEX_FORMAT_BITS-1:0] req_format,
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input wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] req_u,
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input wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] req_v,
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input wire [`NUM_THREADS-1:0][3:0][31:0] req_texels,
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input wire [`NUM_THREADS-1:0][3:0][31:0] req_data,
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input wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] req_blend_u,
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input wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] req_blend_v,
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output wire req_ready,
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// ouputs
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@ -33,7 +33,7 @@ module VX_tex_sampler #(
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`UNUSED_PARAM (CORE_ID)
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wire [`NUM_THREADS-1:0][31:0] req_data;
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wire [`NUM_THREADS-1:0][31:0] result;
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wire stall_out;
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@ -42,22 +42,19 @@ module VX_tex_sampler #(
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wire [3:0][31:0] fmt_texels;
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wire [31:0] texel_ul, texel_uh, texel_v;
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wire [`BLEND_FRAC-1:0] blend_u = req_u[i][`BLEND_FRAC-1:0];
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wire [`BLEND_FRAC-1:0] blend_v = req_v[i][`BLEND_FRAC-1:0];
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for (genvar j = 0; j < 4; j++) begin
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VX_tex_format #(
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.CORE_ID (CORE_ID)
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) tex_format (
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.format (req_format),
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.texel_in (req_texels[i][j]),
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.texel_in (req_data[i][j]),
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.texel_out (fmt_texels[j])
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);
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end
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VX_tex_lerp #(
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) tex_lerp_ul (
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.blend (blend_u),
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.blend (req_blend_u[i]),
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.in1 (fmt_texels[0]),
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.in2 (fmt_texels[1]),
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.out (texel_ul)
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@ -65,7 +62,7 @@ module VX_tex_sampler #(
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VX_tex_lerp #(
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) tex_lerp_uh (
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.blend (blend_u),
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.blend (req_blend_u[i]),
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.in1 (fmt_texels[2]),
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.in2 (fmt_texels[3]),
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.out (texel_uh)
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@ -73,13 +70,13 @@ module VX_tex_sampler #(
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VX_tex_lerp #(
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) tex_lerp_v (
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.blend (blend_v),
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.blend (req_blend_v[i]),
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.in1 (texel_ul),
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.in2 (texel_uh),
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.out (texel_v)
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);
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assign req_data[i] = req_filter ? texel_v : fmt_texels[0];
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assign result[i] = req_filter ? texel_v : fmt_texels[0];
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end
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assign stall_out = rsp_valid && ~rsp_ready;
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@ -91,11 +88,32 @@ module VX_tex_sampler #(
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_data}),
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.data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, result}),
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.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data})
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);
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// can accept new request?
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assign req_ready = ~stall_out;
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assign req_ready = ~stall_out;
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`ifdef DBG_PRINT_TEX
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always @(posedge clk) begin
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if (req_valid && req_ready) begin
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$write("%t: core%0d-sampler-req: wid=%0d, PC=%0h, tmask=%b, filter=%0d, format=%0d, data=",
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$time, CORE_ID, req_wid, req_PC, req_tmask, req_filter, req_format);
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`PRINT_ARRAY2D(req_data, 4, `NUM_THREADS);
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$write("u0=");
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`PRINT_ARRAY2D(req_u0, 4, `NUM_THREADS);
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$write("v0=");
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`PRINT_ARRAY2D(req_v0, 4, `NUM_THREADS);
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$write("\n");
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end
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if (rsp_valid && rsp_ready) begin
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$write("%t: core%0d-sampler-rsp: wid=%0d, PC=%0h, tmask=%b, data=",
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$time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask);
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`PRINT_ARRAY2D(rsp_data, 4, `NUM_THREADS);
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$write("\n");
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end
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end
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`endif
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endmodule
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@ -19,7 +19,7 @@ module VX_tex_unit #(
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);
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localparam REQ_INFO_WIDTH_A = `TEX_FORMAT_BITS + `NR_BITS + 1;
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localparam REQ_INFO_WIDTH_M = (2 * `NUM_THREADS * `FIXED_FRAC) + REQ_INFO_WIDTH_A;
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localparam REQ_INFO_WIDTH_M = (2 * `NUM_THREADS * `BLEND_FRAC) + REQ_INFO_WIDTH_A;
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR (reset)
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@ -93,8 +93,8 @@ module VX_tex_unit #(
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wire [31:0] mem_req_PC;
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wire [`TEX_FILTER_BITS-1:0] mem_req_filter;
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wire [`TEX_STRIDE_BITS-1:0] mem_req_stride;
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wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_u;
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wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_v;
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wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] mem_req_blend_u;
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wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] mem_req_blend_v;
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wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr;
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wire [REQ_INFO_WIDTH_A-1:0] mem_req_info;
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wire mem_req_ready;
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@ -111,41 +111,41 @@ module VX_tex_unit #(
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VX_tex_addr #(
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.REQ_INFO_WIDTH (REQ_INFO_WIDTH_A)
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) tex_addr (
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.clk (clk),
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.reset (reset),
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.clk (clk),
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.reset (reset),
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.valid_in (tex_req_if.valid),
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.ready_in (tex_req_if.ready),
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.valid_in (tex_req_if.valid),
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.ready_in (tex_req_if.ready),
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.req_wid (tex_req_if.wid),
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.req_tmask (tex_req_if.tmask),
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.req_PC (tex_req_if.PC),
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.req_info ({tex_format[tex_req_if.unit], tex_req_if.rd, tex_req_if.wb}),
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.req_wid (tex_req_if.wid),
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.req_tmask (tex_req_if.tmask),
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.req_PC (tex_req_if.PC),
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.req_info ({tex_format[tex_req_if.unit], tex_req_if.rd, tex_req_if.wb}),
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.format (tex_format[tex_req_if.unit]),
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.filter (tex_filter[tex_req_if.unit]),
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.wrap_u (tex_wrap_u[tex_req_if.unit]),
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.wrap_v (tex_wrap_v[tex_req_if.unit]),
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.format (tex_format[tex_req_if.unit]),
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.filter (tex_filter[tex_req_if.unit]),
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.wrap_u (tex_wrap_u[tex_req_if.unit]),
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.wrap_v (tex_wrap_v[tex_req_if.unit]),
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.base_addr (tex_baddr[tex_req_if.unit]),
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.mip_offsets (tex_mipoffs),
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.log_widths (tex_widths),
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.log_heights (tex_heights),
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.base_addr (tex_baddr[tex_req_if.unit]),
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.mip_offsets(tex_mipoffs),
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.log_widths (tex_widths),
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.log_heights(tex_heights),
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.coord_u (tex_req_if.u),
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.coord_v (tex_req_if.v),
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.coord_u (tex_req_if.u),
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.coord_v (tex_req_if.v),
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.mem_req_valid (mem_req_valid),
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.mem_req_wid (mem_req_wid),
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.mem_req_tmask (mem_req_tmask),
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.mem_req_PC (mem_req_PC),
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.mem_req_filter (mem_req_filter),
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.mem_req_stride (mem_req_stride),
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.mem_req_addr (mem_req_addr),
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.mem_req_u (mem_req_u),
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.mem_req_v (mem_req_v),
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.mem_req_info (mem_req_info),
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.mem_req_ready (mem_req_ready)
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.rsp_valid (mem_req_valid),
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.rsp_wid (mem_req_wid),
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.rsp_tmask (mem_req_tmask),
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.rsp_PC (mem_req_PC),
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.rsp_filter (mem_req_filter),
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.rsp_stride (mem_req_stride),
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.rsp_addr (mem_req_addr),
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.rsp_blend_u(mem_req_blend_u),
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.rsp_blend_v(mem_req_blend_v),
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.rsp_info (mem_req_info),
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.rsp_ready (mem_req_ready)
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);
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// retrieve texel values from memory
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@ -168,7 +168,7 @@ module VX_tex_unit #(
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.req_filter(mem_req_filter),
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.req_stride(mem_req_stride),
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.req_addr (mem_req_addr),
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.req_info ({mem_req_u, mem_req_v, mem_req_info}),
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.req_info ({mem_req_blend_u, mem_req_blend_v, mem_req_info}),
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.req_ready (mem_req_ready),
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// outputs
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@ -184,13 +184,12 @@ module VX_tex_unit #(
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// apply sampler
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wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] rsp_blend_u, rsp_blend_v;
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wire [`TEX_FORMAT_BITS-1:0] rsp_format;
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wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] rsp_u;
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wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] rsp_v;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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assign {rsp_u, rsp_v, rsp_format, rsp_rd, rsp_wb} = mem_rsp_info;
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assign {rsp_blend_u, rsp_blend_v, rsp_format, rsp_rd, rsp_wb} = mem_rsp_info;
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VX_tex_sampler #(
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.CORE_ID (CORE_ID)
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@ -203,11 +202,11 @@ module VX_tex_unit #(
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.req_wid (mem_rsp_wid),
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.req_tmask (mem_rsp_tmask),
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.req_PC (mem_rsp_PC),
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.req_texels (mem_rsp_data),
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.req_data (mem_rsp_data),
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.req_filter (mem_rsp_filter),
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.req_format (rsp_format),
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.req_u (rsp_u),
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.req_v (rsp_v),
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.req_blend_u(rsp_blend_u),
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.req_blend_v(rsp_blend_v),
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.req_rd (rsp_rd),
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.req_wb (rsp_wb),
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.req_ready (mem_rsp_ready),
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