13 commits

Author	SHA1	Message	Date
MichaelJSr	5eecd0e987	Added case for vector-test due to different exitcode ... The vector tests need the cluster exitcodes	2024-11-27 23:50:57 -08:00
Jaewon Lee	3caeeeea13	satp_ is not set, then we skip VAT	2024-06-30 00:35:26 -04:00
Jaewon Lee	d531fa6b26	64bit support	2024-06-29 17:43:20 -04:00
Jaewon Lee	02091f3d44	Merge Vortex 2.2	2024-06-22 23:55:01 -04:00
Jaewon Lee	01c7b5e384	Change the declaration of set_processor_satp function	2024-06-19 01:36:26 -04:00
Jaewon Lee	cfcece940e	Merge Austin's code (Preliminary)	2024-06-19 01:36:26 -04:00
Blaise Tine	f8ef570778	riscv tests refactoring	2024-05-28 10:46:31 -07:00
Blaise Tine	db0f0fd353	runtime API refactoring to support memory reservation and protection	2024-04-28 04:23:00 -07:00
Blaise Tine	840ced22a9	simx refactoring - emulation vs simulation discrete separation	2024-03-12 00:23:42 -07:00
Blaise Tine	d47cccc157	Vortex 2.0 changes: ... + Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes	2023-10-19 20:51:22 -07:00
Blaise Tine	5825b7c15a	dram simulator fix	2021-12-07 22:44:06 -05:00
Blaise Tine	b741807f8c	using ramulator dram simulator	2021-12-06 01:22:45 -05:00
Blaise Tine	2a7a4df342	simx directory name fix	2021-11-30 07:17:58 -05:00

Renamed from sim/simX/processor.h (Browse further)