37 commits

Author	SHA1	Message	Date
Blaise Tine	e2461108d2	redesign of predicate extension to handle complex code optimizations	2023-07-10 20:06:48 -04:00
Blaise Tine	22f4d6609c	imadd feature deprecation	2023-07-03 00:13:45 -04:00
Blaise Tine	bd5a52ff9c	adding support for double-precision FPU hardware	2023-06-14 06:13:57 -04:00
Blaise Tine	11c242c345	minor update	2023-06-06 16:45:10 -04:00
Blaise Tine	014490dcd8	enabling support for 64-bit floating-point hardware	2023-06-05 14:41:39 -04:00
Blaise Tine	d2961cc3f8	adding support for atomic extension to simx	2023-05-28 07:45:45 -04:00
Blaise Tine	f7e18477ec	bug fix: busy signal should wait for all intrs to complete	2022-10-09 23:41:35 -04:00
Blaise Tine	362e7ebbb4	per-cluster texture unit support	2022-06-02 08:41:35 -04:00
Blaise Tine	89b53b7bae	removed sw prefetch	2022-05-28 04:07:59 -04:00
Blaise Tine	c56a0bd0d2	refacoring pass on IMADD, CMOV, ROP, RASTER, Draw3D - simplified raster/rop serives, remove custom interpolation instruction	2022-03-20 02:41:14 -04:00
Blaise Tine	45150919e3	rasterizer simulator updates	2022-03-09 02:17:45 -05:00
Blaise Tine	d1e9b3283c	simx files refactoring	2022-03-07 06:39:15 -05:00
Blaise Tine	a767efe3c2	fixed vortex custom extension opcode to use official unused values	2022-03-06 22:55:52 -05:00
Blaise Tine	4d51d15ab9	simx rasterizer & render output implementation	2022-03-05 20:59:11 -05:00
Blaise Tine	302387a2cf	moved global csrs to device configuration registers (DCRs) to resolve namespace conflict & added vx_interp & draw3d kernel update	2022-03-02 12:22:18 -05:00
lc97667	e7a5853e37	interpolation rtl update	2022-02-23 18:59:39 -05:00
Blaise Tine	d139f6bd4b	simx debug trace level update	2022-02-17 15:49:12 -05:00
Blaise Tine	1bd25acb0b	cmov	2022-02-05 17:58:12 -05:00
Santosh Srivatsan	b7e5a83ba3	Merged branch xlen-parameterization into staging	2022-02-05 13:47:42 -05:00
Blaise Tine	140124b423	additional bug fixes	2022-02-05 07:42:50 -05:00
Blaise Tine	703d3faf27	minor bug fixes	2022-02-05 06:37:54 -05:00
Blaise Tine	5fbace9fa0	fixed several bugs and refactor memory access	2022-02-04 17:50:19 -05:00
Blaise Tine	cf2a0a5f39	code refactoring	2022-02-04 00:07:24 -05:00
Santosh Srivatsan	836c777680	XLEN parameterization for simx	2022-02-03 15:19:31 -05:00
Santosh Srivatsan	7e3a2fdb0f	Modifications to allow 64-bit riscv tests to run on travis CI	2022-01-27 15:55:19 -05:00
Santosh Srivatsan	7aa93a735d	Added FLEN parameterization for RV32/64 F and D instructions	2022-01-24 15:42:15 -05:00
Santosh Srivatsan	ad92c09f5b	Changed all instances of DWord to XWord and DWordI to XWordI. Added XLEN parameterization to the simx Makefile	2022-01-22 13:47:44 -05:00
Santosh Srivatsan	91c22a2592	Fixed some riscv-tests	2022-01-22 12:54:10 -05:00
Blaise Tine	29df0da8b5	minor warning fixes	2022-01-10 20:33:37 -05:00
Santosh Srivatsan	71acf4eadb	Changed instruction size from wsize() * 4 to wsize() * 8	2021-12-13 20:42:44 -05:00
Santosh Srivatsan	4abfca4cb2	Replaced all instanced of DoubleWord to DWord and DoubleWordI to DWordI	2021-12-13 19:55:02 -05:00
Santosh Srivatsan	e82d5fe48f	Removed all comments labelled \'simx64\'	2021-12-13 19:52:13 -05:00
Santosh Srivatsan	885bb58ca9	Merged RV64IMFD extensions to master branch	2021-12-11 17:06:29 -05:00
Santosh Srivatsan	5edb9098ce	Merge branch 'simx64'	2021-12-10 21:48:29 -05:00
Santosh Srivatsan	e7bc436b52	Renamed simX to simx	2021-12-10 16:57:29 -05:00
Blaise Tine	0e2de4f13a	prefetch test fixes	2021-12-09 04:54:10 -05:00
Blaise Tine	2a7a4df342	simx directory name fix	2021-11-30 07:17:58 -05:00

Renamed from sim/simX/decode.cpp (Browse further)