mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-06-28 17:43:24 -04:00
129 lines
No EOL
3 KiB
C++
129 lines
No EOL
3 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "mem_sim.h"
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#include <vector>
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#include <queue>
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#include <stdlib.h>
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#include <dram_sim.h>
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#include "constants.h"
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#include "types.h"
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#include "debug.h"
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using namespace vortex;
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class MemSim::Impl {
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private:
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MemSim* simobject_;
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Config config_;
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DramSim dram_sim_;
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PerfStats perf_stats_;
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struct DramCallbackArgs {
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MemSim* simobject;
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MemReq request;
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uint32_t i;
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};
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public:
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Impl(MemSim* simobject, const Config& config)
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: simobject_(simobject)
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, config_(config)
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, dram_sim_(MEM_CLOCK_RATIO)
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{}
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~Impl() {
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//--
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}
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const PerfStats& perf_stats() const {
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return perf_stats_;
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}
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void reset() {
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dram_sim_.reset();
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}
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void tick() {
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dram_sim_.tick();
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uint32_t counter = 0;
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for (uint32_t i = 0; i < NUM_MEM_PORTS; ++i) {
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if (simobject_->MemReqPorts.at(i).empty())
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continue;
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auto& mem_req = simobject_->MemReqPorts.at(i).front();
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// try to enqueue the request to the memory system
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auto req_args = new DramCallbackArgs{simobject_, mem_req, i};
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auto enqueue_success = dram_sim_.send_request(
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mem_req.write,
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mem_req.addr,
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0,
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[](void* arg) {
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auto rsp_args = reinterpret_cast<const DramCallbackArgs*>(arg);
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// only send a response for read requests
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if (!rsp_args->request.write) {
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MemRsp mem_rsp{rsp_args->request.tag, rsp_args->request.cid, rsp_args->request.uuid};
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rsp_args->simobject->MemRspPorts.at(rsp_args->i).push(mem_rsp, 1);
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DT(3, rsp_args->simobject->name() << " mem-rsp: bank=" << rsp_args->i << ", " << mem_rsp);
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}
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delete rsp_args;
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},
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req_args
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);
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// check if the request was enqueued successfully
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if (!enqueue_success) {
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delete req_args;
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continue;
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}
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DT(3, simobject_->name() << " mem-req: bank=" << i << ", " << mem_req);
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simobject_->MemReqPorts.at(i).pop();
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counter++;
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}
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perf_stats_.counter += counter;
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if (counter > 0) {
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++perf_stats_.ticks;
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}
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}
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};
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///////////////////////////////////////////////////////////////////////////////
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MemSim::MemSim(const SimContext& ctx, const char* name, const Config& config)
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: SimObject<MemSim>(ctx, name)
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, MemReqPorts(NUM_MEM_PORTS, this)
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, MemRspPorts(NUM_MEM_PORTS, this)
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, impl_(new Impl(this, config))
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{}
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MemSim::~MemSim() {
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delete impl_;
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}
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void MemSim::reset() {
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impl_->reset();
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}
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void MemSim::tick() {
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impl_->tick();
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}
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const MemSim::PerfStats &MemSim::perf_stats() const {
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return impl_->perf_stats();
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} |