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54 lines
1.6 KiB
Systemverilog
54 lines
1.6 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_multiplier #(
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parameter A_WIDTH = 1,
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parameter B_WIDTH = A_WIDTH,
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parameter R_WIDTH = A_WIDTH + B_WIDTH,
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parameter SIGNED = 0,
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parameter LATENCY = 0
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) (
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input wire clk,
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input wire enable,
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input wire [A_WIDTH-1:0] dataa,
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input wire [B_WIDTH-1:0] datab,
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output wire [R_WIDTH-1:0] result
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);
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wire [R_WIDTH-1:0] prod_w;
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if (SIGNED != 0) begin : g_prod_s
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assign prod_w = R_WIDTH'($signed(dataa) * $signed(datab));
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end else begin : g_prod_u
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assign prod_w = R_WIDTH'(dataa * datab);
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end
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if (LATENCY == 0) begin : g_passthru
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assign result = prod_w;
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end else begin : g_latency
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reg [LATENCY-1:0][R_WIDTH-1:0] prod_r;
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always @(posedge clk) begin
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if (enable) begin
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prod_r[0] <= prod_w;
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for (integer i = 1; i < LATENCY; ++i) begin
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prod_r[i] <= prod_r[i-1];
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end
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end
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end
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assign result = prod_r[LATENCY-1];
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end
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endmodule
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`TRACING_ON
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