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86 lines
2.6 KiB
Markdown
86 lines
2.6 KiB
Markdown
# FPGA Startup and Configuration Guide
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OPAE Environment Setup
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----------------------
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$ source /opt/inteldevstack/init_env_user.sh
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$ export OPAE_HOME=/opt/opae/1.1.2
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$ export PATH=$OPAE_HOME/bin:$PATH
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$ export C_INCLUDE_PATH=$OPAE_HOME/include:$C_INCLUDE_PATH
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$ export LIBRARY_PATH=$OPAE_HOME/lib:$LIBRARY_PATH
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$ export LD_LIBRARY_PATH=$OPAE_HOME/lib:$LD_LIBRARY_PATH
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$ export RISCV_TOOLCHAIN_PATH=/opt/riscv-gnu-toolchain
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$ export PATH=:/opt/verilator/bin:$PATH
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$ export VERILATOR_ROOT=/opt/verilator
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OPAE Build
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------------------
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The FPGA has to following configuration options:
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- 1 core fpga (fpga-1c)
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- 2 cores fpga (fpga-2c)
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- 4 cores fpga (fpga-4c)
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- 8 cores fpga (fpga-8c)
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- 16 cores fpga (fpga-16c)
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- 32 cores fpga (fpga-32c)
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- 64 cores fpga (fpga-64c)
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Command line:
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$ cd hw/syn/opae
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$ make fpga-<num-of-cores>c
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Example: `make fpga-4c`
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A new folder (ex: `build_fpga_4c`) will be created and the build will start and take ~30-480 min to complete.
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OPAE Build Configuration
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------------------------
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The hardware configuration file `/hw/rtl/VX_config.vh` defines all the hardware parameters that can be modified when build the processor.For example, have the following parameters that can be configured:
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- `NUM_WARPS`: Number of warps per cores
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- `NUM_THREADS`: Number of threads per warps
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- `PERF_ENABLE`: enable the use of all profile counters
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You configure the syntesis build from the command line:
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$ CONFIGS="-DPERF_ENABLE -DNUM_THREADS=8" make fpga-4c
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OPAE Build Progress
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-------------------
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You could check the last 10 lines in the build log for possible errors until build completion.
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$ tail -n 10 ./build_fpga_<num-of-cores>c/build.log
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Check if the build is still running by looking for quartus_sh, quartus_syn, or quartus_fit programs.
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$ ps -u <username>
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If the build fails and you need to restart it, clean up the build folder using the following command:
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$ make clean-fpga-<num-of-cores>c
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Example: `make clean-fpga-4c`
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The file `vortex_afu.gbs` should exist when the build is done:
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$ ls -lsa ./build_fpga_<num-of-cores>c/vortex_afu.gbs
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Signing the bitstream and Programming the FPGA
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----------------------------------------------
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$ cd ./build_fpga_<num-of-cores>c
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$ PACSign PR -t UPDATE -H openssl_manager -i vortex_afu.gbs -o vortex_afu_unsigned_ssl.gbs
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$ fpgasupdate vortex_afu_unsigned_ssl.gbs
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FPGA sample test running OpenCL sgemm kernel
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--------------------------------------------
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Run the following from the Vortex root directory
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$ ./ci/blackbox.sh --driver=fpga --app=sgemm --args="-n64"
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