vortex/hw
2020-06-30 18:20:59 -07:00
..
configs project directories reorganization 2020-04-14 06:35:20 -04:00
models/memory RTL code refactoring 2020-04-19 03:38:00 -04:00
modelsim fpga fixes 2020-06-27 14:03:20 -07:00
old_rtl refactoring fixes 2020-04-14 19:39:59 -04:00
opae OPAE CSR access 2020-06-30 18:14:06 -07:00
rtl Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2020-06-30 18:20:59 -07:00
scripts fix opae build 2020-04-20 12:51:42 -07:00
simulate set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18 2020-06-29 08:03:19 -07:00
syn minor update 2020-06-29 15:09:14 -07:00
unit_tests fpga fixes 2020-06-27 14:03:20 -07:00
.gitignore adding dram writeenable support + scheduler bug fixes 2020-05-27 19:00:23 -04:00
Makefile verilator suppor for opae (partial) 2020-06-03 06:22:49 -04:00