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vortex/simX/obj_dir/Vcache_simX__Trace.cpp
Blaise Tine 857bb54f3f remove temp files
2020-03-01 00:30:36 -05:00

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Tracing implementation internals
#include "verilated_vcd_c.h"
#include "Vcache_simX__Syms.h"
//======================
void Vcache_simX::traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code) {
// Callback from vcd->dump()
Vcache_simX* t=(Vcache_simX*)userthis;
Vcache_simX__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table
if (vlSymsp->getClearActivity()) {
t->traceChgThis (vlSymsp, vcdp, code);
}
}
//======================
void Vcache_simX::traceChgThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
int c=code;
if (0 && vcdp && c) {} // Prevent unused
// Body
{
if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity
| (vlTOPp->__Vm_traceActivity
>> 1U))))) {
vlTOPp->traceChgThis__2(vlSymsp, vcdp, code);
}
if (VL_UNLIKELY((1U & ((vlTOPp->__Vm_traceActivity
| (vlTOPp->__Vm_traceActivity
>> 1U)) | (vlTOPp->__Vm_traceActivity
>> 2U))))) {
vlTOPp->traceChgThis__3(vlSymsp, vcdp, code);
}
if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity
| (vlTOPp->__Vm_traceActivity
>> 2U))))) {
vlTOPp->traceChgThis__4(vlSymsp, vcdp, code);
}
if (VL_UNLIKELY((4U & vlTOPp->__Vm_traceActivity))) {
vlTOPp->traceChgThis__5(vlSymsp, vcdp, code);
}
vlTOPp->traceChgThis__6(vlSymsp, vcdp, code);
}
// Final
vlTOPp->__Vm_traceActivity = 0U;
}
void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
int c=code;
if (0 && vcdp && c) {} // Prevent unused
// Variables
VL_SIGW(__Vtemp686,127,0,4);
VL_SIGW(__Vtemp687,127,0,4);
VL_SIGW(__Vtemp688,127,0,4);
VL_SIGW(__Vtemp689,127,0,4);
VL_SIGW(__Vtemp690,127,0,4);
VL_SIGW(__Vtemp695,127,0,4);
VL_SIGW(__Vtemp696,127,0,4);
VL_SIGW(__Vtemp697,127,0,4);
VL_SIGW(__Vtemp698,127,0,4);
VL_SIGW(__Vtemp699,127,0,4);
VL_SIGW(__Vtemp700,127,0,4);
VL_SIGW(__Vtemp701,127,0,4);
VL_SIGW(__Vtemp702,127,0,4);
VL_SIGW(__Vtemp703,127,0,4);
VL_SIGW(__Vtemp704,127,0,4);
VL_SIGW(__Vtemp705,127,0,4);
VL_SIGW(__Vtemp706,127,0,4);
VL_SIGW(__Vtemp707,127,0,4);
VL_SIGW(__Vtemp708,127,0,4);
VL_SIGW(__Vtemp709,127,0,4);
VL_SIGW(__Vtemp710,127,0,4);
VL_SIGW(__Vtemp711,127,0,4);
VL_SIGW(__Vtemp712,127,0,4);
VL_SIGW(__Vtemp713,127,0,4);
VL_SIGW(__Vtemp714,127,0,4);
VL_SIGW(__Vtemp715,127,0,4);
VL_SIGW(__Vtemp716,127,0,4);
VL_SIGW(__Vtemp717,127,0,4);
VL_SIGW(__Vtemp718,127,0,4);
VL_SIGW(__Vtemp719,127,0,4);
VL_SIGW(__Vtemp720,127,0,4);
VL_SIGW(__Vtemp721,127,0,4);
VL_SIGW(__Vtemp722,127,0,4);
VL_SIGW(__Vtemp723,127,0,4);
VL_SIGW(__Vtemp724,127,0,4);
VL_SIGW(__Vtemp725,127,0,4);
VL_SIGW(__Vtemp726,127,0,4);
VL_SIGW(__Vtemp727,127,0,4);
VL_SIGW(__Vtemp728,127,0,4);
VL_SIGW(__Vtemp729,127,0,4);
VL_SIGW(__Vtemp730,127,0,4);
VL_SIGW(__Vtemp731,127,0,4);
VL_SIGW(__Vtemp732,127,0,4);
VL_SIGW(__Vtemp733,127,0,4);
VL_SIGW(__Vtemp734,127,0,4);
VL_SIGW(__Vtemp735,127,0,4);
VL_SIGW(__Vtemp736,127,0,4);
VL_SIGW(__Vtemp737,127,0,4);
VL_SIGW(__Vtemp738,127,0,4);
VL_SIGW(__Vtemp739,127,0,4);
// Body
{
vcdp->chgBit (c+1,((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]
<< 8U)
| (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]
>> 0x18U))))));
vcdp->chgBus (c+2,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid),4);
vcdp->chgBus (c+3,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid),4);
vcdp->chgBit (c+4,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write));
vcdp->chgArray(c+5,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address),128);
vcdp->chgBus (c+9,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read),3);
vcdp->chgBus (c+10,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write),3);
vcdp->chgBus (c+11,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read),3);
vcdp->chgBus (c+12,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write),3);
vcdp->chgArray(c+13,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual),128);
__Vtemp686[0U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U]
: 0U);
__Vtemp686[1U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U]
: 0U);
__Vtemp686[2U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U]
: 0U);
__Vtemp686[3U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U]
: 0U);
vcdp->chgArray(c+17,(__Vtemp686),128);
vcdp->chgBus (c+21,((0xfU & (((~ (IData)((0U
!= (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid)
: 0U))),4);
vcdp->chgBit (c+22,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))));
vcdp->chgBus (c+23,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read),3);
vcdp->chgArray(c+24,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address),128);
vcdp->chgArray(c+28,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data),128);
vcdp->chgBus (c+32,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid),4);
vcdp->chgBus (c+33,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid),4);
vcdp->chgArray(c+34,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data),128);
vcdp->chgBus (c+38,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr),28);
vcdp->chgArray(c+39,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata),512);
vcdp->chgArray(c+55,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata),512);
vcdp->chgBus (c+71,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we),8);
vcdp->chgBit (c+72,(((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))));
vcdp->chgBus (c+73,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),12);
vcdp->chgBus (c+74,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid),4);
vcdp->chgBit (c+75,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write));
vcdp->chgBit (c+76,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write));
vcdp->chgBit (c+77,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write));
vcdp->chgBit (c+78,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write));
vcdp->chgBus (c+79,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced),4);
vcdp->chgBus (c+80,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid),4);
vcdp->chgBus (c+81,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids),16);
vcdp->chgBus (c+82,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid),4);
vcdp->chgBus (c+83,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),8);
vcdp->chgBus (c+84,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual),4);
vcdp->chgBus (c+85,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids),3);
vcdp->chgBus (c+86,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids),3);
vcdp->chgBus (c+87,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids),3);
vcdp->chgBus (c+88,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids),3);
vcdp->chgBus (c+89,((0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))),4);
vcdp->chgBus (c+90,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)
>> 4U))),4);
vcdp->chgBus (c+91,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)
>> 8U))),4);
vcdp->chgBus (c+92,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)
>> 0xcU))),4);
vcdp->chgBus (c+93,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index),2);
vcdp->chgBit (c+94,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found));
vcdp->chgBus (c+95,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i),32);
vcdp->chgBus (c+96,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index),2);
vcdp->chgBit (c+97,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found));
vcdp->chgBus (c+98,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i),32);
vcdp->chgBus (c+99,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index),2);
vcdp->chgBit (c+100,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found));
vcdp->chgBus (c+101,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i),32);
vcdp->chgBus (c+102,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index),2);
vcdp->chgBit (c+103,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found));
vcdp->chgBus (c+104,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i),32);
vcdp->chgBus (c+105,((0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)),7);
__Vtemp687[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U];
__Vtemp687[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U];
__Vtemp687[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U];
__Vtemp687[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U];
vcdp->chgArray(c+106,(__Vtemp687),128);
vcdp->chgBus (c+110,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we))),2);
vcdp->chgBus (c+111,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 7U))),7);
__Vtemp688[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U];
__Vtemp688[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U];
__Vtemp688[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U];
__Vtemp688[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U];
vcdp->chgArray(c+112,(__Vtemp688),128);
vcdp->chgBus (c+116,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)
>> 2U))),2);
vcdp->chgBus (c+117,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 0xeU))),7);
__Vtemp689[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U];
__Vtemp689[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U];
__Vtemp689[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU];
__Vtemp689[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU];
vcdp->chgArray(c+118,(__Vtemp689),128);
vcdp->chgBus (c+122,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)
>> 4U))),2);
vcdp->chgBus (c+123,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 0x15U))),7);
__Vtemp690[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU];
__Vtemp690[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU];
__Vtemp690[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU];
__Vtemp690[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU];
vcdp->chgArray(c+124,(__Vtemp690),128);
vcdp->chgBus (c+128,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)
>> 6U))),2);
vcdp->chgBus (c+129,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[0U])),32);
vcdp->chgArray(c+130,(vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata),512);
vcdp->chgArray(c+146,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read),128);
vcdp->chgBus (c+150,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks),16);
vcdp->chgBus (c+151,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank),8);
vcdp->chgBus (c+152,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank),16);
vcdp->chgBus (c+153,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank),4);
vcdp->chgBus (c+154,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank),16);
vcdp->chgArray(c+155,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank),128);
vcdp->chgBus (c+159,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank),4);
vcdp->chgBus (c+160,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb),4);
vcdp->chgBus (c+161,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state),4);
vcdp->chgBus (c+162,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid),4);
vcdp->chgBus (c+163,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid),4);
vcdp->chgArray(c+164,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank),128);
vcdp->chgBit (c+168,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))));
vcdp->chgBus (c+169,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual),4);
vcdp->chgBus (c+170,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[0]),4);
vcdp->chgBus (c+171,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[1]),4);
vcdp->chgBus (c+172,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[2]),4);
vcdp->chgBus (c+173,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[3]),4);
vcdp->chgBus (c+174,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss),4);
vcdp->chgBus (c+175,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index),2);
vcdp->chgBit (c+176,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found));
vcdp->chgBus (c+177,((0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks))),4);
vcdp->chgBus (c+178,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))),2);
vcdp->chgBit (c+179,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))));
vcdp->chgBus (c+180,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[0U]),32);
vcdp->chgBus (c+181,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)
>> 4U))),4);
vcdp->chgBus (c+182,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 2U))),2);
vcdp->chgBit (c+183,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)
>> 1U))));
vcdp->chgBus (c+184,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[1U]),32);
vcdp->chgBus (c+185,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)
>> 8U))),4);
vcdp->chgBus (c+186,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 4U))),2);
vcdp->chgBit (c+187,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)
>> 2U))));
vcdp->chgBus (c+188,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[2U]),32);
vcdp->chgBus (c+189,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)
>> 0xcU))),4);
vcdp->chgBus (c+190,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 6U))),2);
vcdp->chgBit (c+191,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)
>> 3U))));
vcdp->chgBus (c+192,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U]),32);
vcdp->chgBus (c+193,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32);
vcdp->chgBus (c+194,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2);
vcdp->chgBus (c+195,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 0xbU))),21);
vcdp->chgBus (c+196,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 4U))),2);
vcdp->chgBus (c+197,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))),5);
vcdp->chgBit (c+198,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank))));
vcdp->chgBit (c+199,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
vcdp->chgBus (c+200,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32);
vcdp->chgBus (c+201,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2);
vcdp->chgBus (c+202,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 0xbU))),21);
vcdp->chgBus (c+203,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 4U))),2);
vcdp->chgBus (c+204,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))),5);
vcdp->chgBit (c+205,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)
>> 1U))));
vcdp->chgBit (c+206,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
vcdp->chgBus (c+207,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32);
vcdp->chgBus (c+208,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2);
vcdp->chgBus (c+209,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 0xbU))),21);
vcdp->chgBus (c+210,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 4U))),2);
vcdp->chgBus (c+211,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))),5);
vcdp->chgBit (c+212,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)
>> 2U))));
vcdp->chgBit (c+213,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
vcdp->chgBus (c+214,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32);
vcdp->chgBus (c+215,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2);
vcdp->chgBus (c+216,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 0xbU))),21);
vcdp->chgBus (c+217,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 4U))),2);
vcdp->chgBus (c+218,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))),5);
vcdp->chgBit (c+219,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)
>> 3U))));
vcdp->chgBit (c+220,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
vcdp->chgBus (c+221,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i),32);
vcdp->chgBus (c+222,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)
? ((IData)(1U)
<< (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index))
: 0U))),4);
vcdp->chgBus (c+223,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),2);
vcdp->chgBit (c+224,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found));
vcdp->chgBus (c+225,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i),32);
vcdp->chgBus (c+226,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)
? ((IData)(1U)
<< (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index))
: 0U))),4);
vcdp->chgBus (c+227,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index),2);
vcdp->chgBit (c+228,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found));
vcdp->chgBus (c+229,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i),32);
vcdp->chgBus (c+230,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)
? ((IData)(1U)
<< (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index))
: 0U))),4);
vcdp->chgBus (c+231,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index),2);
vcdp->chgBit (c+232,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found));
vcdp->chgBus (c+233,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i),32);
vcdp->chgBus (c+234,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)
? ((IData)(1U)
<< (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index))
: 0U))),4);
vcdp->chgBus (c+235,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index),2);
vcdp->chgBit (c+236,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found));
vcdp->chgBus (c+237,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i),32);
vcdp->chgBus (c+238,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank[0U])),32);
vcdp->chgArray(c+239,(vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata),512);
vcdp->chgBus (c+255,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read),32);
vcdp->chgBus (c+256,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks),4);
vcdp->chgBus (c+257,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank),4);
vcdp->chgBus (c+258,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank),4);
vcdp->chgBus (c+259,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank),4);
vcdp->chgBus (c+260,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank),4);
vcdp->chgArray(c+261,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank),128);
vcdp->chgBus (c+265,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank),4);
vcdp->chgBus (c+266,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb),4);
vcdp->chgBus (c+267,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state),4);
vcdp->chgBus (c+268,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid),1);
vcdp->chgBus (c+269,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid),1);
vcdp->chgArray(c+270,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank),128);
vcdp->chgBus (c+274,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual),1);
vcdp->chgBus (c+275,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0]),1);
vcdp->chgBus (c+276,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[1]),1);
vcdp->chgBus (c+277,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[2]),1);
vcdp->chgBus (c+278,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[3]),1);
vcdp->chgBus (c+279,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss),4);
vcdp->chgBus (c+280,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index),2);
vcdp->chgBit (c+281,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found));
vcdp->chgBus (c+282,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks))),1);
vcdp->chgBus (c+283,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank))),1);
vcdp->chgBit (c+284,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank))));
vcdp->chgBus (c+285,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[0U]),32);
vcdp->chgBus (c+286,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks)
>> 1U))),1);
vcdp->chgBus (c+287,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank)
>> 1U))),1);
vcdp->chgBit (c+288,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)
>> 1U))));
vcdp->chgBus (c+289,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[1U]),32);
vcdp->chgBus (c+290,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks)
>> 2U))),1);
vcdp->chgBus (c+291,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank)
>> 2U))),1);
vcdp->chgBit (c+292,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)
>> 2U))));
vcdp->chgBus (c+293,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[2U]),32);
vcdp->chgBus (c+294,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks)
>> 3U))),1);
vcdp->chgBus (c+295,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank)
>> 3U))),1);
vcdp->chgBit (c+296,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)
>> 3U))));
vcdp->chgBus (c+297,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[3U]),32);
vcdp->chgBus (c+298,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32);
vcdp->chgBus (c+299,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2);
vcdp->chgBus (c+300,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 0xbU))),21);
vcdp->chgBus (c+301,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 4U))),2);
vcdp->chgBus (c+302,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))),5);
vcdp->chgBit (c+303,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank))));
vcdp->chgBit (c+304,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
vcdp->chgBus (c+305,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32);
vcdp->chgBus (c+306,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2);
vcdp->chgBus (c+307,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 0xbU))),21);
vcdp->chgBus (c+308,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 4U))),2);
vcdp->chgBus (c+309,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))),5);
vcdp->chgBit (c+310,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)
>> 1U))));
vcdp->chgBit (c+311,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
vcdp->chgBus (c+312,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32);
vcdp->chgBus (c+313,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2);
vcdp->chgBus (c+314,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 0xbU))),21);
vcdp->chgBus (c+315,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 4U))),2);
vcdp->chgBus (c+316,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))),5);
vcdp->chgBit (c+317,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)
>> 2U))));
vcdp->chgBit (c+318,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
vcdp->chgBus (c+319,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32);
vcdp->chgBus (c+320,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2);
vcdp->chgBus (c+321,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 0xbU))),21);
vcdp->chgBus (c+322,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 4U))),2);
vcdp->chgBus (c+323,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))),5);
vcdp->chgBit (c+324,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)
>> 3U))));
vcdp->chgBit (c+325,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
vcdp->chgBus (c+326,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i),32);
vcdp->chgBus (c+327,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)
? ((IData)(1U)
<< (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index))
: 0U))),1);
vcdp->chgBus (c+328,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),1);
vcdp->chgBit (c+329,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found));
vcdp->chgBus (c+330,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)
? ((IData)(1U)
<< (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index))
: 0U))),1);
vcdp->chgBus (c+331,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index),1);
vcdp->chgBit (c+332,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found));
vcdp->chgBus (c+333,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)
? ((IData)(1U)
<< (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index))
: 0U))),1);
vcdp->chgBus (c+334,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index),1);
vcdp->chgBit (c+335,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found));
vcdp->chgBus (c+336,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)
? ((IData)(1U)
<< (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index))
: 0U))),1);
vcdp->chgBus (c+337,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index),1);
vcdp->chgBit (c+338,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found));
vcdp->chgBus (c+339,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid),4);
__Vtemp695[0U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]
<< 8U)
| (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]
>> 0x18U))))
? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U]
: 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U]);
__Vtemp695[1U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]
<< 8U)
| (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]
>> 0x18U))))
? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U]
: 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U]);
__Vtemp695[2U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]
<< 8U)
| (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]
>> 0x18U))))
? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U]
: 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U]);
__Vtemp695[3U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]
<< 8U)
| (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]
>> 0x18U))))
? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U]
: 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U]);
vcdp->chgArray(c+340,(__Vtemp695),128);
vcdp->chgBus (c+344,(0U),32);
vcdp->chgBus (c+345,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x8000U
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U
== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))
: 0U)),32);
vcdp->chgBit (c+346,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use
== (0x1fffffU &
(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 0xbU))))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use))));
vcdp->chgBit (c+347,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way)
>> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
vcdp->chgBus (c+348,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use
<< 0xbU) | (0x7c0U
& vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))),32);
vcdp->chgArray(c+349,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
vcdp->chgBus (c+353,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21);
vcdp->chgBit (c+354,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use));
vcdp->chgBit (c+355,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access));
vcdp->chgBit (c+356,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem));
vcdp->chgBit (c+357,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use
!= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 0xbU)))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use))
& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in))));
vcdp->chgBit (c+358,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
vcdp->chgBit (c+359,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
vcdp->chgBit (c+360,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
vcdp->chgBit (c+361,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
vcdp->chgBit (c+362,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
vcdp->chgBit (c+363,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
vcdp->chgBit (c+364,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
vcdp->chgBit (c+365,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
vcdp->chgBit (c+366,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
vcdp->chgBus (c+367,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32);
vcdp->chgBus (c+368,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+369,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+370,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+371,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+372,(0U),32);
vcdp->chgBus (c+373,(0U),32);
vcdp->chgBus (c+374,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
vcdp->chgBus (c+375,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4);
vcdp->chgBus (c+376,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
? 3U : 0xcU)),4);
vcdp->chgBus (c+377,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16);
vcdp->chgArray(c+378,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128);
vcdp->chgQuad (c+382,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
vcdp->chgArray(c+384,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
vcdp->chgBus (c+392,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
vcdp->chgBus (c+393,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
vcdp->chgBus (c+394,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
vcdp->chgBus (c+395,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
vcdp->chgArray(c+396,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
vcdp->chgBus (c+404,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
vcdp->chgBit (c+405,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
vcdp->chgBus (c+406,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
vcdp->chgBus (c+407,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
vcdp->chgBus (c+408,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
vcdp->chgBus (c+409,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
vcdp->chgBit (c+410,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
vcdp->chgBus (c+411,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
vcdp->chgBit (c+412,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
__Vtemp696[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
__Vtemp696[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
__Vtemp696[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
__Vtemp696[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
vcdp->chgArray(c+413,(__Vtemp696),128);
vcdp->chgBit (c+417,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+418,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
vcdp->chgBit (c+419,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))
| (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
vcdp->chgBit (c+420,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
vcdp->chgBus (c+421,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))),16);
vcdp->chgBit (c+422,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U))));
__Vtemp697[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
__Vtemp697[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
__Vtemp697[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
__Vtemp697[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
vcdp->chgArray(c+423,(__Vtemp697),128);
vcdp->chgBit (c+427,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+428,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))));
vcdp->chgBit (c+429,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))))
| ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U)))));
vcdp->chgBit (c+430,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))))));
vcdp->chgBus (c+431,(0U),32);
vcdp->chgBus (c+432,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x8000U
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U
== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))
: 0U)),32);
vcdp->chgBit (c+433,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use
== (0x1fffffU &
(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 0xbU))))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use))));
vcdp->chgBit (c+434,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way)
>> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
vcdp->chgBus (c+435,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use
<< 0xbU) | (0x7c0U
& vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))),32);
vcdp->chgArray(c+436,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
vcdp->chgBus (c+440,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21);
vcdp->chgBit (c+441,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use));
vcdp->chgBit (c+442,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access));
vcdp->chgBit (c+443,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem));
vcdp->chgBit (c+444,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use
!= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 0xbU)))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use))
& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in))));
vcdp->chgBit (c+445,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
vcdp->chgBit (c+446,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
vcdp->chgBit (c+447,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
vcdp->chgBit (c+448,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
vcdp->chgBus (c+449,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32);
vcdp->chgBus (c+450,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+451,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+452,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+453,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+454,(0U),32);
vcdp->chgBus (c+455,(0U),32);
vcdp->chgBus (c+456,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
vcdp->chgBus (c+457,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4);
vcdp->chgBus (c+458,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
? 3U : 0xcU)),4);
vcdp->chgBus (c+459,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16);
vcdp->chgArray(c+460,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128);
vcdp->chgQuad (c+464,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
vcdp->chgArray(c+466,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
vcdp->chgBus (c+474,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
vcdp->chgBus (c+475,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
vcdp->chgBus (c+476,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
vcdp->chgBus (c+477,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
vcdp->chgArray(c+478,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
vcdp->chgBus (c+486,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
vcdp->chgBit (c+487,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
vcdp->chgBus (c+488,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
vcdp->chgBus (c+489,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
vcdp->chgBus (c+490,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
vcdp->chgBus (c+491,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
vcdp->chgBit (c+492,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
vcdp->chgBus (c+493,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
vcdp->chgBit (c+494,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
__Vtemp698[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
__Vtemp698[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
__Vtemp698[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
__Vtemp698[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
vcdp->chgArray(c+495,(__Vtemp698),128);
vcdp->chgBit (c+499,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+500,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
vcdp->chgBit (c+501,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))
| (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
vcdp->chgBit (c+502,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
vcdp->chgBus (c+503,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))),16);
vcdp->chgBit (c+504,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U))));
__Vtemp699[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
__Vtemp699[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
__Vtemp699[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
__Vtemp699[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
vcdp->chgArray(c+505,(__Vtemp699),128);
vcdp->chgBit (c+509,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+510,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))));
vcdp->chgBit (c+511,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))))
| ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U)))));
vcdp->chgBit (c+512,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))))));
vcdp->chgBus (c+513,(0U),32);
vcdp->chgBus (c+514,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x8000U
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U
== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))
: 0U)),32);
vcdp->chgBit (c+515,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use
== (0x1fffffU &
(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 0xbU))))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use))));
vcdp->chgBit (c+516,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way)
>> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
vcdp->chgBus (c+517,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use
<< 0xbU) | (0x7c0U
& vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))),32);
vcdp->chgArray(c+518,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
vcdp->chgBus (c+522,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21);
vcdp->chgBit (c+523,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use));
vcdp->chgBit (c+524,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access));
vcdp->chgBit (c+525,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem));
vcdp->chgBit (c+526,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use
!= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 0xbU)))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use))
& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in))));
vcdp->chgBit (c+527,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
vcdp->chgBit (c+528,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
vcdp->chgBit (c+529,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
vcdp->chgBit (c+530,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
vcdp->chgBus (c+531,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32);
vcdp->chgBus (c+532,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+533,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+534,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+535,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+536,(0U),32);
vcdp->chgBus (c+537,(0U),32);
vcdp->chgBus (c+538,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
vcdp->chgBus (c+539,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4);
vcdp->chgBus (c+540,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
? 3U : 0xcU)),4);
vcdp->chgBus (c+541,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16);
vcdp->chgArray(c+542,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128);
vcdp->chgQuad (c+546,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
vcdp->chgArray(c+548,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
vcdp->chgBus (c+556,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
vcdp->chgBus (c+557,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
vcdp->chgBus (c+558,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
vcdp->chgBus (c+559,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
vcdp->chgArray(c+560,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
vcdp->chgBus (c+568,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
vcdp->chgBit (c+569,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
vcdp->chgBus (c+570,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
vcdp->chgBus (c+571,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
vcdp->chgBus (c+572,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
vcdp->chgBus (c+573,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
vcdp->chgBit (c+574,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
vcdp->chgBus (c+575,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
vcdp->chgBit (c+576,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
__Vtemp700[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
__Vtemp700[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
__Vtemp700[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
__Vtemp700[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
vcdp->chgArray(c+577,(__Vtemp700),128);
vcdp->chgBit (c+581,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+582,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
vcdp->chgBit (c+583,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))
| (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
vcdp->chgBit (c+584,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
vcdp->chgBus (c+585,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))),16);
vcdp->chgBit (c+586,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U))));
__Vtemp701[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
__Vtemp701[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
__Vtemp701[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
__Vtemp701[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
vcdp->chgArray(c+587,(__Vtemp701),128);
vcdp->chgBit (c+591,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+592,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))));
vcdp->chgBit (c+593,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))))
| ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U)))));
vcdp->chgBit (c+594,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))))));
vcdp->chgBus (c+595,(0U),32);
vcdp->chgBus (c+596,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x8000U
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U
== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))
: 0U)),32);
vcdp->chgBit (c+597,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use
== (0x1fffffU &
(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 0xbU))))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use))));
vcdp->chgBit (c+598,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way)
>> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
vcdp->chgBus (c+599,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use
<< 0xbU) | (0x7c0U
& vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))),32);
vcdp->chgArray(c+600,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
vcdp->chgBus (c+604,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21);
vcdp->chgBit (c+605,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use));
vcdp->chgBit (c+606,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access));
vcdp->chgBit (c+607,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem));
vcdp->chgBit (c+608,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use
!= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 0xbU)))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use))
& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in))));
vcdp->chgBit (c+609,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
vcdp->chgBit (c+610,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
vcdp->chgBit (c+611,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
vcdp->chgBit (c+612,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
vcdp->chgBus (c+613,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32);
vcdp->chgBus (c+614,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+615,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+616,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+617,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+618,(0U),32);
vcdp->chgBus (c+619,(0U),32);
vcdp->chgBus (c+620,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
vcdp->chgBus (c+621,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4);
vcdp->chgBus (c+622,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
? 3U : 0xcU)),4);
vcdp->chgBus (c+623,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16);
vcdp->chgArray(c+624,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128);
vcdp->chgQuad (c+628,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
vcdp->chgArray(c+630,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
vcdp->chgBus (c+638,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
vcdp->chgBus (c+639,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
vcdp->chgBus (c+640,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
vcdp->chgBus (c+641,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
vcdp->chgArray(c+642,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
vcdp->chgBus (c+650,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
vcdp->chgBit (c+651,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
vcdp->chgBus (c+652,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
vcdp->chgBus (c+653,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
vcdp->chgBus (c+654,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
vcdp->chgBus (c+655,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
vcdp->chgBit (c+656,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
vcdp->chgBus (c+657,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
vcdp->chgBit (c+658,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
__Vtemp702[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
__Vtemp702[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
__Vtemp702[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
__Vtemp702[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
vcdp->chgArray(c+659,(__Vtemp702),128);
vcdp->chgBit (c+663,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+664,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
vcdp->chgBit (c+665,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))
| (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
vcdp->chgBit (c+666,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
vcdp->chgBus (c+667,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))),16);
vcdp->chgBit (c+668,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U))));
__Vtemp703[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
__Vtemp703[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
__Vtemp703[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
__Vtemp703[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
vcdp->chgArray(c+669,(__Vtemp703),128);
vcdp->chgBit (c+673,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+674,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))));
vcdp->chgBit (c+675,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))))
| ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U)))));
vcdp->chgBit (c+676,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))))));
__Vtemp704[0U] = 0U;
__Vtemp704[1U] = 0U;
__Vtemp704[2U] = 0U;
__Vtemp704[3U] = 0U;
vcdp->chgBus (c+677,(__Vtemp704[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]),32);
vcdp->chgBus (c+678,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x8000U
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U
== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))
: 0U)),32);
vcdp->chgBit (c+679,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use
== (0x1fffffU &
(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 0xbU))))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use))));
vcdp->chgBit (c+680,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way)
>> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
vcdp->chgBus (c+681,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use
<< 0xbU) | (0x7c0U
& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))),32);
vcdp->chgArray(c+682,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
vcdp->chgBus (c+686,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21);
vcdp->chgBit (c+687,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use));
vcdp->chgBit (c+688,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access));
vcdp->chgBit (c+689,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem));
vcdp->chgBit (c+690,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__miss));
vcdp->chgBit (c+691,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
vcdp->chgBit (c+692,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
vcdp->chgBit (c+693,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
vcdp->chgBit (c+694,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
vcdp->chgBit (c+695,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
vcdp->chgBit (c+696,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
vcdp->chgBit (c+697,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
vcdp->chgBit (c+698,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
vcdp->chgBit (c+699,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
vcdp->chgBit (c+700,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
vcdp->chgBit (c+701,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
vcdp->chgBit (c+702,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
vcdp->chgBus (c+703,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32);
vcdp->chgBus (c+704,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+705,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+706,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+707,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
__Vtemp705[0U] = 0U;
__Vtemp705[1U] = 0U;
__Vtemp705[2U] = 0U;
__Vtemp705[3U] = 0U;
__Vtemp706[0U] = 0U;
__Vtemp706[1U] = 0U;
__Vtemp706[2U] = 0U;
__Vtemp706[3U] = 0U;
__Vtemp707[0U] = 0U;
__Vtemp707[1U] = 0U;
__Vtemp707[2U] = 0U;
__Vtemp707[3U] = 0U;
__Vtemp708[0U] = 0U;
__Vtemp708[1U] = 0U;
__Vtemp708[2U] = 0U;
__Vtemp708[3U] = 0U;
vcdp->chgBus (c+708,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
? (0xff00U & (__Vtemp705[
(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]
<< 8U))
: ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
? (0xff0000U &
(__Vtemp706[
(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]
<< 0x10U)) :
((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
? (0xff000000U
& (__Vtemp707[
(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]
<< 0x18U))
: __Vtemp708[(3U
& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])))),32);
__Vtemp709[0U] = 0U;
__Vtemp709[1U] = 0U;
__Vtemp709[2U] = 0U;
__Vtemp709[3U] = 0U;
__Vtemp710[0U] = 0U;
__Vtemp710[1U] = 0U;
__Vtemp710[2U] = 0U;
__Vtemp710[3U] = 0U;
vcdp->chgBus (c+709,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
? (0xffff0000U & (__Vtemp709[
(3U
& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]
<< 0x10U))
: __Vtemp710[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])),32);
vcdp->chgBus (c+710,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__use_write_data),32);
vcdp->chgBus (c+711,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
vcdp->chgBus (c+712,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4);
vcdp->chgBus (c+713,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
? 3U : 0xcU)),4);
vcdp->chgBus (c+714,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16);
vcdp->chgArray(c+715,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128);
vcdp->chgBit (c+719,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
vcdp->chgBit (c+720,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
vcdp->chgBit (c+721,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
vcdp->chgBit (c+722,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
vcdp->chgQuad (c+723,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
vcdp->chgArray(c+725,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
vcdp->chgBus (c+733,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
vcdp->chgBus (c+734,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
vcdp->chgBus (c+735,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
vcdp->chgBus (c+736,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
vcdp->chgArray(c+737,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
vcdp->chgBus (c+745,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
vcdp->chgBit (c+746,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
vcdp->chgBus (c+747,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
vcdp->chgBus (c+748,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
vcdp->chgBus (c+749,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
vcdp->chgBus (c+750,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
vcdp->chgBit (c+751,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
vcdp->chgBus (c+752,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
vcdp->chgBit (c+753,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
__Vtemp711[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
__Vtemp711[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
__Vtemp711[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
__Vtemp711[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
vcdp->chgArray(c+754,(__Vtemp711),128);
vcdp->chgBit (c+758,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+759,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
vcdp->chgBit (c+760,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))
| (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
vcdp->chgBit (c+761,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
vcdp->chgBus (c+762,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))),16);
vcdp->chgBit (c+763,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U))));
__Vtemp712[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
__Vtemp712[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
__Vtemp712[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
__Vtemp712[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
vcdp->chgArray(c+764,(__Vtemp712),128);
vcdp->chgBit (c+768,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+769,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))));
vcdp->chgBit (c+770,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))))
| ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U)))));
vcdp->chgBit (c+771,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))))));
__Vtemp713[0U] = 0U;
__Vtemp713[1U] = 0U;
__Vtemp713[2U] = 0U;
__Vtemp713[3U] = 0U;
vcdp->chgBus (c+772,(__Vtemp713[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 2U))]),32);
vcdp->chgBus (c+773,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x8000U
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U
== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))
: 0U)),32);
vcdp->chgBit (c+774,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use
== (0x1fffffU &
(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 0xbU))))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use))));
vcdp->chgBit (c+775,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way)
>> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
vcdp->chgBus (c+776,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use
<< 0xbU) | (0x7c0U
& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))),32);
vcdp->chgArray(c+777,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
vcdp->chgBus (c+781,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21);
vcdp->chgBit (c+782,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use));
vcdp->chgBit (c+783,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access));
vcdp->chgBit (c+784,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem));
vcdp->chgBit (c+785,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__miss));
vcdp->chgBit (c+786,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
vcdp->chgBit (c+787,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
vcdp->chgBit (c+788,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
vcdp->chgBit (c+789,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
vcdp->chgBus (c+790,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32);
vcdp->chgBus (c+791,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+792,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+793,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+794,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
__Vtemp714[0U] = 0U;
__Vtemp714[1U] = 0U;
__Vtemp714[2U] = 0U;
__Vtemp714[3U] = 0U;
__Vtemp715[0U] = 0U;
__Vtemp715[1U] = 0U;
__Vtemp715[2U] = 0U;
__Vtemp715[3U] = 0U;
__Vtemp716[0U] = 0U;
__Vtemp716[1U] = 0U;
__Vtemp716[2U] = 0U;
__Vtemp716[3U] = 0U;
__Vtemp717[0U] = 0U;
__Vtemp717[1U] = 0U;
__Vtemp717[2U] = 0U;
__Vtemp717[3U] = 0U;
vcdp->chgBus (c+795,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
? (0xff00U & (__Vtemp714[
(3U &
((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 2U))]
<< 8U))
: ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
? (0xff0000U &
(__Vtemp715[
(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 2U))]
<< 0x10U)) :
((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
? (0xff000000U
& (__Vtemp716[
(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 2U))]
<< 0x18U))
: __Vtemp717[(3U
& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 2U))])))),32);
__Vtemp718[0U] = 0U;
__Vtemp718[1U] = 0U;
__Vtemp718[2U] = 0U;
__Vtemp718[3U] = 0U;
__Vtemp719[0U] = 0U;
__Vtemp719[1U] = 0U;
__Vtemp719[2U] = 0U;
__Vtemp719[3U] = 0U;
vcdp->chgBus (c+796,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
? (0xffff0000U & (__Vtemp718[
(3U
& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 2U))]
<< 0x10U))
: __Vtemp719[(3U &
((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 2U))])),32);
vcdp->chgBus (c+797,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__use_write_data),32);
vcdp->chgBus (c+798,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
vcdp->chgBus (c+799,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4);
vcdp->chgBus (c+800,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
? 3U : 0xcU)),4);
vcdp->chgBus (c+801,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16);
vcdp->chgArray(c+802,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128);
vcdp->chgBit (c+806,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
vcdp->chgBit (c+807,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
vcdp->chgBit (c+808,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
vcdp->chgBit (c+809,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
vcdp->chgQuad (c+810,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
vcdp->chgArray(c+812,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
vcdp->chgBus (c+820,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
vcdp->chgBus (c+821,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
vcdp->chgBus (c+822,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
vcdp->chgBus (c+823,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
vcdp->chgArray(c+824,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
vcdp->chgBus (c+832,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
vcdp->chgBit (c+833,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
vcdp->chgBus (c+834,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
vcdp->chgBus (c+835,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
vcdp->chgBus (c+836,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
vcdp->chgBus (c+837,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
vcdp->chgBit (c+838,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
vcdp->chgBus (c+839,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
vcdp->chgBit (c+840,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
__Vtemp720[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
__Vtemp720[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
__Vtemp720[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
__Vtemp720[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
vcdp->chgArray(c+841,(__Vtemp720),128);
vcdp->chgBit (c+845,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+846,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
vcdp->chgBit (c+847,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))
| (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
vcdp->chgBit (c+848,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
vcdp->chgBus (c+849,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))),16);
vcdp->chgBit (c+850,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U))));
__Vtemp721[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
__Vtemp721[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
__Vtemp721[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
__Vtemp721[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
vcdp->chgArray(c+851,(__Vtemp721),128);
vcdp->chgBit (c+855,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+856,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))));
vcdp->chgBit (c+857,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))))
| ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U)))));
vcdp->chgBit (c+858,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))))));
__Vtemp722[0U] = 0U;
__Vtemp722[1U] = 0U;
__Vtemp722[2U] = 0U;
__Vtemp722[3U] = 0U;
vcdp->chgBus (c+859,(__Vtemp722[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 4U))]),32);
vcdp->chgBus (c+860,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x8000U
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U
== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))
: 0U)),32);
vcdp->chgBit (c+861,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use
== (0x1fffffU &
(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 0xbU))))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use))));
vcdp->chgBit (c+862,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way)
>> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
vcdp->chgBus (c+863,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use
<< 0xbU) | (0x7c0U
& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))),32);
vcdp->chgArray(c+864,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
vcdp->chgBus (c+868,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21);
vcdp->chgBit (c+869,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use));
vcdp->chgBit (c+870,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access));
vcdp->chgBit (c+871,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem));
vcdp->chgBit (c+872,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__miss));
vcdp->chgBit (c+873,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
vcdp->chgBit (c+874,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
vcdp->chgBit (c+875,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
vcdp->chgBit (c+876,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
vcdp->chgBus (c+877,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32);
vcdp->chgBus (c+878,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+879,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+880,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+881,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
__Vtemp723[0U] = 0U;
__Vtemp723[1U] = 0U;
__Vtemp723[2U] = 0U;
__Vtemp723[3U] = 0U;
__Vtemp724[0U] = 0U;
__Vtemp724[1U] = 0U;
__Vtemp724[2U] = 0U;
__Vtemp724[3U] = 0U;
__Vtemp725[0U] = 0U;
__Vtemp725[1U] = 0U;
__Vtemp725[2U] = 0U;
__Vtemp725[3U] = 0U;
__Vtemp726[0U] = 0U;
__Vtemp726[1U] = 0U;
__Vtemp726[2U] = 0U;
__Vtemp726[3U] = 0U;
vcdp->chgBus (c+882,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
? (0xff00U & (__Vtemp723[
(3U &
((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 4U))]
<< 8U))
: ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
? (0xff0000U &
(__Vtemp724[
(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 4U))]
<< 0x10U)) :
((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
? (0xff000000U
& (__Vtemp725[
(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 4U))]
<< 0x18U))
: __Vtemp726[(3U
& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 4U))])))),32);
__Vtemp727[0U] = 0U;
__Vtemp727[1U] = 0U;
__Vtemp727[2U] = 0U;
__Vtemp727[3U] = 0U;
__Vtemp728[0U] = 0U;
__Vtemp728[1U] = 0U;
__Vtemp728[2U] = 0U;
__Vtemp728[3U] = 0U;
vcdp->chgBus (c+883,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
? (0xffff0000U & (__Vtemp727[
(3U
& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 4U))]
<< 0x10U))
: __Vtemp728[(3U &
((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 4U))])),32);
vcdp->chgBus (c+884,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__use_write_data),32);
vcdp->chgBus (c+885,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
vcdp->chgBus (c+886,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4);
vcdp->chgBus (c+887,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
? 3U : 0xcU)),4);
vcdp->chgBus (c+888,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16);
vcdp->chgArray(c+889,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128);
vcdp->chgBit (c+893,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
vcdp->chgBit (c+894,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
vcdp->chgBit (c+895,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
vcdp->chgBit (c+896,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
vcdp->chgQuad (c+897,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
vcdp->chgArray(c+899,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
vcdp->chgBus (c+907,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
vcdp->chgBus (c+908,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
vcdp->chgBus (c+909,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
vcdp->chgBus (c+910,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
vcdp->chgArray(c+911,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
vcdp->chgBus (c+919,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
vcdp->chgBit (c+920,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
vcdp->chgBus (c+921,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
vcdp->chgBus (c+922,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
vcdp->chgBus (c+923,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
vcdp->chgBus (c+924,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
vcdp->chgBit (c+925,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
vcdp->chgBus (c+926,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
vcdp->chgBit (c+927,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
__Vtemp729[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
__Vtemp729[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
__Vtemp729[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
__Vtemp729[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
vcdp->chgArray(c+928,(__Vtemp729),128);
vcdp->chgBit (c+932,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+933,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
vcdp->chgBit (c+934,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))
| (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
vcdp->chgBit (c+935,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
vcdp->chgBus (c+936,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))),16);
vcdp->chgBit (c+937,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U))));
__Vtemp730[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
__Vtemp730[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
__Vtemp730[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
__Vtemp730[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
vcdp->chgArray(c+938,(__Vtemp730),128);
vcdp->chgBit (c+942,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+943,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))));
vcdp->chgBit (c+944,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))))
| ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U)))));
vcdp->chgBit (c+945,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))))));
__Vtemp731[0U] = 0U;
__Vtemp731[1U] = 0U;
__Vtemp731[2U] = 0U;
__Vtemp731[3U] = 0U;
vcdp->chgBus (c+946,(__Vtemp731[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 6U))]),32);
vcdp->chgBus (c+947,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x8000U
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U
== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))
: 0U)),32);
vcdp->chgBit (c+948,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use
== (0x1fffffU &
(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 0xbU))))
& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use))));
vcdp->chgBit (c+949,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way)
>> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
vcdp->chgBus (c+950,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use
<< 0xbU) | (0x7c0U
& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))),32);
vcdp->chgArray(c+951,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
vcdp->chgBus (c+955,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21);
vcdp->chgBit (c+956,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use));
vcdp->chgBit (c+957,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access));
vcdp->chgBit (c+958,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem));
vcdp->chgBit (c+959,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__miss));
vcdp->chgBit (c+960,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
vcdp->chgBit (c+961,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
vcdp->chgBit (c+962,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
vcdp->chgBit (c+963,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
vcdp->chgBus (c+964,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32);
vcdp->chgBus (c+965,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+966,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
vcdp->chgBus (c+967,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
vcdp->chgBus (c+968,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
__Vtemp732[0U] = 0U;
__Vtemp732[1U] = 0U;
__Vtemp732[2U] = 0U;
__Vtemp732[3U] = 0U;
__Vtemp733[0U] = 0U;
__Vtemp733[1U] = 0U;
__Vtemp733[2U] = 0U;
__Vtemp733[3U] = 0U;
__Vtemp734[0U] = 0U;
__Vtemp734[1U] = 0U;
__Vtemp734[2U] = 0U;
__Vtemp734[3U] = 0U;
__Vtemp735[0U] = 0U;
__Vtemp735[1U] = 0U;
__Vtemp735[2U] = 0U;
__Vtemp735[3U] = 0U;
vcdp->chgBus (c+969,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
? (0xff00U & (__Vtemp732[
(3U &
((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 6U))]
<< 8U))
: ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
? (0xff0000U &
(__Vtemp733[
(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 6U))]
<< 0x10U)) :
((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
? (0xff000000U
& (__Vtemp734[
(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 6U))]
<< 0x18U))
: __Vtemp735[(3U
& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 6U))])))),32);
__Vtemp736[0U] = 0U;
__Vtemp736[1U] = 0U;
__Vtemp736[2U] = 0U;
__Vtemp736[3U] = 0U;
__Vtemp737[0U] = 0U;
__Vtemp737[1U] = 0U;
__Vtemp737[2U] = 0U;
__Vtemp737[3U] = 0U;
vcdp->chgBus (c+970,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
? (0xffff0000U & (__Vtemp736[
(3U
& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 6U))]
<< 0x10U))
: __Vtemp737[(3U &
((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)
>> 6U))])),32);
vcdp->chgBus (c+971,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__use_write_data),32);
vcdp->chgBus (c+972,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffffff00U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
: ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
? (0xffff0000U
| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
: ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
? (0xffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
: vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
vcdp->chgBus (c+973,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4);
vcdp->chgBus (c+974,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
? 3U : 0xcU)),4);
vcdp->chgBus (c+975,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16);
vcdp->chgArray(c+976,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128);
vcdp->chgBit (c+980,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
vcdp->chgBit (c+981,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
vcdp->chgBit (c+982,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
vcdp->chgBit (c+983,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
vcdp->chgQuad (c+984,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
vcdp->chgArray(c+986,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
vcdp->chgBus (c+994,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
vcdp->chgBus (c+995,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
vcdp->chgBus (c+996,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
vcdp->chgBus (c+997,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
vcdp->chgArray(c+998,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
vcdp->chgBus (c+1006,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
vcdp->chgBit (c+1007,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
vcdp->chgBus (c+1008,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
vcdp->chgBus (c+1009,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
vcdp->chgBus (c+1010,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
vcdp->chgBus (c+1011,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
vcdp->chgBit (c+1012,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
vcdp->chgBus (c+1013,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
vcdp->chgBit (c+1014,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
__Vtemp738[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
__Vtemp738[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
__Vtemp738[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
__Vtemp738[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
vcdp->chgArray(c+1015,(__Vtemp738),128);
vcdp->chgBit (c+1019,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+1020,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
vcdp->chgBit (c+1021,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))
| (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
vcdp->chgBit (c+1022,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
vcdp->chgBus (c+1023,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))),16);
vcdp->chgBit (c+1024,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U))));
__Vtemp739[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
__Vtemp739[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
__Vtemp739[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
__Vtemp739[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
vcdp->chgArray(c+1025,(__Vtemp739),128);
vcdp->chgBit (c+1029,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
vcdp->chgBit (c+1030,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))));
vcdp->chgBit (c+1031,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use))
& (0U != (0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U))))
| ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)
>> 1U)))));
vcdp->chgBit (c+1032,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
? 0U : (0U !=
(0xffffU
& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way
>> 0x10U)))))));
}
}
void Vcache_simX::traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
int c=code;
if (0 && vcdp && c) {} // Prevent unused
// Variables
VL_SIGW(__Vtemp752,127,0,4);
VL_SIGW(__Vtemp753,127,0,4);
VL_SIGW(__Vtemp754,127,0,4);
VL_SIGW(__Vtemp755,127,0,4);
VL_SIGW(__Vtemp756,127,0,4);
VL_SIGW(__Vtemp757,127,0,4);
VL_SIGW(__Vtemp758,127,0,4);
VL_SIGW(__Vtemp759,127,0,4);
VL_SIGW(__Vtemp760,127,0,4);
VL_SIGW(__Vtemp761,127,0,4);
VL_SIGW(__Vtemp762,127,0,4);
VL_SIGW(__Vtemp763,127,0,4);
VL_SIGW(__Vtemp764,127,0,4);
VL_SIGW(__Vtemp765,127,0,4);
VL_SIGW(__Vtemp766,127,0,4);
VL_SIGW(__Vtemp767,127,0,4);
VL_SIGW(__Vtemp742,127,0,4);
VL_SIGW(__Vtemp745,127,0,4);
VL_SIGW(__Vtemp748,127,0,4);
VL_SIGW(__Vtemp751,127,0,4);
// Body
{
vcdp->chgBit (c+1033,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid))
| (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))));
vcdp->chgBus (c+1034,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual)
? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read
: vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read)),32);
vcdp->chgBit (c+1035,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid)
| (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)))));
vcdp->chgBit (c+1036,((1U & ((~ ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid))
| (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))))
& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)))));
vcdp->chgBus (c+1037,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)
& (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))
: ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)
& (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))))),4);
__Vtemp742[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]);
__Vtemp742[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]);
__Vtemp742[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]);
__Vtemp742[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]);
vcdp->chgArray(c+1038,(__Vtemp742),128);
__Vtemp745[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 7U))][0U]);
__Vtemp745[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 7U))][1U]);
__Vtemp745[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 7U))][2U]);
__Vtemp745[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 7U))][3U]);
vcdp->chgArray(c+1042,(__Vtemp745),128);
__Vtemp748[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 0xeU))][0U]);
__Vtemp748[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 0xeU))][1U]);
__Vtemp748[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 0xeU))][2U]);
__Vtemp748[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 0xeU))][3U]);
vcdp->chgArray(c+1046,(__Vtemp748),128);
__Vtemp751[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 0x15U))][0U]);
__Vtemp751[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 0x15U))][1U]);
__Vtemp751[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 0x15U))][2U]);
__Vtemp751[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
[(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr
>> 0x15U))][3U]);
vcdp->chgArray(c+1050,(__Vtemp751),128);
vcdp->chgBit (c+1054,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)))));
vcdp->chgBit (c+1055,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
& (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state)))));
vcdp->chgBit (c+1056,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb)))));
vcdp->chgBit (c+1057,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
& (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state)))));
vcdp->chgBit (c+1058,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))
| ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid))
| (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))))));
vcdp->chgBus (c+1059,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp752[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp752[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp752[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp752[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1060,(__Vtemp752),128);
vcdp->chgBit (c+1064,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1065,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp753[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp753[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp753[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp753[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1066,(__Vtemp753),128);
vcdp->chgBit (c+1070,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1071,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp754[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp754[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp754[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp754[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1072,(__Vtemp754),128);
vcdp->chgBit (c+1076,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1077,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp755[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp755[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp755[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp755[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1078,(__Vtemp755),128);
vcdp->chgBit (c+1082,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1083,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp756[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp756[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp756[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp756[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1084,(__Vtemp756),128);
vcdp->chgBit (c+1088,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1089,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp757[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp757[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp757[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp757[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1090,(__Vtemp757),128);
vcdp->chgBit (c+1094,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1095,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp758[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp758[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp758[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp758[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1096,(__Vtemp758),128);
vcdp->chgBit (c+1100,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1101,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp759[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp759[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp759[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp759[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1102,(__Vtemp759),128);
vcdp->chgBit (c+1106,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1107,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp760[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp760[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp760[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp760[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1108,(__Vtemp760),128);
vcdp->chgBit (c+1112,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1113,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp761[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp761[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp761[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp761[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1114,(__Vtemp761),128);
vcdp->chgBit (c+1118,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1119,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp762[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp762[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp762[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp762[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1120,(__Vtemp762),128);
vcdp->chgBit (c+1124,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1125,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp763[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp763[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp763[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp763[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1126,(__Vtemp763),128);
vcdp->chgBit (c+1130,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1131,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp764[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp764[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp764[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp764[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1132,(__Vtemp764),128);
vcdp->chgBit (c+1136,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1137,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp765[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp765[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp765[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp765[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1138,(__Vtemp765),128);
vcdp->chgBit (c+1142,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1143,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp766[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp766[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp766[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp766[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1144,(__Vtemp766),128);
vcdp->chgBit (c+1148,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))]));
vcdp->chgBus (c+1149,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))]),21);
__Vtemp767[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][0U];
__Vtemp767[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][1U];
__Vtemp767[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][2U];
__Vtemp767[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))][3U];
vcdp->chgArray(c+1150,(__Vtemp767),128);
vcdp->chgBit (c+1154,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr
>> 6U))]));
}
}
void Vcache_simX::traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
int c=code;
if (0 && vcdp && c) {} // Prevent unused
// Body
{
vcdp->chgBus (c+1155,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__way_to_update),1);
vcdp->chgBus (c+1156,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__way_to_update),1);
vcdp->chgBus (c+1157,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__way_to_update),1);
vcdp->chgBus (c+1158,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__way_to_update),1);
vcdp->chgBus (c+1159,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__way_to_update),1);
vcdp->chgBus (c+1160,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__way_to_update),1);
vcdp->chgBus (c+1161,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__way_to_update),1);
vcdp->chgBus (c+1162,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__way_to_update),1);
}
}
void Vcache_simX::traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
int c=code;
if (0 && vcdp && c) {} // Prevent unused
// Variables
VL_SIGW(__Vtemp768,127,0,4);
VL_SIGW(__Vtemp769,127,0,4);
VL_SIGW(__Vtemp770,127,0,4);
VL_SIGW(__Vtemp771,127,0,4);
VL_SIGW(__Vtemp772,127,0,4);
VL_SIGW(__Vtemp773,127,0,4);
VL_SIGW(__Vtemp774,127,0,4);
VL_SIGW(__Vtemp775,127,0,4);
VL_SIGW(__Vtemp776,127,0,4);
VL_SIGW(__Vtemp777,127,0,4);
VL_SIGW(__Vtemp778,127,0,4);
VL_SIGW(__Vtemp779,127,0,4);
VL_SIGW(__Vtemp780,127,0,4);
VL_SIGW(__Vtemp781,127,0,4);
VL_SIGW(__Vtemp782,127,0,4);
VL_SIGW(__Vtemp783,127,0,4);
VL_SIGW(__Vtemp784,127,0,4);
VL_SIGW(__Vtemp785,127,0,4);
VL_SIGW(__Vtemp786,127,0,4);
VL_SIGW(__Vtemp787,127,0,4);
VL_SIGW(__Vtemp788,127,0,4);
VL_SIGW(__Vtemp789,127,0,4);
VL_SIGW(__Vtemp790,127,0,4);
VL_SIGW(__Vtemp791,127,0,4);
VL_SIGW(__Vtemp792,127,0,4);
VL_SIGW(__Vtemp793,127,0,4);
VL_SIGW(__Vtemp794,127,0,4);
VL_SIGW(__Vtemp795,127,0,4);
VL_SIGW(__Vtemp796,127,0,4);
VL_SIGW(__Vtemp797,127,0,4);
VL_SIGW(__Vtemp798,127,0,4);
VL_SIGW(__Vtemp799,127,0,4);
VL_SIGW(__Vtemp800,127,0,4);
VL_SIGW(__Vtemp801,127,0,4);
VL_SIGW(__Vtemp802,127,0,4);
VL_SIGW(__Vtemp803,127,0,4);
VL_SIGW(__Vtemp804,127,0,4);
VL_SIGW(__Vtemp805,127,0,4);
VL_SIGW(__Vtemp806,127,0,4);
VL_SIGW(__Vtemp807,127,0,4);
VL_SIGW(__Vtemp808,127,0,4);
VL_SIGW(__Vtemp809,127,0,4);
VL_SIGW(__Vtemp810,127,0,4);
VL_SIGW(__Vtemp811,127,0,4);
VL_SIGW(__Vtemp812,127,0,4);
VL_SIGW(__Vtemp813,127,0,4);
VL_SIGW(__Vtemp814,127,0,4);
VL_SIGW(__Vtemp815,127,0,4);
VL_SIGW(__Vtemp816,127,0,4);
VL_SIGW(__Vtemp817,127,0,4);
VL_SIGW(__Vtemp818,127,0,4);
VL_SIGW(__Vtemp819,127,0,4);
VL_SIGW(__Vtemp820,127,0,4);
VL_SIGW(__Vtemp821,127,0,4);
VL_SIGW(__Vtemp822,127,0,4);
VL_SIGW(__Vtemp823,127,0,4);
VL_SIGW(__Vtemp824,127,0,4);
VL_SIGW(__Vtemp825,127,0,4);
VL_SIGW(__Vtemp826,127,0,4);
VL_SIGW(__Vtemp827,127,0,4);
VL_SIGW(__Vtemp828,127,0,4);
VL_SIGW(__Vtemp829,127,0,4);
VL_SIGW(__Vtemp830,127,0,4);
VL_SIGW(__Vtemp831,127,0,4);
VL_SIGW(__Vtemp832,127,0,4);
VL_SIGW(__Vtemp833,127,0,4);
VL_SIGW(__Vtemp834,127,0,4);
VL_SIGW(__Vtemp835,127,0,4);
VL_SIGW(__Vtemp836,127,0,4);
VL_SIGW(__Vtemp837,127,0,4);
VL_SIGW(__Vtemp838,127,0,4);
VL_SIGW(__Vtemp839,127,0,4);
VL_SIGW(__Vtemp840,127,0,4);
VL_SIGW(__Vtemp841,127,0,4);
VL_SIGW(__Vtemp842,127,0,4);
VL_SIGW(__Vtemp843,127,0,4);
VL_SIGW(__Vtemp844,127,0,4);
VL_SIGW(__Vtemp845,127,0,4);
VL_SIGW(__Vtemp846,127,0,4);
VL_SIGW(__Vtemp847,127,0,4);
VL_SIGW(__Vtemp848,127,0,4);
VL_SIGW(__Vtemp849,127,0,4);
VL_SIGW(__Vtemp850,127,0,4);
VL_SIGW(__Vtemp851,127,0,4);
VL_SIGW(__Vtemp852,127,0,4);
VL_SIGW(__Vtemp853,127,0,4);
VL_SIGW(__Vtemp854,127,0,4);
VL_SIGW(__Vtemp855,127,0,4);
VL_SIGW(__Vtemp856,127,0,4);
VL_SIGW(__Vtemp857,127,0,4);
VL_SIGW(__Vtemp858,127,0,4);
VL_SIGW(__Vtemp859,127,0,4);
VL_SIGW(__Vtemp860,127,0,4);
VL_SIGW(__Vtemp861,127,0,4);
VL_SIGW(__Vtemp862,127,0,4);
VL_SIGW(__Vtemp863,127,0,4);
VL_SIGW(__Vtemp864,127,0,4);
VL_SIGW(__Vtemp865,127,0,4);
VL_SIGW(__Vtemp866,127,0,4);
VL_SIGW(__Vtemp867,127,0,4);
VL_SIGW(__Vtemp868,127,0,4);
VL_SIGW(__Vtemp869,127,0,4);
VL_SIGW(__Vtemp870,127,0,4);
VL_SIGW(__Vtemp871,127,0,4);
VL_SIGW(__Vtemp872,127,0,4);
VL_SIGW(__Vtemp873,127,0,4);
VL_SIGW(__Vtemp874,127,0,4);
VL_SIGW(__Vtemp875,127,0,4);
VL_SIGW(__Vtemp876,127,0,4);
VL_SIGW(__Vtemp877,127,0,4);
VL_SIGW(__Vtemp878,127,0,4);
VL_SIGW(__Vtemp879,127,0,4);
VL_SIGW(__Vtemp880,127,0,4);
VL_SIGW(__Vtemp881,127,0,4);
VL_SIGW(__Vtemp882,127,0,4);
VL_SIGW(__Vtemp883,127,0,4);
VL_SIGW(__Vtemp884,127,0,4);
VL_SIGW(__Vtemp885,127,0,4);
VL_SIGW(__Vtemp886,127,0,4);
VL_SIGW(__Vtemp887,127,0,4);
VL_SIGW(__Vtemp888,127,0,4);
VL_SIGW(__Vtemp889,127,0,4);
VL_SIGW(__Vtemp890,127,0,4);
VL_SIGW(__Vtemp891,127,0,4);
VL_SIGW(__Vtemp892,127,0,4);
VL_SIGW(__Vtemp893,127,0,4);
VL_SIGW(__Vtemp894,127,0,4);
VL_SIGW(__Vtemp895,127,0,4);
VL_SIGW(__Vtemp896,127,0,4);
VL_SIGW(__Vtemp897,127,0,4);
VL_SIGW(__Vtemp898,127,0,4);
VL_SIGW(__Vtemp899,127,0,4);
VL_SIGW(__Vtemp900,127,0,4);
VL_SIGW(__Vtemp901,127,0,4);
VL_SIGW(__Vtemp902,127,0,4);
VL_SIGW(__Vtemp903,127,0,4);
VL_SIGW(__Vtemp904,127,0,4);
VL_SIGW(__Vtemp905,127,0,4);
VL_SIGW(__Vtemp906,127,0,4);
VL_SIGW(__Vtemp907,127,0,4);
VL_SIGW(__Vtemp908,127,0,4);
VL_SIGW(__Vtemp909,127,0,4);
VL_SIGW(__Vtemp910,127,0,4);
VL_SIGW(__Vtemp911,127,0,4);
VL_SIGW(__Vtemp912,127,0,4);
VL_SIGW(__Vtemp913,127,0,4);
VL_SIGW(__Vtemp914,127,0,4);
VL_SIGW(__Vtemp915,127,0,4);
VL_SIGW(__Vtemp916,127,0,4);
VL_SIGW(__Vtemp917,127,0,4);
VL_SIGW(__Vtemp918,127,0,4);
VL_SIGW(__Vtemp919,127,0,4);
VL_SIGW(__Vtemp920,127,0,4);
VL_SIGW(__Vtemp921,127,0,4);
VL_SIGW(__Vtemp922,127,0,4);
VL_SIGW(__Vtemp923,127,0,4);
VL_SIGW(__Vtemp924,127,0,4);
VL_SIGW(__Vtemp925,127,0,4);
VL_SIGW(__Vtemp926,127,0,4);
VL_SIGW(__Vtemp927,127,0,4);
VL_SIGW(__Vtemp928,127,0,4);
VL_SIGW(__Vtemp929,127,0,4);
VL_SIGW(__Vtemp930,127,0,4);
VL_SIGW(__Vtemp931,127,0,4);
VL_SIGW(__Vtemp932,127,0,4);
VL_SIGW(__Vtemp933,127,0,4);
VL_SIGW(__Vtemp934,127,0,4);
VL_SIGW(__Vtemp935,127,0,4);
VL_SIGW(__Vtemp936,127,0,4);
VL_SIGW(__Vtemp937,127,0,4);
VL_SIGW(__Vtemp938,127,0,4);
VL_SIGW(__Vtemp939,127,0,4);
VL_SIGW(__Vtemp940,127,0,4);
VL_SIGW(__Vtemp941,127,0,4);
VL_SIGW(__Vtemp942,127,0,4);
VL_SIGW(__Vtemp943,127,0,4);
VL_SIGW(__Vtemp944,127,0,4);
VL_SIGW(__Vtemp945,127,0,4);
VL_SIGW(__Vtemp946,127,0,4);
VL_SIGW(__Vtemp947,127,0,4);
VL_SIGW(__Vtemp948,127,0,4);
VL_SIGW(__Vtemp949,127,0,4);
VL_SIGW(__Vtemp950,127,0,4);
VL_SIGW(__Vtemp951,127,0,4);
VL_SIGW(__Vtemp952,127,0,4);
VL_SIGW(__Vtemp953,127,0,4);
VL_SIGW(__Vtemp954,127,0,4);
VL_SIGW(__Vtemp955,127,0,4);
VL_SIGW(__Vtemp956,127,0,4);
VL_SIGW(__Vtemp957,127,0,4);
VL_SIGW(__Vtemp958,127,0,4);
VL_SIGW(__Vtemp959,127,0,4);
VL_SIGW(__Vtemp960,127,0,4);
VL_SIGW(__Vtemp961,127,0,4);
VL_SIGW(__Vtemp962,127,0,4);
VL_SIGW(__Vtemp963,127,0,4);
VL_SIGW(__Vtemp964,127,0,4);
VL_SIGW(__Vtemp965,127,0,4);
VL_SIGW(__Vtemp966,127,0,4);
VL_SIGW(__Vtemp967,127,0,4);
VL_SIGW(__Vtemp968,127,0,4);
VL_SIGW(__Vtemp969,127,0,4);
VL_SIGW(__Vtemp970,127,0,4);
VL_SIGW(__Vtemp971,127,0,4);
VL_SIGW(__Vtemp972,127,0,4);
VL_SIGW(__Vtemp973,127,0,4);
VL_SIGW(__Vtemp974,127,0,4);
VL_SIGW(__Vtemp975,127,0,4);
VL_SIGW(__Vtemp976,127,0,4);
VL_SIGW(__Vtemp977,127,0,4);
VL_SIGW(__Vtemp978,127,0,4);
VL_SIGW(__Vtemp979,127,0,4);
VL_SIGW(__Vtemp980,127,0,4);
VL_SIGW(__Vtemp981,127,0,4);
VL_SIGW(__Vtemp982,127,0,4);
VL_SIGW(__Vtemp983,127,0,4);
VL_SIGW(__Vtemp984,127,0,4);
VL_SIGW(__Vtemp985,127,0,4);
VL_SIGW(__Vtemp986,127,0,4);
VL_SIGW(__Vtemp987,127,0,4);
VL_SIGW(__Vtemp988,127,0,4);
VL_SIGW(__Vtemp989,127,0,4);
VL_SIGW(__Vtemp990,127,0,4);
VL_SIGW(__Vtemp991,127,0,4);
VL_SIGW(__Vtemp992,127,0,4);
VL_SIGW(__Vtemp993,127,0,4);
VL_SIGW(__Vtemp994,127,0,4);
VL_SIGW(__Vtemp995,127,0,4);
VL_SIGW(__Vtemp996,127,0,4);
VL_SIGW(__Vtemp997,127,0,4);
VL_SIGW(__Vtemp998,127,0,4);
VL_SIGW(__Vtemp999,127,0,4);
VL_SIGW(__Vtemp1000,127,0,4);
VL_SIGW(__Vtemp1001,127,0,4);
VL_SIGW(__Vtemp1002,127,0,4);
VL_SIGW(__Vtemp1003,127,0,4);
VL_SIGW(__Vtemp1004,127,0,4);
VL_SIGW(__Vtemp1005,127,0,4);
VL_SIGW(__Vtemp1006,127,0,4);
VL_SIGW(__Vtemp1007,127,0,4);
VL_SIGW(__Vtemp1008,127,0,4);
VL_SIGW(__Vtemp1009,127,0,4);
VL_SIGW(__Vtemp1010,127,0,4);
VL_SIGW(__Vtemp1011,127,0,4);
VL_SIGW(__Vtemp1012,127,0,4);
VL_SIGW(__Vtemp1013,127,0,4);
VL_SIGW(__Vtemp1014,127,0,4);
VL_SIGW(__Vtemp1015,127,0,4);
VL_SIGW(__Vtemp1016,127,0,4);
VL_SIGW(__Vtemp1017,127,0,4);
VL_SIGW(__Vtemp1018,127,0,4);
VL_SIGW(__Vtemp1019,127,0,4);
VL_SIGW(__Vtemp1020,127,0,4);
VL_SIGW(__Vtemp1021,127,0,4);
VL_SIGW(__Vtemp1022,127,0,4);
VL_SIGW(__Vtemp1023,127,0,4);
VL_SIGW(__Vtemp1024,127,0,4);
VL_SIGW(__Vtemp1025,127,0,4);
VL_SIGW(__Vtemp1026,127,0,4);
VL_SIGW(__Vtemp1027,127,0,4);
VL_SIGW(__Vtemp1028,127,0,4);
VL_SIGW(__Vtemp1029,127,0,4);
VL_SIGW(__Vtemp1030,127,0,4);
VL_SIGW(__Vtemp1031,127,0,4);
VL_SIGW(__Vtemp1032,127,0,4);
VL_SIGW(__Vtemp1033,127,0,4);
VL_SIGW(__Vtemp1034,127,0,4);
VL_SIGW(__Vtemp1035,127,0,4);
VL_SIGW(__Vtemp1036,127,0,4);
VL_SIGW(__Vtemp1037,127,0,4);
VL_SIGW(__Vtemp1038,127,0,4);
VL_SIGW(__Vtemp1039,127,0,4);
VL_SIGW(__Vtemp1040,127,0,4);
VL_SIGW(__Vtemp1041,127,0,4);
VL_SIGW(__Vtemp1042,127,0,4);
VL_SIGW(__Vtemp1043,127,0,4);
VL_SIGW(__Vtemp1044,127,0,4);
VL_SIGW(__Vtemp1045,127,0,4);
VL_SIGW(__Vtemp1046,127,0,4);
VL_SIGW(__Vtemp1047,127,0,4);
VL_SIGW(__Vtemp1048,127,0,4);
VL_SIGW(__Vtemp1049,127,0,4);
VL_SIGW(__Vtemp1050,127,0,4);
VL_SIGW(__Vtemp1051,127,0,4);
VL_SIGW(__Vtemp1052,127,0,4);
VL_SIGW(__Vtemp1053,127,0,4);
VL_SIGW(__Vtemp1054,127,0,4);
VL_SIGW(__Vtemp1055,127,0,4);
VL_SIGW(__Vtemp1056,127,0,4);
VL_SIGW(__Vtemp1057,127,0,4);
VL_SIGW(__Vtemp1058,127,0,4);
VL_SIGW(__Vtemp1059,127,0,4);
VL_SIGW(__Vtemp1060,127,0,4);
VL_SIGW(__Vtemp1061,127,0,4);
VL_SIGW(__Vtemp1062,127,0,4);
VL_SIGW(__Vtemp1063,127,0,4);
VL_SIGW(__Vtemp1064,127,0,4);
VL_SIGW(__Vtemp1065,127,0,4);
VL_SIGW(__Vtemp1066,127,0,4);
VL_SIGW(__Vtemp1067,127,0,4);
VL_SIGW(__Vtemp1068,127,0,4);
VL_SIGW(__Vtemp1069,127,0,4);
VL_SIGW(__Vtemp1070,127,0,4);
VL_SIGW(__Vtemp1071,127,0,4);
VL_SIGW(__Vtemp1072,127,0,4);
VL_SIGW(__Vtemp1073,127,0,4);
VL_SIGW(__Vtemp1074,127,0,4);
VL_SIGW(__Vtemp1075,127,0,4);
VL_SIGW(__Vtemp1076,127,0,4);
VL_SIGW(__Vtemp1077,127,0,4);
VL_SIGW(__Vtemp1078,127,0,4);
VL_SIGW(__Vtemp1079,127,0,4);
VL_SIGW(__Vtemp1080,127,0,4);
VL_SIGW(__Vtemp1081,127,0,4);
VL_SIGW(__Vtemp1082,127,0,4);
VL_SIGW(__Vtemp1083,127,0,4);
VL_SIGW(__Vtemp1084,127,0,4);
VL_SIGW(__Vtemp1085,127,0,4);
VL_SIGW(__Vtemp1086,127,0,4);
VL_SIGW(__Vtemp1087,127,0,4);
VL_SIGW(__Vtemp1088,127,0,4);
VL_SIGW(__Vtemp1089,127,0,4);
VL_SIGW(__Vtemp1090,127,0,4);
VL_SIGW(__Vtemp1091,127,0,4);
VL_SIGW(__Vtemp1092,127,0,4);
VL_SIGW(__Vtemp1093,127,0,4);
VL_SIGW(__Vtemp1094,127,0,4);
VL_SIGW(__Vtemp1095,127,0,4);
VL_SIGW(__Vtemp1096,127,0,4);
VL_SIGW(__Vtemp1097,127,0,4);
VL_SIGW(__Vtemp1098,127,0,4);
VL_SIGW(__Vtemp1099,127,0,4);
VL_SIGW(__Vtemp1100,127,0,4);
VL_SIGW(__Vtemp1101,127,0,4);
VL_SIGW(__Vtemp1102,127,0,4);
VL_SIGW(__Vtemp1103,127,0,4);
VL_SIGW(__Vtemp1104,127,0,4);
VL_SIGW(__Vtemp1105,127,0,4);
VL_SIGW(__Vtemp1106,127,0,4);
VL_SIGW(__Vtemp1107,127,0,4);
VL_SIGW(__Vtemp1108,127,0,4);
VL_SIGW(__Vtemp1109,127,0,4);
VL_SIGW(__Vtemp1110,127,0,4);
VL_SIGW(__Vtemp1111,127,0,4);
VL_SIGW(__Vtemp1112,127,0,4);
VL_SIGW(__Vtemp1113,127,0,4);
VL_SIGW(__Vtemp1114,127,0,4);
VL_SIGW(__Vtemp1115,127,0,4);
VL_SIGW(__Vtemp1116,127,0,4);
VL_SIGW(__Vtemp1117,127,0,4);
VL_SIGW(__Vtemp1118,127,0,4);
VL_SIGW(__Vtemp1119,127,0,4);
VL_SIGW(__Vtemp1120,127,0,4);
VL_SIGW(__Vtemp1121,127,0,4);
VL_SIGW(__Vtemp1122,127,0,4);
VL_SIGW(__Vtemp1123,127,0,4);
VL_SIGW(__Vtemp1124,127,0,4);
VL_SIGW(__Vtemp1125,127,0,4);
VL_SIGW(__Vtemp1126,127,0,4);
VL_SIGW(__Vtemp1127,127,0,4);
VL_SIGW(__Vtemp1128,127,0,4);
VL_SIGW(__Vtemp1129,127,0,4);
VL_SIGW(__Vtemp1130,127,0,4);
VL_SIGW(__Vtemp1131,127,0,4);
VL_SIGW(__Vtemp1132,127,0,4);
VL_SIGW(__Vtemp1133,127,0,4);
VL_SIGW(__Vtemp1134,127,0,4);
VL_SIGW(__Vtemp1135,127,0,4);
VL_SIGW(__Vtemp1136,127,0,4);
VL_SIGW(__Vtemp1137,127,0,4);
VL_SIGW(__Vtemp1138,127,0,4);
VL_SIGW(__Vtemp1139,127,0,4);
VL_SIGW(__Vtemp1140,127,0,4);
VL_SIGW(__Vtemp1141,127,0,4);
VL_SIGW(__Vtemp1142,127,0,4);
VL_SIGW(__Vtemp1143,127,0,4);
VL_SIGW(__Vtemp1144,127,0,4);
VL_SIGW(__Vtemp1145,127,0,4);
VL_SIGW(__Vtemp1146,127,0,4);
VL_SIGW(__Vtemp1147,127,0,4);
VL_SIGW(__Vtemp1148,127,0,4);
VL_SIGW(__Vtemp1149,127,0,4);
VL_SIGW(__Vtemp1150,127,0,4);
VL_SIGW(__Vtemp1151,127,0,4);
VL_SIGW(__Vtemp1152,127,0,4);
VL_SIGW(__Vtemp1153,127,0,4);
VL_SIGW(__Vtemp1154,127,0,4);
VL_SIGW(__Vtemp1155,127,0,4);
VL_SIGW(__Vtemp1156,127,0,4);
VL_SIGW(__Vtemp1157,127,0,4);
VL_SIGW(__Vtemp1158,127,0,4);
VL_SIGW(__Vtemp1159,127,0,4);
VL_SIGW(__Vtemp1160,127,0,4);
VL_SIGW(__Vtemp1161,127,0,4);
VL_SIGW(__Vtemp1162,127,0,4);
VL_SIGW(__Vtemp1163,127,0,4);
VL_SIGW(__Vtemp1164,127,0,4);
VL_SIGW(__Vtemp1165,127,0,4);
VL_SIGW(__Vtemp1166,127,0,4);
VL_SIGW(__Vtemp1167,127,0,4);
VL_SIGW(__Vtemp1168,127,0,4);
VL_SIGW(__Vtemp1169,127,0,4);
VL_SIGW(__Vtemp1170,127,0,4);
VL_SIGW(__Vtemp1171,127,0,4);
VL_SIGW(__Vtemp1172,127,0,4);
VL_SIGW(__Vtemp1173,127,0,4);
VL_SIGW(__Vtemp1174,127,0,4);
VL_SIGW(__Vtemp1175,127,0,4);
VL_SIGW(__Vtemp1176,127,0,4);
VL_SIGW(__Vtemp1177,127,0,4);
VL_SIGW(__Vtemp1178,127,0,4);
VL_SIGW(__Vtemp1179,127,0,4);
VL_SIGW(__Vtemp1180,127,0,4);
VL_SIGW(__Vtemp1181,127,0,4);
VL_SIGW(__Vtemp1182,127,0,4);
VL_SIGW(__Vtemp1183,127,0,4);
VL_SIGW(__Vtemp1184,127,0,4);
VL_SIGW(__Vtemp1185,127,0,4);
VL_SIGW(__Vtemp1186,127,0,4);
VL_SIGW(__Vtemp1187,127,0,4);
VL_SIGW(__Vtemp1188,127,0,4);
VL_SIGW(__Vtemp1189,127,0,4);
VL_SIGW(__Vtemp1190,127,0,4);
VL_SIGW(__Vtemp1191,127,0,4);
VL_SIGW(__Vtemp1192,127,0,4);
VL_SIGW(__Vtemp1193,127,0,4);
VL_SIGW(__Vtemp1194,127,0,4);
VL_SIGW(__Vtemp1195,127,0,4);
VL_SIGW(__Vtemp1196,127,0,4);
VL_SIGW(__Vtemp1197,127,0,4);
VL_SIGW(__Vtemp1198,127,0,4);
VL_SIGW(__Vtemp1199,127,0,4);
VL_SIGW(__Vtemp1200,127,0,4);
VL_SIGW(__Vtemp1201,127,0,4);
VL_SIGW(__Vtemp1202,127,0,4);
VL_SIGW(__Vtemp1203,127,0,4);
VL_SIGW(__Vtemp1204,127,0,4);
VL_SIGW(__Vtemp1205,127,0,4);
VL_SIGW(__Vtemp1206,127,0,4);
VL_SIGW(__Vtemp1207,127,0,4);
VL_SIGW(__Vtemp1208,127,0,4);
VL_SIGW(__Vtemp1209,127,0,4);
VL_SIGW(__Vtemp1210,127,0,4);
VL_SIGW(__Vtemp1211,127,0,4);
VL_SIGW(__Vtemp1212,127,0,4);
VL_SIGW(__Vtemp1213,127,0,4);
VL_SIGW(__Vtemp1214,127,0,4);
VL_SIGW(__Vtemp1215,127,0,4);
VL_SIGW(__Vtemp1216,127,0,4);
VL_SIGW(__Vtemp1217,127,0,4);
VL_SIGW(__Vtemp1218,127,0,4);
VL_SIGW(__Vtemp1219,127,0,4);
VL_SIGW(__Vtemp1220,127,0,4);
VL_SIGW(__Vtemp1221,127,0,4);
VL_SIGW(__Vtemp1222,127,0,4);
VL_SIGW(__Vtemp1223,127,0,4);
VL_SIGW(__Vtemp1224,127,0,4);
VL_SIGW(__Vtemp1225,127,0,4);
VL_SIGW(__Vtemp1226,127,0,4);
VL_SIGW(__Vtemp1227,127,0,4);
VL_SIGW(__Vtemp1228,127,0,4);
VL_SIGW(__Vtemp1229,127,0,4);
VL_SIGW(__Vtemp1230,127,0,4);
VL_SIGW(__Vtemp1231,127,0,4);
VL_SIGW(__Vtemp1232,127,0,4);
VL_SIGW(__Vtemp1233,127,0,4);
VL_SIGW(__Vtemp1234,127,0,4);
VL_SIGW(__Vtemp1235,127,0,4);
VL_SIGW(__Vtemp1236,127,0,4);
VL_SIGW(__Vtemp1237,127,0,4);
VL_SIGW(__Vtemp1238,127,0,4);
VL_SIGW(__Vtemp1239,127,0,4);
VL_SIGW(__Vtemp1240,127,0,4);
VL_SIGW(__Vtemp1241,127,0,4);
VL_SIGW(__Vtemp1242,127,0,4);
VL_SIGW(__Vtemp1243,127,0,4);
VL_SIGW(__Vtemp1244,127,0,4);
VL_SIGW(__Vtemp1245,127,0,4);
VL_SIGW(__Vtemp1246,127,0,4);
VL_SIGW(__Vtemp1247,127,0,4);
VL_SIGW(__Vtemp1248,127,0,4);
VL_SIGW(__Vtemp1249,127,0,4);
VL_SIGW(__Vtemp1250,127,0,4);
VL_SIGW(__Vtemp1251,127,0,4);
VL_SIGW(__Vtemp1252,127,0,4);
VL_SIGW(__Vtemp1253,127,0,4);
VL_SIGW(__Vtemp1254,127,0,4);
VL_SIGW(__Vtemp1255,127,0,4);
VL_SIGW(__Vtemp1256,127,0,4);
VL_SIGW(__Vtemp1257,127,0,4);
VL_SIGW(__Vtemp1258,127,0,4);
VL_SIGW(__Vtemp1259,127,0,4);
VL_SIGW(__Vtemp1260,127,0,4);
VL_SIGW(__Vtemp1261,127,0,4);
VL_SIGW(__Vtemp1262,127,0,4);
VL_SIGW(__Vtemp1263,127,0,4);
VL_SIGW(__Vtemp1264,127,0,4);
VL_SIGW(__Vtemp1265,127,0,4);
VL_SIGW(__Vtemp1266,127,0,4);
VL_SIGW(__Vtemp1267,127,0,4);
VL_SIGW(__Vtemp1268,127,0,4);
VL_SIGW(__Vtemp1269,127,0,4);
VL_SIGW(__Vtemp1270,127,0,4);
VL_SIGW(__Vtemp1271,127,0,4);
VL_SIGW(__Vtemp1272,127,0,4);
VL_SIGW(__Vtemp1273,127,0,4);
VL_SIGW(__Vtemp1274,127,0,4);
VL_SIGW(__Vtemp1275,127,0,4);
VL_SIGW(__Vtemp1276,127,0,4);
VL_SIGW(__Vtemp1277,127,0,4);
VL_SIGW(__Vtemp1278,127,0,4);
VL_SIGW(__Vtemp1279,127,0,4);
// Body
{
vcdp->chgBit (c+1163,(vlTOPp->cache_simX__DOT__icache_i_m_ready));
vcdp->chgBit (c+1164,(vlTOPp->cache_simX__DOT__dcache_i_m_ready));
vcdp->chgBus (c+1165,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests),4);
vcdp->chgBit (c+1166,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))));
vcdp->chgBus (c+1167,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
vcdp->chgBus (c+1168,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
vcdp->chgBus (c+1169,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
vcdp->chgBus (c+1170,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
vcdp->chgBus (c+1171,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr)),32);
vcdp->chgBit (c+1172,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))));
vcdp->chgArray(c+1173,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read),128);
vcdp->chgBus (c+1177,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict),1);
vcdp->chgBus (c+1178,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state),4);
vcdp->chgBus (c+1179,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid),4);
vcdp->chgBus (c+1180,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr),32);
vcdp->chgBus (c+1181,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr)),32);
vcdp->chgBit (c+1182,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))));
vcdp->chgBus (c+1183,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read),32);
vcdp->chgBus (c+1184,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict),1);
vcdp->chgBus (c+1185,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state),4);
vcdp->chgBus (c+1186,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid),1);
vcdp->chgBus (c+1187,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr),32);
__Vtemp768[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[0U][0U];
__Vtemp768[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[0U][1U];
__Vtemp768[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[0U][2U];
__Vtemp768[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[0U][3U];
vcdp->chgArray(c+1188,(__Vtemp768),128);
__Vtemp769[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[1U][0U];
__Vtemp769[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[1U][1U];
__Vtemp769[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[1U][2U];
__Vtemp769[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[1U][3U];
vcdp->chgArray(c+1192,(__Vtemp769),128);
__Vtemp770[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[2U][0U];
__Vtemp770[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[2U][1U];
__Vtemp770[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[2U][2U];
__Vtemp770[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[2U][3U];
vcdp->chgArray(c+1196,(__Vtemp770),128);
__Vtemp771[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[3U][0U];
__Vtemp771[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[3U][1U];
__Vtemp771[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[3U][2U];
__Vtemp771[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[3U][3U];
vcdp->chgArray(c+1200,(__Vtemp771),128);
__Vtemp772[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[4U][0U];
__Vtemp772[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[4U][1U];
__Vtemp772[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[4U][2U];
__Vtemp772[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[4U][3U];
vcdp->chgArray(c+1204,(__Vtemp772),128);
__Vtemp773[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[5U][0U];
__Vtemp773[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[5U][1U];
__Vtemp773[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[5U][2U];
__Vtemp773[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[5U][3U];
vcdp->chgArray(c+1208,(__Vtemp773),128);
__Vtemp774[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[6U][0U];
__Vtemp774[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[6U][1U];
__Vtemp774[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[6U][2U];
__Vtemp774[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[6U][3U];
vcdp->chgArray(c+1212,(__Vtemp774),128);
__Vtemp775[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[7U][0U];
__Vtemp775[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[7U][1U];
__Vtemp775[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[7U][2U];
__Vtemp775[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[7U][3U];
vcdp->chgArray(c+1216,(__Vtemp775),128);
__Vtemp776[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[8U][0U];
__Vtemp776[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[8U][1U];
__Vtemp776[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[8U][2U];
__Vtemp776[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[8U][3U];
vcdp->chgArray(c+1220,(__Vtemp776),128);
__Vtemp777[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[9U][0U];
__Vtemp777[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
[9U][1U];
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vcdp->chgBit (c+1379,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[31]));
vcdp->chgBit (c+1380,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0]));
vcdp->chgBit (c+1381,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[1]));
vcdp->chgBit (c+1382,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[2]));
vcdp->chgBit (c+1383,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[3]));
vcdp->chgBit (c+1384,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[4]));
vcdp->chgBit (c+1385,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[5]));
vcdp->chgBit (c+1386,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[6]));
vcdp->chgBit (c+1387,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[7]));
vcdp->chgBit (c+1388,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[8]));
vcdp->chgBit (c+1389,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[9]));
vcdp->chgBit (c+1390,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[10]));
vcdp->chgBit (c+1391,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[11]));
vcdp->chgBit (c+1392,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[12]));
vcdp->chgBit (c+1393,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[13]));
vcdp->chgBit (c+1394,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[14]));
vcdp->chgBit (c+1395,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[15]));
vcdp->chgBit (c+1396,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[16]));
vcdp->chgBit (c+1397,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[17]));
vcdp->chgBit (c+1398,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[18]));
vcdp->chgBit (c+1399,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[19]));
vcdp->chgBit (c+1400,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[20]));
vcdp->chgBit (c+1401,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[21]));
vcdp->chgBit (c+1402,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[22]));
vcdp->chgBit (c+1403,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[23]));
vcdp->chgBit (c+1404,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[24]));
vcdp->chgBit (c+1405,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[25]));
vcdp->chgBit (c+1406,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[26]));
vcdp->chgBit (c+1407,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[27]));
vcdp->chgBit (c+1408,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[28]));
vcdp->chgBit (c+1409,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[29]));
vcdp->chgBit (c+1410,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[30]));
vcdp->chgBit (c+1411,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[31]));
vcdp->chgBus (c+1412,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f),32);
vcdp->chgBus (c+1413,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind),32);
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vcdp->chgArray(c+1414,(__Vtemp800),128);
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vcdp->chgArray(c+1418,(__Vtemp801),128);
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vcdp->chgArray(c+1422,(__Vtemp802),128);
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vcdp->chgArray(c+1426,(__Vtemp803),128);
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vcdp->chgArray(c+1430,(__Vtemp804),128);
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vcdp->chgArray(c+1434,(__Vtemp805),128);
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vcdp->chgArray(c+1438,(__Vtemp806),128);
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vcdp->chgArray(c+1442,(__Vtemp807),128);
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vcdp->chgArray(c+1446,(__Vtemp808),128);
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vcdp->chgArray(c+1450,(__Vtemp809),128);
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vcdp->chgBit (c+1616,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[10]));
vcdp->chgBit (c+1617,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[11]));
vcdp->chgBit (c+1618,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[12]));
vcdp->chgBit (c+1619,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[13]));
vcdp->chgBit (c+1620,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[14]));
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vcdp->chgBit (c+1622,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[16]));
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vcdp->chgBit (c+1624,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[18]));
vcdp->chgBit (c+1625,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[19]));
vcdp->chgBit (c+1626,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[20]));
vcdp->chgBit (c+1627,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[21]));
vcdp->chgBit (c+1628,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[22]));
vcdp->chgBit (c+1629,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[23]));
vcdp->chgBit (c+1630,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[24]));
vcdp->chgBit (c+1631,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[25]));
vcdp->chgBit (c+1632,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[26]));
vcdp->chgBit (c+1633,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[27]));
vcdp->chgBit (c+1634,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[28]));
vcdp->chgBit (c+1635,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[29]));
vcdp->chgBit (c+1636,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[30]));
vcdp->chgBit (c+1637,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[31]));
vcdp->chgBus (c+1638,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f),32);
vcdp->chgBus (c+1639,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind),32);
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vcdp->chgArray(c+1640,(__Vtemp832),128);
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vcdp->chgArray(c+1644,(__Vtemp833),128);
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vcdp->chgArray(c+1652,(__Vtemp835),128);
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vcdp->chgArray(c+1756,(__Vtemp861),128);
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vcdp->chgArray(c+1760,(__Vtemp862),128);
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vcdp->chgBit (c+1863,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[31]));
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vcdp->chgArray(c+1986,(__Vtemp894),128);
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vcdp->chgBit (c+2315,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[31]));
vcdp->chgBus (c+2316,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f),32);
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vcdp->chgBit (c+2753,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[17]));
vcdp->chgBit (c+2754,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[18]));
vcdp->chgBit (c+2755,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[19]));
vcdp->chgBit (c+2756,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[20]));
vcdp->chgBit (c+2757,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[21]));
vcdp->chgBit (c+2758,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[22]));
vcdp->chgBit (c+2759,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[23]));
vcdp->chgBit (c+2760,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[24]));
vcdp->chgBit (c+2761,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[25]));
vcdp->chgBit (c+2762,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[26]));
vcdp->chgBit (c+2763,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[27]));
vcdp->chgBit (c+2764,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[28]));
vcdp->chgBit (c+2765,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[29]));
vcdp->chgBit (c+2766,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[30]));
vcdp->chgBit (c+2767,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[31]));
vcdp->chgBus (c+2768,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f),32);
vcdp->chgBus (c+2769,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind),32);
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vcdp->chgArray(c+3512,(__Vtemp1104),128);
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vcdp->chgArray(c+3544,(__Vtemp1112),128);
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vcdp->chgBus (c+3577,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[1]),21);
vcdp->chgBus (c+3578,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[2]),21);
vcdp->chgBus (c+3579,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[3]),21);
vcdp->chgBus (c+3580,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[4]),21);
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vcdp->chgArray(c+4190,(__Vtemp1200),128);
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vcdp->chgArray(c+4194,(__Vtemp1201),128);
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vcdp->chgArray(c+4198,(__Vtemp1202),128);
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vcdp->chgArray(c+4202,(__Vtemp1203),128);
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vcdp->chgArray(c+4206,(__Vtemp1204),128);
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vcdp->chgArray(c+4210,(__Vtemp1205),128);
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vcdp->chgArray(c+4218,(__Vtemp1207),128);
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vcdp->chgArray(c+4222,(__Vtemp1208),128);
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vcdp->chgArray(c+4226,(__Vtemp1209),128);
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vcdp->chgArray(c+4230,(__Vtemp1210),128);
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vcdp->chgArray(c+4234,(__Vtemp1211),128);
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vcdp->chgArray(c+4238,(__Vtemp1212),128);
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vcdp->chgArray(c+4242,(__Vtemp1213),128);
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vcdp->chgArray(c+4246,(__Vtemp1214),128);
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vcdp->chgArray(c+4250,(__Vtemp1215),128);
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vcdp->chgBus (c+4255,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[1]),21);
vcdp->chgBus (c+4256,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[2]),21);
vcdp->chgBus (c+4257,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[3]),21);
vcdp->chgBus (c+4258,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[4]),21);
vcdp->chgBus (c+4259,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[5]),21);
vcdp->chgBus (c+4260,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[6]),21);
vcdp->chgBus (c+4261,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[7]),21);
vcdp->chgBus (c+4262,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[8]),21);
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vcdp->chgBit (c+4797,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[27]));
vcdp->chgBit (c+4798,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[28]));
vcdp->chgBit (c+4799,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[29]));
vcdp->chgBit (c+4800,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[30]));
vcdp->chgBit (c+4801,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[31]));
vcdp->chgBus (c+4802,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f),32);
vcdp->chgBus (c+4803,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind),32);
}
}
void Vcache_simX::traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
int c=code;
if (0 && vcdp && c) {} // Prevent unused
// Body
{
vcdp->chgBit (c+4804,(vlTOPp->clk));
vcdp->chgBit (c+4805,(vlTOPp->reset));
vcdp->chgBus (c+4806,(vlTOPp->in_icache_pc_addr),32);
vcdp->chgBit (c+4807,(vlTOPp->in_icache_valid_pc_addr));
vcdp->chgBit (c+4808,(vlTOPp->out_icache_stall));
vcdp->chgBus (c+4809,(vlTOPp->in_dcache_mem_read),3);
vcdp->chgBus (c+4810,(vlTOPp->in_dcache_mem_write),3);
vcdp->chgBit (c+4811,(vlTOPp->in_dcache_in_valid[0]));
vcdp->chgBit (c+4812,(vlTOPp->in_dcache_in_valid[1]));
vcdp->chgBit (c+4813,(vlTOPp->in_dcache_in_valid[2]));
vcdp->chgBit (c+4814,(vlTOPp->in_dcache_in_valid[3]));
vcdp->chgBus (c+4815,(vlTOPp->in_dcache_in_address[0]),32);
vcdp->chgBus (c+4816,(vlTOPp->in_dcache_in_address[1]),32);
vcdp->chgBus (c+4817,(vlTOPp->in_dcache_in_address[2]),32);
vcdp->chgBus (c+4818,(vlTOPp->in_dcache_in_address[3]),32);
vcdp->chgBit (c+4819,(vlTOPp->out_dcache_stall));
vcdp->chgBus (c+4820,(((IData)(vlTOPp->in_icache_valid_pc_addr)
? 2U : 7U)),3);
}
}
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