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267 lines
10 KiB
Verilog
267 lines
10 KiB
Verilog
`include "VX_define.vh"
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module VX_cluster #(
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parameter CLUSTER_ID = 0
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) (
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`SCOPE_IO_VX_cluster
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// Clock
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input wire clk,
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input wire reset,
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// Memory request
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output wire mem_req_valid,
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output wire mem_req_rw,
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output wire [`L2MEM_BYTEEN_WIDTH-1:0] mem_req_byteen,
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output wire [`L2MEM_ADDR_WIDTH-1:0] mem_req_addr,
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output wire [`L2MEM_LINE_WIDTH-1:0] mem_req_data,
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output wire [`L2MEM_TAG_WIDTH-1:0] mem_req_tag,
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input wire mem_req_ready,
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// Memory response
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input wire mem_rsp_valid,
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input wire [`L2MEM_LINE_WIDTH-1:0] mem_rsp_data,
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input wire [`L2MEM_TAG_WIDTH-1:0] mem_rsp_tag,
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output wire mem_rsp_ready,
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// CSR Request
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input wire csr_req_valid,
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input wire [`NC_BITS-1:0] csr_req_coreid,
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input wire [11:0] csr_req_addr,
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input wire csr_req_rw,
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input wire [31:0] csr_req_data,
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output wire csr_req_ready,
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// CSR Response
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output wire csr_rsp_valid,
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output wire [31:0] csr_rsp_data,
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input wire csr_rsp_ready,
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// Status
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output wire busy,
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output wire ebreak
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);
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wire [`NUM_CORES-1:0] per_core_mem_req_valid;
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wire [`NUM_CORES-1:0] per_core_mem_req_rw;
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wire [`NUM_CORES-1:0][`DMEM_BYTEEN_WIDTH-1:0] per_core_mem_req_byteen;
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wire [`NUM_CORES-1:0][`DMEM_ADDR_WIDTH-1:0] per_core_mem_req_addr;
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wire [`NUM_CORES-1:0][`DMEM_LINE_WIDTH-1:0] per_core_mem_req_data;
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wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_req_tag;
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wire [`NUM_CORES-1:0] per_core_mem_req_ready;
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wire [`NUM_CORES-1:0] per_core_mem_rsp_valid;
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wire [`NUM_CORES-1:0][`DMEM_LINE_WIDTH-1:0] per_core_mem_rsp_data;
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wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_rsp_tag;
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wire [`NUM_CORES-1:0] per_core_mem_rsp_ready;
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wire [`NUM_CORES-1:0] per_core_csr_req_valid;
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wire [`NUM_CORES-1:0][11:0] per_core_csr_req_addr;
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wire [`NUM_CORES-1:0] per_core_csr_req_rw;
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wire [`NUM_CORES-1:0][31:0] per_core_csr_req_data;
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wire [`NUM_CORES-1:0] per_core_csr_req_ready;
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wire [`NUM_CORES-1:0] per_core_csr_rsp_valid;
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wire [`NUM_CORES-1:0][31:0] per_core_csr_rsp_data;
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wire [`NUM_CORES-1:0] per_core_csr_rsp_ready;
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wire [`NUM_CORES-1:0] per_core_busy;
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wire [`NUM_CORES-1:0] per_core_ebreak;
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for (genvar i = 0; i < `NUM_CORES; i++) begin
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wire core_reset;
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VX_reset_relay #(
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.DEPTH (`NUM_CORES > 1)
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) reset_relay (
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.clk (clk),
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.reset (reset),
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.reset_o (core_reset)
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);
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VX_core #(
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.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
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) core (
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`SCOPE_BIND_VX_cluster_core(i)
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.clk (clk),
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.reset (core_reset),
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.mem_req_valid (per_core_mem_req_valid[i]),
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.mem_req_rw (per_core_mem_req_rw [i]),
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.mem_req_byteen (per_core_mem_req_byteen[i]),
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.mem_req_addr (per_core_mem_req_addr [i]),
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.mem_req_data (per_core_mem_req_data [i]),
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.mem_req_tag (per_core_mem_req_tag [i]),
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.mem_req_ready (per_core_mem_req_ready[i]),
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.mem_rsp_valid (per_core_mem_rsp_valid[i]),
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.mem_rsp_data (per_core_mem_rsp_data [i]),
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.mem_rsp_tag (per_core_mem_rsp_tag [i]),
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.mem_rsp_ready (per_core_mem_rsp_ready[i]),
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.csr_req_valid (per_core_csr_req_valid [i]),
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.csr_req_rw (per_core_csr_req_rw [i]),
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.csr_req_addr (per_core_csr_req_addr [i]),
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.csr_req_data (per_core_csr_req_data [i]),
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.csr_req_ready (per_core_csr_req_ready [i]),
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.csr_rsp_valid (per_core_csr_rsp_valid [i]),
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.csr_rsp_data (per_core_csr_rsp_data [i]),
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.csr_rsp_ready (per_core_csr_rsp_ready [i]),
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.busy (per_core_busy [i]),
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.ebreak (per_core_ebreak [i])
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);
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end
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VX_csr_arb #(
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.NUM_REQS (`NUM_CORES),
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.DATA_WIDTH (32),
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.ADDR_WIDTH (12),
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.BUFFERED_REQ (1),
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.BUFFERED_RSP (1)
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) csr_arb (
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.clk (clk),
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.reset (reset),
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.request_id (csr_req_coreid),
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// input requests
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.req_valid_in (csr_req_valid),
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.req_addr_in (csr_req_addr),
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.req_rw_in (csr_req_rw),
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.req_data_in (csr_req_data),
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.req_ready_in (csr_req_ready),
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// output request
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.req_valid_out (per_core_csr_req_valid),
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.req_addr_out (per_core_csr_req_addr),
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.req_rw_out (per_core_csr_req_rw),
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.req_data_out (per_core_csr_req_data),
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.req_ready_out (per_core_csr_req_ready),
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// input responses
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.rsp_valid_in (per_core_csr_rsp_valid),
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.rsp_data_in (per_core_csr_rsp_data),
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.rsp_ready_in (per_core_csr_rsp_ready),
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// output response
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.rsp_valid_out (csr_rsp_valid),
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.rsp_data_out (csr_rsp_data),
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.rsp_ready_out (csr_rsp_ready)
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);
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assign busy = (| per_core_busy);
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assign ebreak = (| per_core_ebreak);
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if (`L2_ENABLE) begin
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`ifdef PERF_ENABLE
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VX_perf_cache_if perf_l2cache_if();
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`endif
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VX_cache #(
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.CACHE_ID (`L2CACHE_ID),
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.CACHE_SIZE (`L2CACHE_SIZE),
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.CACHE_LINE_SIZE (`L2CACHE_LINE_SIZE),
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.NUM_BANKS (`L2NUM_BANKS),
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.WORD_SIZE (`L2WORD_SIZE),
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.NUM_REQS (`NUM_CORES),
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.CREQ_SIZE (`L2CREQ_SIZE),
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.MSHR_SIZE (`L2MSHR_SIZE),
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.MRSQ_SIZE (`L2MRSQ_SIZE),
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.MREQ_SIZE (`L2MREQ_SIZE),
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.WRITE_ENABLE (1),
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.CORE_TAG_WIDTH (`XMEM_TAG_WIDTH),
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.CORE_TAG_ID_BITS (0),
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.MEM_TAG_WIDTH (`L2MEM_TAG_WIDTH)
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) l2cache (
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`SCOPE_BIND_VX_cluster_l2cache
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.clk (clk),
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.reset (reset),
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.flush (1'b0),
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`ifdef PERF_ENABLE
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.perf_cache_if (perf_l2cache_if),
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`endif
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// Core request
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.core_req_valid (per_core_mem_req_valid),
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.core_req_rw (per_core_mem_req_rw),
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.core_req_byteen (per_core_mem_req_byteen),
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.core_req_addr (per_core_mem_req_addr),
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.core_req_data (per_core_mem_req_data),
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.core_req_tag (per_core_mem_req_tag),
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.core_req_ready (per_core_mem_req_ready),
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// Core response
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.core_rsp_valid (per_core_mem_rsp_valid),
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.core_rsp_data (per_core_mem_rsp_data),
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.core_rsp_tag (per_core_mem_rsp_tag),
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.core_rsp_ready (per_core_mem_rsp_ready),
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// Memory request
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.mem_req_valid (mem_req_valid),
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.mem_req_rw (mem_req_rw),
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.mem_req_byteen (mem_req_byteen),
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.mem_req_addr (mem_req_addr),
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.mem_req_data (mem_req_data),
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.mem_req_tag (mem_req_tag),
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.mem_req_ready (mem_req_ready),
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// Memory response
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.mem_rsp_valid (mem_rsp_valid),
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.mem_rsp_tag (mem_rsp_tag),
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.mem_rsp_data (mem_rsp_data),
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.mem_rsp_ready (mem_rsp_ready)
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);
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end else begin
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VX_mem_arb #(
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.NUM_REQS (`NUM_CORES),
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.DATA_WIDTH (`L2MEM_LINE_WIDTH),
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.TAG_IN_WIDTH (`XMEM_TAG_WIDTH),
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.TAG_OUT_WIDTH (`L2MEM_TAG_WIDTH),
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.BUFFERED_REQ (1),
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.BUFFERED_RSP (1)
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) mem_arb (
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.clk (clk),
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.reset (reset),
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// Core request
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.req_valid_in (per_core_mem_req_valid),
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.req_rw_in (per_core_mem_req_rw),
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.req_byteen_in (per_core_mem_req_byteen),
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.req_addr_in (per_core_mem_req_addr),
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.req_data_in (per_core_mem_req_data),
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.req_tag_in (per_core_mem_req_tag),
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.req_ready_in (per_core_mem_req_ready),
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// Memory request
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.req_valid_out (mem_req_valid),
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.req_rw_out (mem_req_rw),
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.req_byteen_out (mem_req_byteen),
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.req_addr_out (mem_req_addr),
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.req_data_out (mem_req_data),
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.req_tag_out (mem_req_tag),
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.req_ready_out (mem_req_ready),
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// Core response
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.rsp_valid_out (per_core_mem_rsp_valid),
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.rsp_data_out (per_core_mem_rsp_data),
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.rsp_tag_out (per_core_mem_rsp_tag),
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.rsp_ready_out (per_core_mem_rsp_ready),
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// Memory response
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.rsp_valid_in (mem_rsp_valid),
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.rsp_tag_in (mem_rsp_tag),
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.rsp_data_in (mem_rsp_data),
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.rsp_ready_in (mem_rsp_ready)
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);
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end
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endmodule
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