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afu
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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cache
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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fp_cores
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fpu dpi update
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2021-03-31 02:36:34 -07:00 |
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interfaces
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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libs
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minor ibuffer critical path optimization.
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2021-04-19 20:53:13 -07:00 |
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tex_unit
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modelsim fixes && pipeline optimization
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2020-07-28 14:20:23 -07:00 |
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.DS_Store
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project directories reorganization
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2020-04-14 06:35:20 -04:00 |
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.gitignore
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fix opae build
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2020-04-20 12:51:42 -07:00 |
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Vortex.v
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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VX_alu_unit.v
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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VX_cluster.v
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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VX_commit.v
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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VX_config.vh
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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VX_core.v
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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VX_csr_arb.v
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minor update
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2021-02-12 08:52:06 -08:00 |
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VX_csr_data.v
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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VX_csr_io_arb.v
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csr minor update
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2021-03-08 03:46:07 -08:00 |
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VX_csr_unit.v
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csr minor update
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2021-03-08 03:46:07 -08:00 |
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VX_databus_arb.v
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databus optimization
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2021-03-29 23:48:04 -07:00 |
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VX_decode.v
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minor updates
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2021-04-04 04:04:41 -07:00 |
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VX_define.vh
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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VX_execute.v
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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VX_fetch.v
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cache request interfaces update
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2021-02-10 20:55:04 -08:00 |
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VX_fpu_unit.v
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adding empty to index_buffer
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2021-03-30 10:15:42 -07:00 |
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VX_gpr_ram_f.v
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minor update
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2021-01-01 20:24:18 -08:00 |
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VX_gpr_ram_i.v
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fixed register file initialization to zero synthesis inference
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2020-12-10 00:27:56 -08:00 |
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VX_gpr_stage.v
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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VX_gpu_unit.v
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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VX_ibuffer.v
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minor ibuffer critical path optimization.
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2021-04-19 20:53:13 -07:00 |
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VX_icache_stage.v
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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VX_instr_demux.v
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minor update
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2021-03-22 23:04:35 -07:00 |
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VX_ipdom_stack.v
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critical path optimization - fpga fmax @4c = ~212 mhz
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2020-12-26 03:28:32 -08:00 |
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VX_issue.v
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perf counters generic size
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2021-04-25 21:15:24 -07:00 |
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VX_lsu_unit.v
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minor update
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2021-04-25 21:10:54 -07:00 |
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VX_mem_arb.v
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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VX_mem_unit.v
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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VX_muldiv.v
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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VX_pipeline.v
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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VX_platform.vh
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arrays logging
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2021-04-02 02:20:15 -07:00 |
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VX_print_instr.vh
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minor update
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2021-02-27 21:54:55 -08:00 |
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VX_scope.vh
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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VX_scoreboard.v
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minor ibuffer critical path optimization.
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2021-04-19 20:53:13 -07:00 |
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VX_types.vh
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FPU float<->int conversion optimization
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2020-12-29 15:37:45 -08:00 |
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VX_warp_sched.v
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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VX_writeback.v
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relaxing commit back-pressure in writeback stage
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2021-03-15 14:39:55 -07:00 |
