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60 lines
No EOL
1.4 KiB
Verilog
60 lines
No EOL
1.4 KiB
Verilog
`include "VX_define.vh"
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module VX_fetch #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_fetch
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input wire clk,
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input wire reset,
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// Icache interface
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VX_icache_core_req_if icache_req_if,
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VX_icache_core_rsp_if icache_rsp_if,
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// inputs
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VX_wstall_if wstall_if,
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VX_join_if join_if,
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VX_branch_ctl_if branch_ctl_if,
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VX_warp_ctl_if warp_ctl_if,
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// outputs
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VX_ifetch_rsp_if ifetch_rsp_if,
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output wire busy
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);
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VX_ifetch_req_if ifetch_req_if();
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VX_warp_sched #(
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.CORE_ID(CORE_ID)
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) warp_sched (
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`SCOPE_BIND_VX_fetch_warp_sched
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.clk (clk),
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.reset (reset),
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.warp_ctl_if (warp_ctl_if),
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.wstall_if (wstall_if),
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.join_if (join_if),
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.branch_ctl_if (branch_ctl_if),
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.ifetch_req_if (ifetch_req_if),
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.ifetch_rsp_if (ifetch_rsp_if),
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.busy (busy)
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);
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VX_icache_stage #(
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.CORE_ID(CORE_ID)
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) icache_stage (
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`SCOPE_BIND_VX_fetch_icache_stage
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.clk (clk),
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.reset (reset),
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.icache_rsp_if (icache_rsp_if),
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.icache_req_if (icache_req_if),
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.ifetch_req_if (ifetch_req_if),
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.ifetch_rsp_if (ifetch_rsp_if)
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);
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endmodule |