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80 lines
2.6 KiB
Verilog
80 lines
2.6 KiB
Verilog
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`include "VX_define.v"
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module VX_memory (
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VX_mem_req_inter VX_mem_req,
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VX_inst_mem_wb_inter VX_mem_wb,
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VX_forward_mem_inter VX_fwd_mem,
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output wire out_delay,
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output wire out_branch_dir,
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output wire[31:0] out_branch_dest,
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input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
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output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
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output wire[2:0] out_cache_driver_in_mem_read,
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output wire[2:0] out_cache_driver_in_mem_write,
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output wire out_cache_driver_in_valid[`NT_M1:0],
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output wire[31:0] out_cache_driver_in_data[`NT_M1:0]
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);
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genvar index;
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for (index = 0; index <= `NT_M1; index = index + 1) begin
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assign out_cache_driver_in_address[index] = VX_mem_req.alu_result[index];
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assign out_cache_driver_in_data[index] = VX_mem_req.rd2[index];
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assign out_cache_driver_in_valid[index] = VX_mem_req.valid[index];
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assign VX_mem_wb.mem_result[index] = in_cache_driver_out_data[index];
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end
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assign out_delay = 1'b0;
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assign out_cache_driver_in_mem_read = VX_mem_req.mem_read;
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assign out_cache_driver_in_mem_write = VX_mem_req.mem_write;
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assign VX_mem_wb.alu_result = VX_mem_req.alu_result;
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assign VX_mem_wb.rd = VX_mem_req.rd;
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assign VX_mem_wb.wb = VX_mem_req.wb;
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assign VX_mem_wb.PC_next = VX_mem_req.PC_next;
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assign VX_mem_wb.valid = VX_mem_req.valid;
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assign VX_mem_wb.warp_num = VX_mem_req.warp_num;
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assign VX_fwd_mem.dest = VX_mem_wb.rd;
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assign VX_fwd_mem.wb = VX_mem_wb.wb;
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assign VX_fwd_mem.alu_result = VX_mem_wb.alu_result;
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assign VX_fwd_mem.mem_data = VX_mem_wb.mem_result;
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assign VX_fwd_mem.PC_next = VX_mem_wb.PC_next;
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assign VX_fwd_mem.warp_num = VX_mem_wb.warp_num;
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reg temp_branch_dir;
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assign out_branch_dest = $signed(VX_mem_req.curr_PC) + ($signed(VX_mem_req.branch_offset) << 1);
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always @(*) begin
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case(VX_mem_req.branch_type)
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`BEQ: temp_branch_dir = (VX_mem_req.alu_result[0] == 0) ? `TAKEN : `NOT_TAKEN;
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`BNE: temp_branch_dir = (VX_mem_req.alu_result[0] == 0) ? `NOT_TAKEN : `TAKEN;
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`BLT: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
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`BGT: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
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`BLTU: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
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`BGTU: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
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`NO_BRANCH: temp_branch_dir = `NOT_TAKEN;
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default: temp_branch_dir = `NOT_TAKEN;
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endcase // in_branch_type
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end
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assign out_branch_dir = temp_branch_dir;
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endmodule // Memory
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