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felsabbagh3 2019-09-08 16:21:37 -04:00
parent fe09aafbb4
commit ac9b06bf7d
49 changed files with 6237 additions and 5268 deletions
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2
rtl/Makefile
View file

@ -3,7 +3,7 @@ all: RUNFILE
VERILATOR:
verilator --compiler gcc -Wall -cc Vortex.v -Iinterfaces/ --exe test_bench.cpp -CFLAGS -std=c++11
verilator --compiler gcc -Wall -cc Vortex.v -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3
RUNFILE: VERILATOR
(cd obj_dir && make -j -f VVortex.mk)

6
rtl/VX_csr_handler.v
View file

@ -3,9 +3,7 @@
module VX_csr_handler (
input wire clk,
input wire[11:0] in_decode_csr_address, // done
/* verilator lint_off UNUSED */
input wire[11:0] in_mem_csr_address,
/* verilator lint_on UNUSED */
input wire in_mem_is_csr,
/* verilator lint_off UNUSED */
input wire[31:0] in_mem_csr_result,
@ -15,7 +13,7 @@ module VX_csr_handler (
);
reg[11:0] csr[1024:0];
reg[1024:0][11:0] csr;
reg[63:0] cycle;
reg[63:0] instret;
reg[11:0] decode_csr_address;
@ -44,9 +42,7 @@ module VX_csr_handler (
always @(posedge clk) begin
if(in_mem_is_csr) begin
/* verilator lint_off WIDTH */
csr[in_mem_csr_address] <= in_mem_csr_result[11:0];
/* verilator lint_on WIDTH */
end
end

76
rtl/VX_decode.v
View file

@ -9,12 +9,14 @@ module VX_decode(
// WriteBack inputs
VX_wb_inter VX_writeback_inter,
// Fwd Request
VX_forward_reqeust_inter VX_fwd_req_de,
// FORWARDING INPUTS
input wire in_src1_fwd,
input wire[`NT_M1:0][31:0] in_src1_fwd_data,
input wire in_src2_fwd,
input wire[`NT_M1:0][31:0] in_src2_fwd_data,
input wire[`NW_M1:0] in_which_wspawn,
VX_forward_response_inter VX_fwd_rsp,
input wire[`NW_M1:0] in_which_wspawn,
// Outputs
VX_frE_to_bckE_req_inter VX_frE_to_bckE_req,
@ -25,6 +27,12 @@ module VX_decode(
);
wire in_src1_fwd = VX_fwd_rsp.src1_fwd;
wire[`NT_M1:0][31:0] in_src1_fwd_data = VX_fwd_rsp.src1_fwd_data;
wire in_src2_fwd = VX_fwd_rsp.src2_fwd;
wire[`NT_M1:0][31:0] in_src2_fwd_data = VX_fwd_rsp.src2_fwd_data;
wire[`NT_M1:0][31:0] in_write_data;
wire[4:0] in_rd;
wire[1:0] in_wb;
@ -105,20 +113,13 @@ module VX_decode(
reg[4:0] alu_op;
reg[4:0] mul_alu;
/* verilator lint_off UNUSED */
wire[31:0][31:0] w0_t0_registers;
/* verilator lint_on UNUSED */
// always @(*) begin
// $display("DECODE WARP: %h", in_warp_num);
// end
// always @(*) begin
// $display("DECODE WARP: %h PC: %h",in_warp_num, in_curr_PC);
// end
assign VX_fwd_req_de.src1 = VX_frE_to_bckE_req.rs1;
assign VX_fwd_req_de.src2 = VX_frE_to_bckE_req.rs2;
assign VX_fwd_req_de.warp_num = VX_frE_to_bckE_req.warp_num;
`ifdef ONLY
@ -231,9 +232,8 @@ module VX_decode(
reg[`NT_M1:0][31:0] temp_out_a_reg_data;
reg[`NT_M1:0][31:0] temp_out_b_reg_data;
/* verilator lint_off UNOPTFLAT */
reg temp_out_clone_stall;
/* verilator lint_on UNOPTFLAT */
always @(*) begin
@ -282,15 +282,6 @@ module VX_decode(
`endif
// assign out_clone_stall = glob_clone_stall[0] || glob_clone_stall[1] ||
// glob_clone_stall[2] || glob_clone_stall[3];
// always @(*) begin
// if (context_one_valid) begin
// $display("PC: %h -> src1: %h\tsrc2: %h",in_curr_PC, one_a_reg_data[0], one_b_reg_data[0]);
// end
// end
assign VX_frE_to_bckE_req.valid = fd_inst_meta_de.valid;
@ -346,9 +337,7 @@ module VX_decode(
genvar tm_i;
generate
for (tm_i = 0; tm_i < `NT; tm_i = tm_i + 1) begin
/* verilator lint_off UNSIGNED */
assign jalrs_thread_mask[tm_i] = tm_i <= $signed(VX_frE_to_bckE_req.b_reg_data[0]);
/* verilator lint_on UNSIGNED */
assign jalrs_thread_mask[tm_i] = $signed(tm_i) <= $signed(VX_frE_to_bckE_req.b_reg_data[0]);
end
endgenerate
@ -369,35 +358,6 @@ module VX_decode(
// assign out_clone = is_clone;
// always @(in_instruction) begin
// $display("Decode inst: %h", in_instruction);
// end
// assign out_reg_data[0] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[0] : rd1_register[0]));
// assign out_reg_data[1] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[0] : rd2_register[0];
// assign out_reg_data[2] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[1] : rd1_register[1]));
// assign out_reg_data[3] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[1] : rd2_register[1];
// assign internal_rd1 = ((is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data : rd1_register));
// assign internal_rd2 = (in_src2_fwd == 1'b1) ? in_src2_fwd_data : rd2_register;
// assign out_reg_data[0] = internal_rd1;
// assign out_reg_data[1] = internal_rd2;
// always @(negedge clk) begin
// if (in_curr_PC == 32'h800001f0) begin
// $display("IN DECODE: Going to write to: %d with val: %h [%h, %h, %h]", VX_frE_to_bckE_req.rd, internal_rd1, in_curr_PC, in_src1_fwd_data, rd1_register);
// end
// end
assign VX_frE_to_bckE_req.is_csr = is_csr;
assign VX_frE_to_bckE_req.csr_mask = (is_csr_immed == 1'b1) ? {27'h0, VX_frE_to_bckE_req.rs1} : VX_frE_to_bckE_req.a_reg_data[0];

49
rtl/VX_e_m_reg.v
View file

@ -1,49 +0,0 @@
`include "VX_define.v"
module VX_e_m_reg (
input wire clk,
input wire reset,
input wire in_freeze,
input wire[11:0] in_csr_address,
input wire in_is_csr,
input wire[31:0] in_csr_result,
input wire in_jal,
input wire[31:0] in_jal_dest,
input wire[`NT_M1:0][31:0] in_a_reg_data,
input wire[`NT_M1:0][31:0] in_b_reg_data,
VX_mem_req_inter VX_exe_mem_req,
VX_mem_req_inter VX_mem_req,
output wire[11:0] out_csr_address,
output wire out_is_csr,
output wire[31:0] out_csr_result,
output wire[`NT_M1:0][31:0] out_a_reg_data,
output wire[`NT_M1:0][31:0] out_b_reg_data,
output wire out_jal,
output wire[31:0] out_jal_dest
);
wire flush = 0;
wire stall = in_freeze;
VX_generic_register #(.N(720)) f_d_reg
(
.clk (clk),
.reset(reset),
.stall(stall),
.flush(flush),
.in ({in_csr_address , in_is_csr , in_csr_result , in_jal , in_jal_dest , in_a_reg_data , in_b_reg_data , VX_exe_mem_req.alu_result, VX_exe_mem_req.mem_read, VX_exe_mem_req.mem_write, VX_exe_mem_req.rd, VX_exe_mem_req.wb, VX_exe_mem_req.rs1, VX_exe_mem_req.rs2, VX_exe_mem_req.rd2, VX_exe_mem_req.PC_next, VX_exe_mem_req.curr_PC, VX_exe_mem_req.branch_offset, VX_exe_mem_req.branch_type, VX_exe_mem_req.valid, VX_exe_mem_req.warp_num}),
.out ({out_csr_address, out_is_csr, out_csr_result, out_jal, out_jal_dest, out_a_reg_data, out_b_reg_data, VX_mem_req.alu_result , VX_mem_req.mem_read , VX_mem_req.mem_write , VX_mem_req.rd , VX_mem_req.wb , VX_mem_req.rs1 , VX_mem_req.rs2 , VX_mem_req.rd2 , VX_mem_req.PC_next , VX_mem_req.curr_PC , VX_mem_req.branch_offset , VX_mem_req.branch_type , VX_mem_req.valid , VX_mem_req.warp_num})
);
endmodule // VX_e_m_reg

17
rtl/VX_execute.v
View file

@ -3,14 +3,13 @@
module VX_execute (
VX_frE_to_bckE_req_inter VX_bckE_req,
VX_forward_exe_inter VX_fwd_exe,
input wire[31:0] in_csr_data,
VX_mem_req_inter VX_exe_mem_req,
output wire[11:0] out_csr_address,
output wire out_is_csr,
output reg[31:0] out_csr_result,
output wire[`NT_M1:0][31:0] out_a_reg_data,
output wire[`NT_M1:0][31:0] out_b_reg_data,
output wire out_jal,
output wire[31:0] out_jal_dest,
output wire out_branch_stall
@ -81,13 +80,6 @@ module VX_execute (
assign out_branch_stall = ((in_branch_type != `NO_BRANCH) || in_jal ) ? `STALL : `NO_STALL;
genvar ind;
for (ind = 0; ind <= `NT_M1; ind = ind + 1) begin
assign out_a_reg_data[ind] = in_a_reg_data[ind];
assign out_b_reg_data[ind] = in_b_reg_data[ind];
end
assign VX_exe_mem_req.mem_read = VX_bckE_req.mem_read;
assign VX_exe_mem_req.mem_write = VX_bckE_req.mem_write;
assign VX_exe_mem_req.wb = VX_bckE_req.wb;
@ -104,6 +96,13 @@ module VX_execute (
assign VX_exe_mem_req.warp_num = VX_bckE_req.warp_num;
assign VX_fwd_exe.dest = VX_exe_mem_req.rd;
assign VX_fwd_exe.wb = VX_exe_mem_req.wb;
assign VX_fwd_exe.alu_result = VX_exe_mem_req.alu_result;
assign VX_fwd_exe.PC_next = VX_exe_mem_req.PC_next;
assign VX_fwd_exe.warp_num = VX_exe_mem_req.warp_num;
assign out_is_csr = VX_bckE_req.is_csr;
assign out_csr_address = VX_bckE_req.csr_address;

206
rtl/VX_fetch_old.v
View file

@ -1,206 +0,0 @@
`include "VX_define.v"
module VX_fetch (
input wire clk,
input wire reset,
input wire in_branch_dir,
input wire in_freeze,
input wire[31:0] in_branch_dest,
input wire in_branch_stall,
input wire in_fwd_stall,
input wire in_branch_stall_exe,
input wire in_clone_stall,
input wire in_jal,
input wire[31:0] in_jal_dest,
input wire in_interrupt,
input wire in_debug,
input wire[31:0] in_instruction,
input wire in_thread_mask[`NT_M1:0],
input wire in_change_mask,
input wire[`NW_M1:0] in_decode_warp_num,
input wire[`NW_M1:0] in_memory_warp_num,
input wire in_wspawn,
input wire[31:0] in_wspawn_pc,
input wire in_ebreak,
output wire[31:0] out_instruction,
output wire out_delay,
output wire[`NW_M1:0] out_warp_num,
output wire[31:0] out_curr_PC,
output wire out_valid[`NT_M1:0],
output wire out_ebreak,
output wire[`NW_M1:0] out_which_wspawn
);
reg stall;
reg[31:0] out_PC;
reg[`NW_M1:0] warp_num;
reg[`NW_M1:0] warp_state;
reg[`NW_M1:0] warp_count;
// reg[31:0] num_ecalls;
initial begin
warp_num = 0;
warp_state = 0;
// num_ecalls = 0;
warp_count = 1;
end
// always @(posedge clk) begin
// if (in_ebreak) begin
// num_ecalls <= num_ecalls + 1;
// $display("--------> New num_ecalls = %h", num_ecalls+1);
// end
// end
wire add_warp = in_wspawn && !in_ebreak && !in_clone_stall;
wire remove_warp = in_ebreak && !in_wspawn && !in_clone_stall;
always @(posedge clk or posedge reset) begin
if (reset || (warp_num >= warp_state) || remove_warp || add_warp) begin
warp_num <= 0;
`ifndef ONLY
end else if (!warp_glob_valid[warp_num+1]) begin
// $display("Skipping one");
warp_num <= warp_num + 2;
`endif
end else begin
warp_num <= warp_num + 1;
end
if (add_warp) begin
warp_state <= warp_state + 1;
warp_count <= warp_count + 1;
// $display("Adding a new warp %h", warp_state+1);
end else if (remove_warp) begin // No removing, just invalidating
warp_count <= warp_count - 1;
// $display("Removing a warp %h %h", in_decode_warp_num, warp_count);
if (warp_count == 2) begin
// $display("&&&&&&&&&&&&& STATE 0");
warp_state <= 0;
end
end
end
assign out_ebreak = (in_decode_warp_num == 0) && in_ebreak;
assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || in_freeze || in_debug;
assign out_which_wspawn = (warp_state+1);
`ifdef ONLY
wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
wire warp_zero_jal = in_jal && (in_memory_warp_num == 0);
wire warp_zero_branch = in_branch_dir && (in_memory_warp_num == 0);
wire warp_zero_stall = stall || (warp_num != 0);
wire warp_zero_wspawn = (0 == 0) ? 0 : (in_wspawn && ((warp_state+1) == 0));
wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
wire warp_zero_remove = remove_warp && (in_decode_warp_num == 0);
// always @(*) begin : proc_
// if (warp_zero_remove) $display("4Removing warp: %h", 0);
// end
VX_warp VX_Warp(
.clk (clk),
.reset (reset),
.stall (warp_zero_stall),
.remove (warp_zero_remove),
.in_thread_mask(in_thread_mask),
.in_change_mask(warp_zero_change_mask),
.in_jal (warp_zero_jal),
.in_jal_dest (in_jal_dest),
.in_branch_dir (warp_zero_branch),
.in_branch_dest(in_branch_dest),
.in_wspawn (warp_zero_wspawn),
.in_wspawn_pc (warp_zero_wspawn_pc),
.out_PC (out_PC),
.out_valid (out_valid)
);
`else
wire[31:0] warp_glob_pc[`NW-1:0];
wire warp_glob_valid[`NW-1:0][`NT_M1:0];
genvar cur_warp;
generate
for (cur_warp = 0; cur_warp < `NW; cur_warp = cur_warp + 1)
begin
wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == cur_warp);
wire warp_zero_jal = in_jal && (in_memory_warp_num == cur_warp);
wire warp_zero_branch = in_branch_dir && (in_memory_warp_num == cur_warp);
wire warp_zero_stall = stall || (warp_num != cur_warp);
wire warp_zero_wspawn = (cur_warp == 0) ? 0 : (in_wspawn && ((warp_state+1) == cur_warp));
wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
wire warp_zero_remove = remove_warp && (in_decode_warp_num == cur_warp);
// always @(*) begin : proc_
// if (warp_zero_remove) $display("4Removing warp: %h", cur_warp);
// end
VX_warp VX_Warp(
.clk (clk),
.reset (reset),
.stall (warp_zero_stall),
.remove (warp_zero_remove),
.in_thread_mask(in_thread_mask),
.in_change_mask(warp_zero_change_mask),
.in_jal (warp_zero_jal),
.in_jal_dest (in_jal_dest),
.in_branch_dir (warp_zero_branch),
.in_branch_dest(in_branch_dest),
.in_wspawn (warp_zero_wspawn),
.in_wspawn_pc (warp_zero_wspawn_pc),
.out_PC (warp_glob_pc[cur_warp]),
.out_valid (warp_glob_valid[cur_warp])
);
end
endgenerate
reg[31:0] out_PC_var;
reg out_valid_var[`NT_M1:0];
always @(*) begin : help
integer g;
integer h;
for (g = 0; g < `NW; g = g + 1)
begin
if (warp_num == g[`NW_M1:0])
begin
out_PC_var = warp_glob_pc[g][31:0];
for (h = 0; h < `NT; h = h + 1) out_valid_var[h] = warp_glob_valid[g][h];
end
end
end
assign out_PC = out_PC_var;
assign out_valid = out_valid_var;
// always @(*) begin
// if (out_valid[0]) begin
// $display("[%d] %h #%b#",out_warp_num, out_PC, out_valid);
// end
// end
`endif
assign out_curr_PC = out_PC;
assign out_warp_num = warp_num;
assign out_delay = 0;
assign out_instruction = stall ? 32'b0 : in_instruction;
endmodule

101
rtl/VX_forwarding.v
View file

@ -3,51 +3,54 @@
module VX_forwarding (
// INFO FROM DECODE
input wire[4:0] in_decode_src1,
input wire[4:0] in_decode_src2,
input wire[11:0] in_decode_csr_address,
input wire[`NW_M1:0] in_decode_warp_num,
VX_forward_reqeust_inter VX_fwd_req_de,
VX_forward_exe_inter VX_fwd_exe,
VX_forward_mem_inter VX_fwd_mem,
VX_forward_wb_inter VX_fwd_wb,
// INFO FROM EXE
input wire[4:0] in_execute_dest,
input wire[1:0] in_execute_wb,
input wire[`NT_M1:0][31:0] in_execute_alu_result,
input wire[31:0] in_execute_PC_next,
input wire in_execute_is_csr,
input wire[11:0] in_execute_csr_address,
input wire[`NW_M1:0] in_execute_warp_num,
// INFO FROM MEM
input wire[4:0] in_memory_dest,
input wire[1:0] in_memory_wb,
input wire[`NT_M1:0][31:0] in_memory_alu_result,
input wire[`NT_M1:0][31:0] in_memory_mem_data,
input wire[31:0] in_memory_PC_next,
input wire in_memory_is_csr,
input wire[11:0] in_memory_csr_address,
input wire[31:0] in_memory_csr_result,
input wire[`NW_M1:0] in_memory_warp_num,
// INFO FROM WB
input wire[4:0] in_writeback_dest,
input wire[1:0] in_writeback_wb,
input wire[`NT_M1:0][31:0] in_writeback_alu_result,
input wire[`NT_M1:0][31:0] in_writeback_mem_data,
input wire[31:0] in_writeback_PC_next,
input wire[`NW_M1:0] in_writeback_warp_num,
// OUT SIGNALS
output wire out_src1_fwd,
output wire out_src2_fwd,
output wire out_csr_fwd,
output wire[`NT_M1:0][31:0] out_src1_fwd_data,
output wire[`NT_M1:0][31:0] out_src2_fwd_data,
output wire[31:0] out_csr_fwd_data,
output wire out_fwd_stall
VX_forward_response_inter VX_fwd_rsp,
output wire out_fwd_stall
);
wire[4:0] in_decode_src1 = VX_fwd_req_de.src1;
wire[4:0] in_decode_src2 = VX_fwd_req_de.src2;
wire[`NW_M1:0] in_decode_warp_num = VX_fwd_req_de.warp_num;
wire[4:0] in_execute_dest = VX_fwd_exe.dest;
wire[1:0] in_execute_wb = VX_fwd_exe.wb;
wire[`NT_M1:0][31:0] in_execute_alu_result = VX_fwd_exe.alu_result;
wire[31:0] in_execute_PC_next = VX_fwd_exe.PC_next;
wire[`NW_M1:0] in_execute_warp_num = VX_fwd_exe.warp_num;
wire[4:0] in_memory_dest = VX_fwd_mem.dest;
wire[1:0] in_memory_wb = VX_fwd_mem.wb;
wire[`NT_M1:0][31:0] in_memory_alu_result = VX_fwd_mem.alu_result;
wire[`NT_M1:0][31:0] in_memory_mem_data = VX_fwd_mem.mem_data;
wire[31:0] in_memory_PC_next = VX_fwd_mem.PC_next;
wire[`NW_M1:0] in_memory_warp_num = VX_fwd_mem.warp_num;
wire[4:0] in_writeback_dest = VX_fwd_wb.dest;
wire[1:0] in_writeback_wb = VX_fwd_wb.wb;
wire[`NT_M1:0][31:0] in_writeback_alu_result = VX_fwd_wb.alu_result;
wire[`NT_M1:0][31:0] in_writeback_mem_data = VX_fwd_wb.mem_data;
wire[31:0] in_writeback_PC_next = VX_fwd_wb.PC_next;
wire[`NW_M1:0] in_writeback_warp_num = VX_fwd_wb.warp_num;
wire out_src1_fwd;
wire out_src2_fwd;
wire[`NT_M1:0][31:0] out_src1_fwd_data;
wire[`NT_M1:0][31:0] out_src2_fwd_data;
assign VX_fwd_rsp.src1_fwd = out_src1_fwd;
assign VX_fwd_rsp.src2_fwd = out_src2_fwd;
assign VX_fwd_rsp.src1_fwd_data = out_src1_fwd_data;
assign VX_fwd_rsp.src2_fwd_data = out_src2_fwd_data;
wire exe_mem_read;
wire mem_mem_read;
@ -55,16 +58,12 @@ module VX_forwarding (
wire exe_jal;
wire mem_jal;
wire wb_jal ;
wire exe_csr;
wire mem_csr;
wire src1_exe_fwd;
wire src1_mem_fwd;
wire src1_wb_fwd;
wire src2_exe_fwd;
wire src2_mem_fwd;
wire src2_wb_fwd;
wire csr_exe_fwd;
wire csr_mem_fwd;
wire[`NT_M1:0][31:0] use_execute_PC_next;
wire[`NT_M1:0][31:0] use_memory_PC_next;
@ -90,8 +89,6 @@ module VX_forwarding (
assign mem_jal = (in_memory_wb == `WB_JAL);
assign wb_jal = (in_writeback_wb == `WB_JAL);
assign exe_csr = (in_execute_is_csr == 1'b1);
assign mem_csr = (in_memory_is_csr == 1'b1);
// SRC1
@ -144,12 +141,6 @@ module VX_forwarding (
// CSR
assign csr_exe_fwd = (in_decode_csr_address == in_execute_csr_address) && exe_csr;
assign csr_mem_fwd = (in_decode_csr_address == in_memory_csr_address) && mem_csr && !csr_exe_fwd;
assign out_csr_fwd = csr_exe_fwd || csr_mem_fwd; // COMMENT
wire exe_mem_read_stall = ((src1_exe_fwd || src2_exe_fwd) && exe_mem_read) ? `STALL : `NO_STALL;
wire mem_mem_read_stall = ((src1_mem_fwd || src2_mem_fwd) && mem_mem_read) ? `STALL : `NO_STALL;
@ -170,10 +161,6 @@ module VX_forwarding (
( src2_wb_fwd ) ? (wb_jal ? use_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) :
in_execute_alu_result; // last one should be deadbeef
assign out_csr_fwd_data = csr_exe_fwd ? in_execute_alu_result[0][31:0] :
csr_mem_fwd ? in_memory_csr_result[31:0] :
in_execute_alu_result[0][31:0]; // last one should be deadbeef

70
rtl/VX_front_end.v
View file

@ -1,16 +1,74 @@
module VX_front_end (
input clk, // Clock
input reset,
input icache_response_t icache_response,
output icache_request_t icache_request,
input wire clk,
input wire reset,
);
VX_fetch vx_fetch(
.clk (clk),
.reset (reset),
.in_branch_dir (memory_branch_dir),
.in_freeze (total_freeze),
.in_branch_dest (memory_branch_dest),
.in_branch_stall (decode_branch_stall),
.in_fwd_stall (forwarding_fwd_stall),
.in_branch_stall_exe(execute_branch_stall),
.in_clone_stall (decode_clone_stall),
.in_jal (e_m_jal),
.in_jal_dest (e_m_jal_dest),
.in_interrupt (interrupt),
.in_debug (debug),
.in_memory_warp_num (VX_mem_wb.warp_num),
.icache_response (icache_response_fe),
.VX_warp_ctl (VX_warp_ctl),
.icache_request (icache_request_fe),
.out_delay (fetch_delay),
.out_ebreak (fetch_ebreak),
.out_which_wspawn (fetch_which_warp),
.fe_inst_meta_fd (fe_inst_meta_fd)
);
VX_f_d_reg vx_f_d_reg(
.clk (clk),
.reset (reset),
.in_fwd_stall (forwarding_fwd_stall),
.in_freeze (total_freeze),
.in_clone_stall (decode_clone_stall),
.fe_inst_meta_fd(fe_inst_meta_fd),
.fd_inst_meta_de(fd_inst_meta_de)
);
VX_decode vx_decode(
.clk (clk),
.fd_inst_meta_de (fd_inst_meta_de),
.VX_writeback_inter(VX_writeback_inter),
.VX_fwd_rsp (VX_fwd_rsp),
.in_which_wspawn (fetch_which_warp),
.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
.VX_fwd_req_de (VX_fwd_req_de),
.VX_warp_ctl (VX_warp_ctl),
.out_clone_stall (decode_clone_stall),
.out_branch_stall (decode_branch_stall)
);
VX_d_e_reg vx_d_e_reg(
.clk (clk),
.reset (reset),
.in_fwd_stall (forwarding_fwd_stall),
.in_branch_stall(execute_branch_stall),
.in_freeze (total_freeze),
.in_clone_stall (decode_clone_stall),
.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
.VX_bckE_req (VX_bckE_req)
);
endmodule

42
rtl/VX_m_w_reg.v
View file

@ -1,42 +0,0 @@
`include "VX_define.v"
module VX_m_w_reg (
input wire clk,
input wire reset,
VX_inst_mem_wb_inter VX_mem_wb,
input wire in_freeze,
output wire[`NT_M1:0][31:0] out_alu_result,
output wire[`NT_M1:0][31:0] out_mem_result, // NEW
output wire[4:0] out_rd,
output wire[1:0] out_wb,
output wire[4:0] out_rs1,
output wire[4:0] out_rs2,
output wire[31:0] out_PC_next,
output wire[`NT_M1:0] out_valid,
output wire[`NW_M1:0] out_warp_num
);
wire flush = 0;
wire stall = in_freeze;
VX_generic_register #(.N(313)) m_w_reg
(
.clk (clk),
.reset(reset),
.stall(stall),
.flush(flush),
.in ({VX_mem_wb.alu_result, VX_mem_wb.mem_result, VX_mem_wb.rd, VX_mem_wb.wb, VX_mem_wb.rs1, VX_mem_wb.rs2, VX_mem_wb.PC_next, VX_mem_wb.valid, VX_mem_wb.warp_num}),
.out ({out_alu_result , out_mem_result , out_rd , out_wb , out_rs1 , out_rs2 , out_PC_next , out_valid , out_warp_num })
);
endmodule // VX_m_w_reg

11
rtl/VX_memory.v
View file

@ -6,6 +6,8 @@ module VX_memory (
VX_mem_req_inter VX_mem_req,
VX_inst_mem_wb_inter VX_mem_wb,
VX_forward_mem_inter VX_fwd_mem,
output wire out_delay,
@ -41,12 +43,17 @@ module VX_memory (
assign VX_mem_wb.alu_result = VX_mem_req.alu_result;
assign VX_mem_wb.rd = VX_mem_req.rd;
assign VX_mem_wb.wb = VX_mem_req.wb;
assign VX_mem_wb.rs1 = VX_mem_req.rs1;
assign VX_mem_wb.rs2 = VX_mem_req.rs2;
assign VX_mem_wb.PC_next = VX_mem_req.PC_next;
assign VX_mem_wb.valid = VX_mem_req.valid;
assign VX_mem_wb.warp_num = VX_mem_req.warp_num;
assign VX_fwd_mem.dest = VX_mem_wb.rd;
assign VX_fwd_mem.wb = VX_mem_wb.wb;
assign VX_fwd_mem.alu_result = VX_mem_wb.alu_result;
assign VX_fwd_mem.mem_data = VX_mem_wb.mem_result;
assign VX_fwd_mem.PC_next = VX_mem_wb.PC_next;
assign VX_fwd_mem.warp_num = VX_mem_wb.warp_num;
reg temp_branch_dir;

42
rtl/VX_writeback.v
View file

@ -3,35 +3,27 @@
module VX_writeback (
/* verilator lint_off UNUSED */
input wire clk,
/* verilator lint_off UNUSED */
input wire[`NT_M1:0][31:0] in_alu_result,
input wire[`NT_M1:0][31:0] in_mem_result,
input wire[4:0] in_rd,
input wire[1:0] in_wb,
input wire[31:0] in_PC_next,
/* verilator lint_off UNUSED */
input wire[`NT_M1:0] in_valid,
/* verilator lint_on UNUSED */
input wire [`NW_M1:0] in_warp_num,
VX_wb_inter VX_writeback_inter
VX_mw_wb_inter VX_mw_wb,
VX_forward_wb_inter VX_fwd_wb,
VX_wb_inter VX_writeback_inter
);
wire[`NT_M1:0][31:0] in_alu_result = VX_mw_wb.alu_result;
wire[`NT_M1:0][31:0] in_mem_result = VX_mw_wb.mem_result;
wire[4:0] in_rd = VX_mw_wb.rd;
wire[1:0] in_wb = VX_mw_wb.wb;
wire[31:0] in_PC_next = VX_mw_wb.PC_next;
wire[`NT_M1:0] in_valid = VX_mw_wb.valid;
wire [`NW_M1:0] in_warp_num = VX_mw_wb.warp_num;
wire is_jal;
wire uses_alu;
wire[`NT_M1:0][31:0] out_pc_data;
// genvar index;
// for (index=0; index < `NT; index=index+1)
// assign out_pc_data[index] = in_PC_next;
// generate
// endgenerate
genvar i;
generate
for (i = 0; i < `NT; i=i+1)
@ -57,4 +49,12 @@ module VX_writeback (
assign VX_writeback_inter.wb_warp_num = in_warp_num;
assign VX_fwd_wb.dest = VX_writeback_inter.rd;
assign VX_fwd_wb.wb = VX_writeback_inter.wb;
assign VX_fwd_wb.alu_result = in_alu_result;
assign VX_fwd_wb.mem_data = in_mem_result;
assign VX_fwd_wb.PC_next = in_PC_next;
assign VX_fwd_wb.warp_num = VX_writeback_inter.wb_warp_num;
endmodule // VX_writeback

146
rtl/Vortex.v
View file

@ -34,12 +34,10 @@ wire decode_clone_stall;
// From execute
wire execute_branch_stall;
wire[11:0] execute_csr_address;
wire execute_is_csr;
reg[31:0] execute_csr_result;
wire[`NT_M1:0][31:0] execute_a_reg_data;
wire[`NT_M1:0][31:0] execute_b_reg_data;
wire execute_branch_stall;
wire[11:0] execute_csr_address;
wire execute_is_csr;
reg[31:0] execute_csr_result;
wire execute_jal;
wire[31:0] execute_jal_dest;
@ -50,10 +48,6 @@ wire[31:0] e_m_jal_dest;
wire[11:0] e_m_csr_address;
wire e_m_is_csr;
wire[31:0] e_m_csr_result;
/* verilator lint_off UNUSED */
wire[`NT_M1:0][31:0] e_m_a_reg_data;
wire[`NT_M1:0][31:0] e_m_b_reg_data;
/* verilator lint_on UNUSED */
// From memory
@ -61,33 +55,12 @@ wire memory_delay;
wire memory_branch_dir;
wire[31:0] memory_branch_dest;
// From m_w_register
wire[`NT_M1:0][31:0] m_w_alu_result;
wire[`NT_M1:0][31:0] m_w_mem_result;
wire[4:0] m_w_rd;
wire[1:0] m_w_wb;
/* verilator lint_off UNUSED */
wire[4:0] m_w_rs1;
wire[4:0] m_w_rs2;
/* verilator lint_on UNUSED */
wire[31:0] m_w_PC_next;
wire[`NT_M1:0] m_w_valid;
wire[`NW_M1:0] m_w_warp_num;
// From csr handler
wire[31:0] csr_decode_csr_data;
// From forwarding
wire forwarding_fwd_stall;
wire forwarding_src1_fwd;
wire forwarding_src2_fwd;
/* verilator lint_off UNUSED */
wire forwarding_csr_fwd;
wire[31:0] forwarding_csr_fwd_data;
/* verilator lint_on UNUSED */
wire[`NT_M1:0][31:0] forwarding_src1_fwd_data;
wire[`NT_M1:0][31:0] forwarding_src2_fwd_data;
// Internal
@ -116,9 +89,18 @@ VX_mem_req_inter VX_mem_req();
VX_inst_mem_wb_inter VX_mem_wb();
VX_mw_wb_inter VX_mw_wb();
VX_warp_ctl_inter VX_warp_ctl();
VX_wb_inter VX_writeback_inter();
VX_forward_reqeust_inter VX_fwd_req_de();
VX_forward_exe_inter VX_fwd_exe();
VX_forward_mem_inter VX_fwd_mem();
VX_forward_wb_inter VX_fwd_wb();
VX_forward_response_inter VX_fwd_rsp();
assign icache_response_fe.instruction = icache_response_instruction;
assign icache_request_pc_address = icache_request_fe.pc_address;
@ -160,16 +142,14 @@ VX_f_d_reg vx_f_d_reg(
VX_decode vx_decode(
.clk (clk),
.fd_inst_meta_de (fd_inst_meta_de),
.clk (clk),
.fd_inst_meta_de (fd_inst_meta_de),
.VX_writeback_inter(VX_writeback_inter),
.in_src1_fwd (forwarding_src1_fwd),
.in_src1_fwd_data(forwarding_src1_fwd_data),
.in_src2_fwd (forwarding_src2_fwd),
.in_src2_fwd_data(forwarding_src2_fwd_data),
.VX_fwd_rsp (VX_fwd_rsp),
.in_which_wspawn (fetch_which_warp),
.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
.VX_fwd_req_de (VX_fwd_req_de),
.VX_warp_ctl (VX_warp_ctl),
.out_clone_stall (decode_clone_stall),
.out_branch_stall (decode_branch_stall)
@ -189,6 +169,7 @@ VX_d_e_reg vx_d_e_reg(
VX_execute vx_execute(
.VX_bckE_req (VX_bckE_req),
.VX_fwd_exe (VX_fwd_exe),
.in_csr_data (csr_decode_csr_data),
.VX_exe_mem_req (VX_exe_mem_req),
@ -197,9 +178,7 @@ VX_execute vx_execute(
.out_csr_result (execute_csr_result),
.out_jal (execute_jal),
.out_jal_dest (execute_jal_dest),
.out_branch_stall (execute_branch_stall),
.out_a_reg_data (execute_a_reg_data),
.out_b_reg_data (execute_b_reg_data)
.out_branch_stall (execute_branch_stall)
);
VX_e_m_reg vx_e_m_reg(
@ -212,28 +191,19 @@ VX_e_m_reg vx_e_m_reg(
.in_jal_dest (execute_jal_dest),
.in_freeze (total_freeze),
.VX_exe_mem_req (VX_exe_mem_req),
.in_a_reg_data (execute_a_reg_data),
.in_b_reg_data (execute_b_reg_data),
.VX_mem_req (VX_mem_req),
.out_csr_address (e_m_csr_address),
.out_is_csr (e_m_is_csr),
.out_csr_result (e_m_csr_result),
.out_a_reg_data (e_m_a_reg_data),
.out_b_reg_data (e_m_b_reg_data),
.out_jal (e_m_jal),
.out_jal_dest (e_m_jal_dest)
);
// wire[31:0] use_rd2[`NT_M1:0];
// assign use_rd2[0] = e_m_reg_data[1];
// assign use_rd2[1] = e_m_reg_data[3];
VX_memory vx_memory(
.VX_mem_req (VX_mem_req),
.VX_mem_wb (VX_mem_wb),
.VX_fwd_mem (VX_fwd_mem),
.out_delay (memory_delay),
.out_branch_dir (memory_branch_dir),
@ -248,75 +218,27 @@ VX_memory vx_memory(
);
VX_m_w_reg vx_m_w_reg(
.clk (clk),
.reset (reset),
.VX_mem_wb (VX_mem_wb),
.in_freeze (total_freeze),
.out_alu_result(m_w_alu_result),
.out_mem_result(m_w_mem_result),
.out_rd (m_w_rd),
.out_wb (m_w_wb),
.out_rs1 (m_w_rs1),
.out_rs2 (m_w_rs2),
.out_PC_next (m_w_PC_next),
.out_valid (m_w_valid),
.out_warp_num (m_w_warp_num)
.clk (clk),
.reset (reset),
.in_freeze (total_freeze),
.VX_mem_wb (VX_mem_wb),
.VX_mw_wb (VX_mw_wb)
);
VX_writeback vx_writeback(
.clk (clk),
.in_alu_result (m_w_alu_result),
.in_mem_result (m_w_mem_result),
.in_rd (m_w_rd),
.in_wb (m_w_wb),
.in_PC_next (m_w_PC_next),
.in_valid (m_w_valid),
.in_warp_num (m_w_warp_num),
.VX_mw_wb (VX_mw_wb),
.VX_fwd_wb (VX_fwd_wb),
.VX_writeback_inter(VX_writeback_inter)
);
VX_forwarding vx_forwarding(
.in_decode_src1 (VX_frE_to_bckE_req.rs1),
.in_decode_src2 (VX_frE_to_bckE_req.rs2),
.in_decode_csr_address (VX_frE_to_bckE_req.csr_address),
.in_decode_warp_num (VX_frE_to_bckE_req.warp_num),
.in_execute_dest (VX_exe_mem_req.rd),
.in_execute_wb (VX_exe_mem_req.wb),
.in_execute_alu_result (VX_exe_mem_req.alu_result),
.in_execute_PC_next (VX_exe_mem_req.PC_next),
.in_execute_is_csr (execute_is_csr),
.in_execute_csr_address (execute_csr_address),
.in_execute_warp_num (VX_exe_mem_req.warp_num),
.in_memory_dest (VX_mem_wb.rd),
.in_memory_wb (VX_mem_wb.wb),
.in_memory_alu_result (VX_mem_wb.alu_result),
.in_memory_mem_data (VX_mem_wb.mem_result),
.in_memory_PC_next (VX_mem_wb.PC_next),
.in_memory_is_csr (e_m_is_csr),
.in_memory_csr_address (e_m_csr_address),
.in_memory_csr_result (e_m_csr_result),
.in_memory_warp_num (VX_mem_wb.warp_num),
.in_writeback_dest (m_w_rd),
.in_writeback_wb (m_w_wb),
.in_writeback_alu_result(m_w_alu_result),
.in_writeback_mem_data (m_w_mem_result),
.in_writeback_PC_next (m_w_PC_next),
.in_writeback_warp_num (VX_writeback_inter.wb_warp_num),
.out_src1_fwd (forwarding_src1_fwd),
.out_src2_fwd (forwarding_src2_fwd),
.out_csr_fwd (forwarding_csr_fwd),
.out_src1_fwd_data (forwarding_src1_fwd_data),
.out_src2_fwd_data (forwarding_src2_fwd_data),
.out_csr_fwd_data (forwarding_csr_fwd_data),
.out_fwd_stall (forwarding_fwd_stall)
.VX_fwd_req_de(VX_fwd_req_de),
.VX_fwd_exe (VX_fwd_exe),
.VX_fwd_mem (VX_fwd_mem),
.VX_fwd_wb (VX_fwd_wb),
.VX_fwd_rsp (VX_fwd_rsp),
.out_fwd_stall(forwarding_fwd_stall)
);
VX_csr_handler vx_csr_handler(
@ -325,7 +247,7 @@ VX_csr_handler vx_csr_handler(
.in_mem_csr_address (e_m_csr_address),
.in_mem_is_csr (e_m_is_csr),
.in_mem_csr_result (e_m_csr_result),
.in_wb_valid (m_w_valid[0]),
.in_wb_valid (VX_mw_wb.valid[0]),
.out_decode_csr_data (csr_decode_csr_data)
);

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rtl/interfaces/VX_forward_csr_response_inter.sv Normal file
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@ -0,0 +1,32 @@
`include "VX_define.v"
`ifndef VX_FWD_CSR_RSP
`define VX_FWD_CSR_RSP
interface VX_forward_csr_response_inter ();
/* verilator lint_off UNUSED */
wire csr_fwd;
wire[31:0] csr_fwd_data;
/* verilator lint_on UNUSED */
// source-side view
modport snk (
input csr_fwd,
input csr_fwd_data
);
// source-side view
modport src (
output csr_fwd,
output csr_fwd_data
);
endinterface
`endif

39
rtl/interfaces/VX_forward_exe_inter.v Normal file
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@ -0,0 +1,39 @@
`include "VX_define.v"
`ifndef VX_FWD_EXE
`define VX_FWD_EXE
interface VX_forward_exe_inter ();
wire[4:0] dest;
wire[1:0] wb;
wire[`NT_M1:0][31:0] alu_result;
wire[31:0] PC_next;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input dest,
input wb,
input alu_result,
input PC_next,
input warp_num
);
// source-side view
modport src (
output dest,
output wb,
output alu_result,
output PC_next,
output warp_num
);
endinterface
`endif

42
rtl/interfaces/VX_forward_mem_inter.sv Normal file
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@ -0,0 +1,42 @@
`include "VX_define.v"
`ifndef VX_FWD_MEM
`define VX_FWD_MEM
interface VX_forward_mem_inter ();
wire[4:0] dest;
wire[1:0] wb;
wire[`NT_M1:0][31:0] alu_result;
wire[`NT_M1:0][31:0] mem_data;
wire[31:0] PC_next;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input dest,
input wb,
input alu_result,
input mem_data,
input PC_next,
input warp_num
);
// source-side view
modport src (
output dest,
output wb,
output alu_result,
output mem_data,
output PC_next,
output warp_num
);
endinterface
`endif

33
rtl/interfaces/VX_forward_reqeust_inter.v Normal file
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@ -0,0 +1,33 @@
`include "VX_define.v"
`ifndef VX_FWD_REQ
`define VX_FWD_REQ
interface VX_forward_reqeust_inter ();
wire[4:0] src1;
wire[4:0] src2;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input src1,
input src2,
input warp_num
);
// source-side view
modport src (
output src1,
output src2,
output warp_num
);
endinterface
`endif

36
rtl/interfaces/VX_forward_response_inter.v Normal file
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@ -0,0 +1,36 @@
`include "VX_define.v"
`ifndef VX_FWD_RSP
`define VX_FWD_RSP
interface VX_forward_response_inter ();
wire src1_fwd;
wire src2_fwd;
wire[`NT_M1:0][31:0] src1_fwd_data;
wire[`NT_M1:0][31:0] src2_fwd_data;
// source-side view
modport snk (
input src1_fwd,
input src2_fwd,
input src1_fwd_data,
input src2_fwd_data
);
// source-side view
modport src (
output src1_fwd,
output src2_fwd,
output src1_fwd_data,
output src2_fwd_data
);
endinterface
`endif

42
rtl/interfaces/VX_forward_wb_inter.v Normal file
View file

@ -0,0 +1,42 @@
`include "VX_define.v"
`ifndef VX_FWD_WB
`define VX_FWD_WB
interface VX_forward_wb_inter ();
wire[4:0] dest;
wire[1:0] wb;
wire[`NT_M1:0][31:0] alu_result;
wire[`NT_M1:0][31:0] mem_data;
wire[31:0] PC_next;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input dest,
input wb,
input alu_result,
input mem_data,
input PC_next,
input warp_num
);
// source-side view
modport src (
output dest,
output wb,
output alu_result,
output mem_data,
output PC_next,
output warp_num
);
endinterface
`endif

6
rtl/interfaces/VX_inst_mem_wb_inter.v
View file

@ -11,8 +11,6 @@ interface VX_inst_mem_wb_inter ();
wire[`NT_M1:0][31:0] mem_result;
wire[4:0] rd;
wire[1:0] wb;
wire[4:0] rs1;
wire[4:0] rs2;
wire[31:0] PC_next;
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
@ -23,8 +21,6 @@ interface VX_inst_mem_wb_inter ();
input mem_result,
input rd,
input wb,
input rs1,
input rs2,
input PC_next,
input valid,
input warp_num
@ -37,8 +33,6 @@ interface VX_inst_mem_wb_inter ();
output mem_result,
output rd,
output wb,
output rs1,
output rs2,
output PC_next,
output valid,
output warp_num

45
rtl/interfaces/VX_mw_wb_inter.v Normal file
View file

@ -0,0 +1,45 @@
`include "VX_define.v"
`ifndef VX_MW_WB_INTER
`define VX_MW_WB_INTER
interface VX_mw_wb_inter ();
wire[`NT_M1:0][31:0] alu_result;
wire[`NT_M1:0][31:0] mem_result;
wire[4:0] rd;
wire[1:0] wb;
wire[31:0] PC_next;
wire[`NT_M1:0] valid;
wire [`NW_M1:0] warp_num;
// source-side view
modport snk (
input alu_result,
input mem_result,
input rd,
input wb,
input PC_next,
input valid,
input warp_num
);
// source-side view
modport src (
input alu_result,
input mem_result,
input rd,
input wb,
input PC_next,
input valid,
input warp_num
);
endinterface
`endif

BIN
rtl/obj_dir/VVortex
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6873
rtl/obj_dir/VVortex.cpp
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260
rtl/obj_dir/VVortex.h
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@ -17,7 +17,6 @@ class VVortex_VX_mem_req_inter;
class VVortex_VX_inst_mem_wb_inter;
class VVortex_VX_warp_ctl_inter;
class VVortex_VX_wb_inter;
class VVortex_VX_context_slave;
//----------
@ -35,13 +34,6 @@ VL_MODULE(VVortex) {
VVortex_VX_inst_mem_wb_inter* __PVT__Vortex__DOT__VX_mem_wb;
VVortex_VX_warp_ctl_inter* __PVT__Vortex__DOT__VX_warp_ctl;
VVortex_VX_wb_inter* __PVT__Vortex__DOT__VX_writeback_inter;
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one;
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one;
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one;
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one;
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one;
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one;
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one;
// PORTS
// The application code writes and reads these signals to
@ -67,8 +59,6 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__decode_branch_stall,0,0);
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0);
VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_num,3,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_state,3,0);
@ -121,16 +111,33 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__real_wspawn,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__real_isclone,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
};
struct {
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_memory__DOT__temp_branch_dir,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__out_src1_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__out_src2_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd,0,0);
};
struct {
VL_SIG16(Vortex__DOT__vx_decode__DOT__alu_tempp,11,0);
VL_SIGW(Vortex__DOT__vx_csr_handler__DOT__csr,12299,0,385);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
VL_SIG(Vortex__DOT__memory_branch_dest,31,0);
VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0);
@ -162,14 +169,60 @@ VL_MODULE(VVortex) {
VL_SIGW(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
};
struct {
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_d_e_reg__DOT__d_e_reg__DOT__value,489,0,16);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIGW(Vortex__DOT__vx_e_m_reg__DOT__f_d_reg__DOT__value,719,0,23);
VL_SIGW(Vortex__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value,312,0,10);
VL_SIGW(Vortex__DOT__vx_e_m_reg__DOT__f_d_reg__DOT__value,463,0,15);
VL_SIGW(Vortex__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value,302,0,10);
VL_SIGW(Vortex__DOT__vx_writeback__DOT__out_pc_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__out_src1_fwd_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__out_src2_fwd_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next,127,0,4);
@ -194,65 +247,135 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__VX_Warp__DOT__valid[4],0,0);
};
struct {
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
};
struct {
VL_SIG8(Vortex__DOT__vx_decode__DOT__in_valid[4],0,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[1025],11,0);
};
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vdly__Vortex__DOT__vx_fetch__DOT__warp_num,3,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0);
VL_SIGW(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT____Vcellout__vx_execute__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data,127,0,4);
VL_SIGW(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data,127,0,4);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIGW(Vortex__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in,489,0,16);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIGW(Vortex__DOT__vx_e_m_reg__DOT____Vcellinp__f_d_reg__in,719,0,23);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[4],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[4],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[4],31,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__0__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__0__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__1__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__1__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__2__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__2__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__3__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__3__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__4__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__4__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__5__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__5__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__6__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__6__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__7__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__7__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
// Anonymous structures to workaround compiler member-count bugs
struct {
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vdly__Vortex__DOT__vx_fetch__DOT__warp_num,3,0);
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VL_SIG8(__Vclklast__TOP__reset,0,0);
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VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__genblk2__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
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VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
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};
struct {
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VL_SIG(Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
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VL_SIG(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
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VL_SIGW(Vortex__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in,489,0,16);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIGW(Vortex__DOT__vx_e_m_reg__DOT____Vcellinp__f_d_reg__in,463,0,15);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[4],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[4],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[4],31,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__0__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__0__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__1__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__1__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__2__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__2__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__3__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__3__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__4__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__4__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__5__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__5__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__6__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__6__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__7__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__7__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
};
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
// INTERNAL VARIABLES
@ -287,9 +410,8 @@ VL_MODULE(VVortex) {
private:
static QData _change_request(VVortex__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__10(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__11(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__7(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__8(VVortex__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
@ -302,13 +424,11 @@ VL_MODULE(VVortex) {
static void _eval_initial(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _eval_settle(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _initial__TOP__1(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__6(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__8(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__9(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__2(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _settle__TOP__3(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

3031
rtl/obj_dir/VVortex_VX_context_slave.cpp
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99
rtl/obj_dir/VVortex_VX_context_slave.h
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@ -1,99 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_context_slave_H_
#define _VVortex_VX_context_slave_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_context_slave) {
public:
// PORTS
// Begin mtask footprint all:
VL_IN8(clk,0,0);
VL_IN8(in_warp,0,0);
VL_IN8(in_wb_warp,0,0);
VL_IN8(in_valid,3,0);
VL_IN8(in_write_register,0,0);
VL_IN8(in_rd,4,0);
VL_IN8(in_src1,4,0);
VL_IN8(in_src2,4,0);
VL_IN8(in_is_clone,0,0);
VL_IN8(in_is_jal,0,0);
VL_IN8(in_src1_fwd,0,0);
VL_IN8(in_src2_fwd,0,0);
VL_IN8(in_wspawn,0,0);
VL_OUT8(out_clone_stall,0,0);
VL_INW(in_write_data,127,0,4);
VL_IN(in_curr_PC,31,0);
VL_INW(in_src1_fwd_data,127,0,4);
VL_INW(in_src2_fwd_data,127,0,4);
VL_INW(in_wspawn_regs,1023,0,32);
VL_OUTW(out_a_reg_data,127,0,4);
VL_OUTW(out_b_reg_data,127,0,4);
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIG8(__PVT__clone_state_stall,5,0);
VL_SIG8(__PVT__wspawn_state_stall,5,0);
VL_SIGW(__PVT__rd1_register,127,0,4);
VL_SIGW(__PVT__rd2_register,127,0,4);
VL_SIGW(__PVT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
// LOCAL VARIABLES
// Begin mtask footprint all:
VL_SIG8(__Vdly__clone_state_stall,5,0);
VL_SIG8(__Vdly__wspawn_state_stall,5,0);
VL_SIG(__Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(__Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_context_slave); ///< Copying not allowed
public:
VVortex_VX_context_slave(const char* name="TOP");
~VVortex_VX_context_slave();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
void _combo__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__29(VVortex__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
void _initial__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__1(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__15(VVortex__Syms* __restrict vlSymsp);
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__22(VVortex__Syms* __restrict vlSymsp);
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__16(VVortex__Syms* __restrict vlSymsp);
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__17(VVortex__Syms* __restrict vlSymsp);
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__18(VVortex__Syms* __restrict vlSymsp);
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__19(VVortex__Syms* __restrict vlSymsp);
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__20(VVortex__Syms* __restrict vlSymsp);
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__21(VVortex__Syms* __restrict vlSymsp);
void _settle__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__8(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

BIN
rtl/obj_dir/VVortex__ALL.a
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1
rtl/obj_dir/VVortex__ALLcls.cpp
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@ -8,4 +8,3 @@
#include "VVortex_VX_inst_mem_wb_inter.cpp"
#include "VVortex_VX_warp_ctl_inter.cpp"
#include "VVortex_VX_wb_inter.cpp"
#include "VVortex_VX_context_slave.cpp"

5
rtl/obj_dir/VVortex__ALLcls.d
View file

@ -4,8 +4,7 @@ VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
VVortex___024unit.h VVortex_VX_inst_meta_inter.h \
VVortex_VX_frE_to_bckE_req_inter.h VVortex_VX_mem_req_inter.h \
VVortex_VX_inst_mem_wb_inter.h VVortex_VX_warp_ctl_inter.h \
VVortex_VX_wb_inter.h VVortex_VX_context_slave.h VVortex___024unit.cpp \
VVortex_VX_wb_inter.h VVortex___024unit.cpp \
VVortex_VX_inst_meta_inter.cpp VVortex_VX_frE_to_bckE_req_inter.cpp \
VVortex_VX_mem_req_inter.cpp VVortex_VX_inst_mem_wb_inter.cpp \
VVortex_VX_warp_ctl_inter.cpp VVortex_VX_wb_inter.cpp \
VVortex_VX_context_slave.cpp
VVortex_VX_warp_ctl_inter.cpp VVortex_VX_wb_inter.cpp

BIN
rtl/obj_dir/VVortex__ALLcls.o
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2
rtl/obj_dir/VVortex__ALLsup.d
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@ -4,4 +4,4 @@ VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
VVortex___024unit.h VVortex_VX_inst_meta_inter.h \
VVortex_VX_frE_to_bckE_req_inter.h VVortex_VX_mem_req_inter.h \
VVortex_VX_inst_mem_wb_inter.h VVortex_VX_warp_ctl_inter.h \
VVortex_VX_wb_inter.h VVortex_VX_context_slave.h
VVortex_VX_wb_inter.h

BIN
rtl/obj_dir/VVortex__ALLsup.o
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22
rtl/obj_dir/VVortex__Syms.cpp
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@ -10,7 +10,6 @@
#include "VVortex_VX_inst_mem_wb_inter.h"
#include "VVortex_VX_warp_ctl_inter.h"
#include "VVortex_VX_wb_inter.h"
#include "VVortex_VX_context_slave.h"
// FUNCTIONS
VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
@ -24,13 +23,6 @@ VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
, TOP__Vortex__DOT__VX_warp_ctl (Verilated::catName(topp->name(),"Vortex.VX_warp_ctl"))
, TOP__Vortex__DOT__VX_writeback_inter (Verilated::catName(topp->name(),"Vortex.VX_writeback_inter"))
, TOP__Vortex__DOT__fe_inst_meta_fd (Verilated::catName(topp->name(),"Vortex.fe_inst_meta_fd"))
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[1].VX_Context_one"))
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[2].VX_Context_one"))
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[3].VX_Context_one"))
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[4].VX_Context_one"))
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[5].VX_Context_one"))
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[6].VX_Context_one"))
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[7].VX_Context_one"))
{
// Pointer to top level
TOPp = topp;
@ -41,13 +33,6 @@ VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
TOPp->__PVT__Vortex__DOT__VX_warp_ctl = &TOP__Vortex__DOT__VX_warp_ctl;
TOPp->__PVT__Vortex__DOT__VX_writeback_inter = &TOP__Vortex__DOT__VX_writeback_inter;
TOPp->__PVT__Vortex__DOT__fe_inst_meta_fd = &TOP__Vortex__DOT__fe_inst_meta_fd;
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one;
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one;
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one;
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one;
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one;
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one;
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one;
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
TOP__Vortex__DOT__VX_exe_mem_req.__Vconfigure(this, true);
@ -56,11 +41,4 @@ VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
TOP__Vortex__DOT__VX_warp_ctl.__Vconfigure(this, true);
TOP__Vortex__DOT__VX_writeback_inter.__Vconfigure(this, true);
TOP__Vortex__DOT__fe_inst_meta_fd.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one.__Vconfigure(this, false);
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one.__Vconfigure(this, false);
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one.__Vconfigure(this, false);
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one.__Vconfigure(this, false);
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one.__Vconfigure(this, false);
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one.__Vconfigure(this, false);
}

8
rtl/obj_dir/VVortex__Syms.h
View file

@ -18,7 +18,6 @@
#include "VVortex_VX_inst_mem_wb_inter.h"
#include "VVortex_VX_warp_ctl_inter.h"
#include "VVortex_VX_wb_inter.h"
#include "VVortex_VX_context_slave.h"
// SYMS CLASS
class VVortex__Syms : public VerilatedSyms {
@ -36,13 +35,6 @@ class VVortex__Syms : public VerilatedSyms {
VVortex_VX_warp_ctl_inter TOP__Vortex__DOT__VX_warp_ctl;
VVortex_VX_wb_inter TOP__Vortex__DOT__VX_writeback_inter;
VVortex_VX_inst_meta_inter TOP__Vortex__DOT__fe_inst_meta_fd;
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one;
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one;
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one;
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one;
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one;
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one;
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one;
// CREATORS
VVortex__Syms(VVortex* topp, const char* namep);

2
rtl/obj_dir/VVortex__ver.d
View file

@ -1 +1 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_context_slave.cpp obj_dir/VVortex_VX_context_slave.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex___024unit.cpp obj_dir/VVortex___024unit.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_generic_register.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v buses.vh interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex___024unit.cpp obj_dir/VVortex___024unit.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_generic_register.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v buses.vh interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.sv interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v

78
rtl/obj_dir/VVortex__verFiles.dat
View file

@ -1,55 +1,59 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--compiler gcc -Wall -cc Vortex.v -Iinterfaces/ --exe test_bench.cpp -CFLAGS -std=c++11"
C "--compiler gcc -Wall -cc Vortex.v -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3"
S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin"
S 2785 1565236 1567474434 0 1567474434 0 "VX_alu.v"
S 3553 1572595 1567702966 0 1567702966 0 "VX_context.v"
S 4995 1572594 1567702948 0 1567702948 0 "VX_context_slave.v"
S 1699 1565239 1567474434 0 1567474434 0 "VX_csr_handler.v"
S 6179 1572602 1567698562 0 1567698562 0 "VX_d_e_reg.v"
S 18559 1572589 1567703138 0 1567703138 0 "VX_decode.v"
S 1563 1573428 1567973468 0 1567973468 0 "VX_csr_handler.v"
S 17085 1574349 1567973680 0 1567973680 0 "VX_decode.v"
S 1676 1565244 1567474434 0 1567474434 0 "VX_define.v"
S 1782 1572383 1567725862 0 1567725862 0 "VX_e_m_reg.v"
S 3753 1572381 1567704198 0 1567704198 0 "VX_execute.v"
S 776 1572788 1567631138 0 1567631138 0 "VX_f_d_reg.v"
S 3835 1573272 1567973378 0 1567973378 0 "VX_execute.v"
S 6600 1571625 1567568548 0 1567568548 0 "VX_fetch.v"
S 6318 1572489 1567703920 0 1567703920 0 "VX_forwarding.v"
S 6148 1573159 1567972050 0 1567972050 0 "VX_forwarding.v"
S 399 1565278 1567537322 0 1567537322 0 "VX_generic_register.v"
S 1038 1572397 1567725842 0 1567725842 0 "VX_m_w_reg.v"
S 2441 1572393 1567725910 0 1567725910 0 "VX_memory.v"
S 2697 1573280 1567972222 0 1567972222 0 "VX_memory.v"
S 1249 1572596 1567702894 0 1567702894 0 "VX_register_file.v"
S 1655 1572598 1567702916 0 1567702916 0 "VX_register_file_master_slave.v"
S 1599 1572597 1567702888 0 1567702888 0 "VX_register_file_slave.v"
S 1915 1565256 1567474434 0 1567474434 0 "VX_warp.v"
S 1368 1572593 1567702438 0 1567702438 0 "VX_writeback.v"
S 9956 1572384 1567726302 0 1567726302 0 "Vortex.v"
S 1597 1573170 1567969318 0 1567969318 0 "VX_writeback.v"
S 7106 1573153 1567973392 0 1567973392 0 "Vortex.v"
S 1356 1571954 1567552292 0 1567552292 0 "buses.vh"
S 528 1573270 1567972030 0 1567972030 0 "interfaces//VX_forward_exe_inter.v"
S 610 1573271 1567971856 0 1567971856 0 "interfaces//VX_forward_mem_inter.sv"
S 377 1573266 1567971920 0 1567971920 0 "interfaces//VX_forward_reqeust_inter.v"
S 520 1573373 1567970758 0 1567970758 0 "interfaces//VX_forward_response_inter.v"
S 595 1573167 1567968126 0 1567968126 0 "interfaces//VX_forward_wb_inter.v"
S 1689 1571958 1567565366 0 1567565366 0 "interfaces//VX_frE_to_bckE_req_inter.v"
S 789 1572399 1567724612 0 1567724612 0 "interfaces//VX_inst_mem_wb_inter.v"
S 679 1573336 1567972210 0 1567972210 0 "interfaces//VX_inst_mem_wb_inter.v"
S 444 1571666 1567552516 0 1567552516 0 "interfaces//VX_inst_meta_inter.v"
S 995 1572568 1567701364 0 1567701364 0 "interfaces//VX_mem_req_inter.v"
S 654 1573355 1567969270 0 1567969270 0 "interfaces//VX_mw_wb_inter.v"
S 603 1571976 1567568452 0 1567568452 0 "interfaces//VX_warp_ctl_inter.v"
S 450 1572588 1567702406 0 1567702406 0 "interfaces//VX_wb_inter.v"
T 611319 1572409 1567726304 0 1567726304 0 "obj_dir/VVortex.cpp"
T 20930 1572391 1567726304 0 1567726304 0 "obj_dir/VVortex.h"
T 1791 1572466 1567726304 0 1567726304 0 "obj_dir/VVortex.mk"
T 218860 1572451 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_context_slave.cpp"
T 4606 1572450 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_context_slave.h"
T 1131 1572441 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1208 1572440 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 882 1572445 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 1572444 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 863 1572402 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 1572401 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 883 1572443 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 1572442 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 900 1572447 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 1572446 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 819 1572449 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 1572448 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_wb_inter.h"
T 5392 1572390 1567726304 0 1567726304 0 "obj_dir/VVortex__Syms.cpp"
T 2283 1572389 1567726304 0 1567726304 0 "obj_dir/VVortex__Syms.h"
T 754 1572398 1567726304 0 1567726304 0 "obj_dir/VVortex___024unit.cpp"
T 873 1572396 1567726304 0 1567726304 0 "obj_dir/VVortex___024unit.h"
T 1324 1572474 1567726304 0 1567726304 0 "obj_dir/VVortex__ver.d"
T 0 0 1567726304 0 1567726304 0 "obj_dir/VVortex__verFiles.dat"
T 1472 1572465 1567726304 0 1567726304 0 "obj_dir/VVortex_classes.mk"
T 1073829 1576136 1567974076 0 1567974076 0 "obj_dir/VVortex.cpp"
T 38817 1576133 1567974076 0 1567974076 0 "obj_dir/VVortex.h"
T 1791 1576224 1567974076 0 1567974076 0 "obj_dir/VVortex.mk"
T 1131 1576214 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1208 1576213 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 882 1576218 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 1576217 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 863 1576212 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 1576211 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 883 1576216 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 1576215 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 900 1576220 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 1576219 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 819 1576222 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 1576221 1567974076 0 1567974076 0 "obj_dir/VVortex_VX_wb_inter.h"
T 2254 1576092 1567974076 0 1567974076 0 "obj_dir/VVortex__Syms.cpp"
T 1447 1576091 1567974076 0 1567974076 0 "obj_dir/VVortex__Syms.h"
T 754 1576130 1567974076 0 1567974076 0 "obj_dir/VVortex___024unit.cpp"
T 873 1576095 1567974076 0 1567974076 0 "obj_dir/VVortex___024unit.h"
T 1509 1576228 1567974076 0 1567974076 0 "obj_dir/VVortex__ver.d"
T 0 0 1567974076 0 1567974076 0 "obj_dir/VVortex__verFiles.dat"
T 1444 1576223 1567974076 0 1567974076 0 "obj_dir/VVortex_classes.mk"
S 6179 1572602 1567698562 0 1567698562 0 "pipe_regs//VX_d_e_reg.v"
S 1538 1573254 1567973402 0 1567973402 0 "pipe_regs//VX_e_m_reg.v"
S 776 1572788 1567631138 0 1567631138 0 "pipe_regs//VX_f_d_reg.v"
S 688 1573273 1567972184 0 1567972184 0 "pipe_regs//VX_m_w_reg.v"

1
rtl/obj_dir/VVortex_classes.mk
View file

@ -25,7 +25,6 @@ VM_CLASSES_FAST += \
VVortex_VX_inst_mem_wb_inter \
VVortex_VX_warp_ctl_inter \
VVortex_VX_wb_inter \
VVortex_VX_context_slave \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \

BIN
rtl/obj_dir/test_bench.o
View file

Binary file not shown.

0
rtl/VX_d_e_reg.v → rtl/pipe_regs/VX_d_e_reg.v
View file

45
rtl/pipe_regs/VX_e_m_reg.v Normal file
View file

@ -0,0 +1,45 @@
`include "VX_define.v"
module VX_e_m_reg (
input wire clk,
input wire reset,
input wire in_freeze,
input wire[11:0] in_csr_address,
input wire in_is_csr,
input wire[31:0] in_csr_result,
input wire in_jal,
input wire[31:0] in_jal_dest,
VX_mem_req_inter VX_exe_mem_req,
VX_mem_req_inter VX_mem_req,
output wire[11:0] out_csr_address,
output wire out_is_csr,
output wire[31:0] out_csr_result,
output wire out_jal,
output wire[31:0] out_jal_dest
);
wire flush = 0;
wire stall = in_freeze;
VX_generic_register #(.N(464)) f_d_reg
(
.clk (clk),
.reset(reset),
.stall(stall),
.flush(flush),
.in ({in_csr_address , in_is_csr , in_csr_result , in_jal , in_jal_dest , VX_exe_mem_req.alu_result, VX_exe_mem_req.mem_read, VX_exe_mem_req.mem_write, VX_exe_mem_req.rd, VX_exe_mem_req.wb, VX_exe_mem_req.rs1, VX_exe_mem_req.rs2, VX_exe_mem_req.rd2, VX_exe_mem_req.PC_next, VX_exe_mem_req.curr_PC, VX_exe_mem_req.branch_offset, VX_exe_mem_req.branch_type, VX_exe_mem_req.valid, VX_exe_mem_req.warp_num}),
.out ({out_csr_address, out_is_csr, out_csr_result, out_jal, out_jal_dest, VX_mem_req.alu_result , VX_mem_req.mem_read , VX_mem_req.mem_write , VX_mem_req.rd , VX_mem_req.wb , VX_mem_req.rs1 , VX_mem_req.rs2 , VX_mem_req.rd2 , VX_mem_req.PC_next , VX_mem_req.curr_PC , VX_mem_req.branch_offset , VX_mem_req.branch_type , VX_mem_req.valid , VX_mem_req.warp_num})
);
endmodule // VX_e_m_reg

0
rtl/VX_f_d_reg.v → rtl/pipe_regs/VX_f_d_reg.v
View file

33
rtl/pipe_regs/VX_m_w_reg.v Normal file
View file

@ -0,0 +1,33 @@
`include "VX_define.v"
module VX_m_w_reg (
input wire clk,
input wire reset,
input wire in_freeze,
VX_inst_mem_wb_inter VX_mem_wb,
VX_mw_wb_inter VX_mw_wb
);
wire flush = 0;
wire stall = in_freeze;
VX_generic_register #(.N(303)) m_w_reg
(
.clk (clk),
.reset(reset),
.stall(stall),
.flush(flush),
.in ({VX_mem_wb.alu_result, VX_mem_wb.mem_result, VX_mem_wb.rd, VX_mem_wb.wb, VX_mem_wb.PC_next, VX_mem_wb.valid, VX_mem_wb.warp_num}),
.out ({VX_mw_wb.alu_result , VX_mw_wb.mem_result , VX_mw_wb.rd , VX_mw_wb.wb , VX_mw_wb.PC_next , VX_mw_wb.valid , VX_mw_wb.warp_num })
);
endmodule // VX_m_w_reg

2
rtl/results.txt
View file

@ -3,5 +3,5 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01056
# time to simulate: 2.19224e-314 milliseconds
# time to simulate: 2.18896e-314 milliseconds
# GRADE: Failed on test: 4294967295