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https://github.com/vortexgpgpu/vortex.git
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331 lines
11 KiB
C++
331 lines
11 KiB
C++
/*******************************************************************************
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HARPtools by Chad D. Kersey, Summer 2011
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*******************************************************************************/
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#include <iostream>
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#include <string>
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#include <stdlib.h>
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#include <string.h>
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#include <iomanip>
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#include <vector>
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#include "include/debug.h"
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#include "include/types.h"
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#include "include/util.h"
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#include "include/enc.h"
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#include "include/archdef.h"
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#include "include/instruction.h"
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using namespace std;
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using namespace Harp;
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// ByteDecoder::ByteDecoder(const ArchDef &ad) {
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// wordSize = ad.getWordSize();
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// }
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static void decodeError(string msg) {
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cout << "Instruction decoder error: " << msg << '\n';
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exit(1);
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}
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static unsigned ceilLog2(RegNum x) {
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unsigned z = 0;
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bool nonZeroInnerValues(false);
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if (x == 0) return 0;
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while (x != 1) {
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z++;
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if (x&1) nonZeroInnerValues = true;
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x >>= 1;
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}
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if (nonZeroInnerValues) z++;
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return z;
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}
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WordDecoder::WordDecoder(const ArchDef &arch) {
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inst_s = arch.getWordSize() * 8;
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opcode_s = 7;
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reg_s = 5;
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func3_s = 3;
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mop_s = 3;
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vmask_s = 1;
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shift_opcode = 0;
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shift_rd = opcode_s;
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shift_func3 = opcode_s + reg_s;
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shift_rs1 = opcode_s + reg_s + func3_s;
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shift_rs2 = opcode_s + reg_s + func3_s + reg_s;
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shift_func7 = opcode_s + reg_s + func3_s + reg_s + reg_s;
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shift_j_u_immed = opcode_s + reg_s;
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shift_s_b_immed = opcode_s + reg_s + func3_s + reg_s + reg_s;
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shift_i_immed = opcode_s + reg_s + func3_s + reg_s;
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shift_vset_immed = opcode_s + reg_s + func3_s + reg_s;
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shift_vmask = opcode_s + reg_s + func3_s + reg_s + reg_s;
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shift_vmop = opcode_s + reg_s + func3_s + reg_s + reg_s + vmask_s;
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shift_vnf = opcode_s + reg_s + func3_s + reg_s + reg_s + vmask_s + mop_s;
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shift_func6 = opcode_s + reg_s + func3_s + reg_s + reg_s + 1;
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shift_vset = opcode_s + reg_s + func3_s + reg_s + reg_s + 6;
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reg_mask = 0x1f;
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func3_mask = 0x7;
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func7_mask = 0x7f;
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opcode_mask = 0x7f;
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i_immed_mask = 0xfff;
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s_immed_mask = 0xfff;
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b_immed_mask = 0x1fff;
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u_immed_mask = 0xfffff;
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j_immed_mask = 0xfffff;
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v_immed_mask = 0x7ff;
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func6_mask = 0x3f;
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}
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static Word signExt(Word w, Size bit, Word mask) {
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if (w>>(bit-1)) w |= ~mask;
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return w;
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}
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Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_inst_t * trace_inst) {
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Word code(readWord(v, idx, inst_s/8));
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// std::cout << "code: " << (int) code << " v: " << v << " indx: " << idx << "\n";
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Instruction &inst = * new Instruction();
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// bool predicated = (code>>(n-1));
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bool predicated = false;
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if (predicated) { inst.setPred((code>>(inst_s-p-1))&pMask); }
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// printf("CUrrent CODE: %x\n", code);
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D(3, "Curr Code: " << hex << code << dec);
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Opcode op = (Opcode)((code>>shift_opcode)&opcode_mask);
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// std::cout << "opcode: " << op << "\n";
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inst.setOpcode(op);
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bool usedImm(false);
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Word imeed, dest_bits, imm_bits, bit_11, bits_4_1, bit_10_5,
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bit_12, bits_19_12, bits_10_1, bit_20, unordered, func3;
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// std::cout << "op: " << std::hex << op << " what " << instTable[op].iType << "\n";
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switch(instTable[op].iType)
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{
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case InstType::N_TYPE:
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break;
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case InstType::R_TYPE:
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inst.setPred((code>>shift_rs1) & reg_mask);
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inst.setDestReg((code>>shift_rd) & reg_mask);
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inst.setSrcReg((code>>shift_rs1) & reg_mask);
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inst.setSrcReg((code>>shift_rs2) & reg_mask);
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inst.setFunc3 ((code>>shift_func3) & func3_mask);
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inst.setFunc7 ((code>>shift_func7) & func7_mask);
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
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trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
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trace_inst->rd = ((code>>shift_rd) & reg_mask);
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break;
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case InstType::I_TYPE:
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inst.setDestReg((code>>shift_rd) & reg_mask);
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inst.setSrcReg((code>>shift_rs1) & reg_mask);
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inst.setFunc7 ((code>>shift_func7) & func7_mask);
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func3 = (code>>shift_func3) & func3_mask;
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inst.setFunc3 (func3);
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if ((func3 == 5) && (op != L_INST))
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{
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// std::cout << "func7: " << func7 << "\n";
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inst.setSrcImm(signExt(((code>>shift_rs2)®_mask), 5, reg_mask));
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}
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else
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{
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inst.setSrcImm(signExt(code>>shift_i_immed, 12, i_immed_mask));
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}
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usedImm = true;
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
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trace_inst->rd = ((code>>shift_rd) & reg_mask);
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break;
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case InstType::S_TYPE:
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// std::cout << "************STORE\n";
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inst.setSrcReg((code>>shift_rs1) & reg_mask);
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inst.setSrcReg((code>>shift_rs2) & reg_mask);
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inst.setFunc3 ((code>>shift_func3) & func3_mask);
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dest_bits = (code>>shift_rd) & reg_mask;
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imm_bits = (code>>shift_s_b_immed & func7_mask);
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imeed = (imm_bits << reg_s) | dest_bits;
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// std::cout << "ENC: store imeed: " << imeed << "\n";
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inst.setSrcImm(signExt(imeed, 12, s_immed_mask));
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usedImm = true;
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
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trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
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break;
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case InstType::B_TYPE:
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inst.setSrcReg((code>>shift_rs1) & reg_mask);
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inst.setSrcReg((code>>shift_rs2) & reg_mask);
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inst.setFunc3 ((code>>shift_func3) & func3_mask);
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dest_bits = (code>>shift_rd) & reg_mask;
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imm_bits = (code>>shift_s_b_immed & func7_mask);
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bit_11 = dest_bits & 0x1;
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bits_4_1 = dest_bits >> 1;
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bit_10_5 = imm_bits & 0x3f;
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bit_12 = imm_bits >> 6;
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imeed = 0 | (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
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inst.setSrcImm(signExt(imeed, 13, b_immed_mask));
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usedImm = true;
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
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trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
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break;
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case InstType::U_TYPE:
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inst.setDestReg((code>>shift_rd) & reg_mask);
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inst.setSrcImm(signExt(code>>shift_j_u_immed, 20, u_immed_mask));
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usedImm = true;
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trace_inst->valid_inst = true;
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trace_inst->rd = ((code>>shift_rd) & reg_mask);
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break;
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case InstType::J_TYPE:
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inst.setDestReg((code>>shift_rd) & reg_mask);
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// [20 | 10:1 | 11 | 19:12]
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unordered = code>>shift_j_u_immed;
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bits_19_12 = unordered & 0xff;
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bit_11 = (unordered>>8) & 0x1;
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bits_10_1 = (unordered >> 9) & 0x3ff;
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bit_20 = (unordered>>19) & 0x1;
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imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
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if (bit_20)
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{
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imeed |= ~j_immed_mask;
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}
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// inst.setSrcImm(signExt(imeed, 20, j_immed_mask));
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inst.setSrcImm(imeed);
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usedImm = true;
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trace_inst->valid_inst = true;
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trace_inst->rd = ((code>>shift_rd) & reg_mask);
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break;
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case InstType::V_TYPE:
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D(3, "Entered here: instr type = vector" << op);
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switch(op) {
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case Opcode::VSET_ARITH: //TODO: arithmetic ops
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inst.setDestReg((code>>shift_rd) & reg_mask);
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inst.setSrcReg((code>>shift_rs1) & reg_mask);
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func3 = (code>>shift_func3) & func3_mask;
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inst.setFunc3 (func3);
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D(3, "Entered here: instr type = vector");
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if(func3 == 7) {
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D(3, "Entered here: imm instr");
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inst.setVsetImm(!(code>>shift_vset));
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if(inst.getVsetImm()) {
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Word immed = (code>>shift_rs2) & v_immed_mask;
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D(3, "immed" << immed);
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inst.setSrcImm(immed); //TODO
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inst.setvlmul(immed & 0x3);
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D(3, "lmul " << (immed & 0x3));
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inst.setvediv((immed>>4) & 0x3);
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D(3, "ediv " << ((immed>>4) & 0x3));
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inst.setvsew((immed>>2) & 0x3);
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D(3, "sew " << ((immed>>2) & 0x3));
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}
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else {
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inst.setSrcReg((code>>shift_rs2) & reg_mask);
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trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
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}
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
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trace_inst->rd = ((code>>shift_rd) & reg_mask);
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} else {
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inst.setSrcReg((code>>shift_rs2) & reg_mask);
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inst.setVmask((code>>shift_vmask) & 0x1);
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inst.setFunc6((code>>shift_func6) & func6_mask);
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
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trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
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trace_inst->rd = ((code>>shift_rd) & reg_mask);
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}
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break;
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case Opcode::VL:
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D(3, "vector load instr");
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inst.setDestReg((code>>shift_rd) & reg_mask);
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inst.setSrcReg((code>>shift_rs1) & reg_mask);
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inst.setVlsWidth((code>>shift_func3) & func3_mask);
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inst.setSrcReg((code>>shift_rs2) & reg_mask);
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inst.setVmask((code>>shift_vmask));
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inst.setVmop((code>>shift_vmop) & func3_mask);
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inst.setVnf((code>>shift_vnf) & func3_mask);
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
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trace_inst->vd = ((code>>shift_rd) & reg_mask);
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//trace_inst->vs2 = ((code>>shift_rs2) & reg_mask);
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break;
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case Opcode::VS:
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inst.setVs3((code>>shift_rd) & reg_mask);
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inst.setSrcReg((code>>shift_rs1) & reg_mask);
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inst.setVlsWidth((code>>shift_func3) & func3_mask);
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inst.setSrcReg((code>>shift_rs2) & reg_mask);
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inst.setVmask((code>>shift_vmask));
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inst.setVmop((code>>shift_vmop) & func3_mask);
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inst.setVnf((code>>shift_vnf) & func3_mask);
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
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//trace_inst->vd = ((code>>shift_rd) & reg_mask);
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trace_inst->vs1 = ((code>>shift_rd) & reg_mask); //vs3
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break;
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}
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break;
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default:
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cout << "Unrecognized argument class in word decoder.\n";
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exit(1);
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}
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if (haveRefs && usedImm && refMap.find(idx-n/8) != refMap.end()) {
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Ref *srcRef = refMap[idx-n/8];
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/* Create a new ref tied to this instruction. */
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// Ref *r = new SimpleRef(srcRef->name, *(Addr*)inst.setSrcImm(),
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// inst.hasRelImm());
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// inst.setImmRef(*r);
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}
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D(2, "Decoded 0x" << hex << code << " into: " << inst << '\n');
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return &inst;
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}
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