15 commits

Author	SHA1	Message	Date
Blizzard Finnegan	09a7f5fe99	Update docs from RIT lab computers	2024-11-26 10:12:59 -05:00
Blizzard Finnegan	18d2f96f6c	Update from windows	2024-11-11 14:40:22 -05:00
Blizzard Finnegan	67367e707f	Bus structure notes	2024-11-04 09:40:34 -05:00
Blizzard Finnegan	3987e87eb1	Init labs 4-6	2024-11-01 10:29:11 -04:00
Blizzard Finnegan	b0b00515e7	Lab4 Prelab complete	2024-10-29 14:49:39 -04:00
Blizzard Finnegan	99d77543d9	Start Modelsim analysis ... Testbench not fully built, but all code now compiles.	2024-10-29 11:05:24 -04:00
Blizzard Finnegan	1a28126d8d	Rewrite base project ... No Testbench written yet	2024-10-28 21:44:29 -04:00
Blizzard Finnegan	35ffd212f4	Start overhauling project ... Lack of documentation in previous iteration led to repeat code in several places.	2024-10-28 17:55:28 -04:00
Blizzard Finnegan	ec6ef2643c	Fix to compile	2024-10-18 15:18:48 -04:00
Blizzard Finnegan	0da40b710a	Start working with lab 4 based on drawings	2024-10-11 15:48:02 -04:00
Blizzard Finnegan	bcb9dbc5ec	Start lab4	2024-10-06 20:56:04 -04:00
Blizzard Finnegan	91bb0bda7c	Add lab 3	2024-10-06 20:09:54 -04:00
Blizzard Finnegan	66ad168c47	Finish lab 2	2024-09-13 09:01:00 -04:00
Blizzard Finnegan	60c3b537bf	Add demo2 and lab1	2024-09-06 11:32:14 -04:00
Blizzard Finnegan	030cf76853	Finish lab demo	2024-08-29 14:57:38 -04:00