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Author	SHA1	Message	Date
Colin Riley	4b16f9bf6f	RPU 1.0 Updated ISA support to RV32IMZcsr - Passes riscv-compliance. Integer divide/rem in 34 cycles. Integer multiply in 2 cycles (when using xilinx dsp blocks!) Saved multiple cycles from fetch/memory load stages by short-cutting the start of memory requests. Compliant misaligned exceptions for jumps,loads and stores. Addrs starting 0xFxxxxxxx ignore alignment requests (assumes mmio space). Added CSRs for riscv-compliance requirements. Source ran through a formatter for ease of use.	2020-09-11 00:06:01 +01:00
Colin Riley	96b86f1dc2	Basic core execution simulator testbench. No memory subsystem, so will only execute from fixed array of instructions - but easy to use in the sim.	2018-11-16 22:43:47 +00:00
Colin Riley	439781c194	Initial commit. Tested on ArtyS7-RPU-SoC and passes SD bootloader and DDR3 memory testing.	2018-09-11 23:53:41 +01:00

Author

SHA1

Message

Date

Colin Riley

4b16f9bf6f

RPU 1.0

Updated ISA support to RV32IMZcsr - Passes riscv-compliance.
Integer divide/rem in 34 cycles.
Integer multiply in 2 cycles (when using xilinx dsp blocks!)
Saved multiple cycles from fetch/memory load stages by short-cutting the start of memory requests.
Compliant misaligned exceptions for jumps,loads and stores. Addrs starting 0xFxxxxxxx ignore alignment requests (assumes mmio space).
Added CSRs for riscv-compliance requirements.
Source ran through a formatter for ease of use.

2020-09-11 00:06:01 +01:00

Colin Riley

96b86f1dc2

Basic core execution simulator testbench. No memory subsystem, so will only execute from fixed array of instructions - but easy to use in the sim.

2018-11-16 22:43:47 +00:00

Colin Riley

439781c194

Initial commit. Tested on ArtyS7-RPU-SoC and passes SD bootloader and DDR3 memory testing.

2018-09-11 23:53:41 +01:00

3 commits