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  • 200284e361 Clarify DooM timedemo score CPU speed master v1.0.0 Colin Riley 2020-09-12 00:23:50 +01:00
  • 4b16f9bf6f RPU 1.0 Updated ISA support to RV32IMZcsr - Passes riscv-compliance. Integer divide/rem in 34 cycles. Integer multiply in 2 cycles (when using xilinx dsp blocks!) Saved multiple cycles from fetch/memory load stages by short-cutting the start of memory requests. Compliant misaligned exceptions for jumps,loads and stores. Addrs starting 0xFxxxxxxx ignore alignment requests (assumes mmio space). Added CSRs for riscv-compliance requirements. Source ran through a formatter for ease of use. Colin Riley 2020-09-11 00:06:01 +01:00
  • 47a0058836 Update readme to reflect latest status Colin Riley 2020-05-17 23:50:59 +01:00
  • 8803d1392d Core can now boot Zephyr RTOS Added Interrupt handling support: - Int enable masks - external interrupt - interrupt enable CSR - illegal instruction - system call instruction - breakpoints - interrupt CSR manipulation - correct nextPC resume/branch target selection Added debug data for CPU trace support Added vexrisc IRQ csrs for testing with 3rd party sw Added LINT unit locally arbitrates IRQs into priorities FIX: correctly sign extend data from memory controller FIX: set ALU to not branch on CSR unit ops FIX: correctly detect invalid operations in decode stage FIX: set signals not outputs in decode Change to use two regs arrays in register set to infer two port rams Colin Riley 2020-05-17 23:39:17 +01:00
  • 01ac31c43d Stores should go though writeback in order for a interrupt check (can be optimized later). Core: disable interrupts by default, make O_DBG output 64 bit to allow for additional data field and rearranged signals. This allowes for instruction tracing implementation on the SoC side. Colin Riley 2018-12-14 00:31:38 +00:00
  • a9f3009b8f Fix bug in which OP decode previously went though the others=> case, which is now solely for invalid instructions. This caused an illegal intruction interrupt on all OP instructions (add,sub) or if interrupts are disabled, allowed the instruction to proceed without the data write from ALU occuring to the register file, causing major debug headaches. Colin Riley 2018-12-14 00:18:22 +00:00
  • bb6683092f RISC-V Machine level Interrupt support first pass. Colin Riley 2018-11-21 23:45:51 +00:00
  • a9c5413cd9 Update to readme clarifying diagram missing CSR unit, and laying out current areas of implementation effort. Colin Riley 2018-11-16 22:48:50 +00:00
  • 96b86f1dc2 Basic core execution simulator testbench. No memory subsystem, so will only execute from fixed array of instructions - but easy to use in the sim. Colin Riley 2018-11-16 22:43:47 +00:00
  • 25411fd194 CSR Unit implemented with all CSR operational modify operations (write, set, clear). Not all CSRs are supported as yet, but cycles, instret and some of the machine identifiers are. Also two R/W locations at 0x400 and 0x401 for testing. Colin Riley 2018-11-16 22:39:57 +00:00
  • cc388e3a90 Start of CSR and interrupt support for machine-mode level operations. No testbenches and the CSR operations are not fixed up yet. Some basic read values are included but as the register write logic is not edited to take values from the CSR unit rather than ALU any reads will result in the incorrect data being stored into rD. Colin Riley 2018-11-12 00:17:16 +00:00
  • 12f77e85c5 Apache 2 license file headers (yes, most of this was written 2 years ago!) Colin Riley 2018-09-17 23:35:20 +01:00
  • 32d133e85d
         Add License Colin Riley 2018-09-17 23:24:42 +01:00
  • 9f24beba69 Rearrange readme and add overview image. Colin Riley 2018-09-11 23:58:33 +01:00
  • 439781c194 Initial commit. Tested on ArtyS7-RPU-SoC and passes SD bootloader and DDR3 memory testing. Colin Riley 2018-09-11 23:53:41 +01:00
  • 84a652b41c
         Initial commit Colin Riley 2018-09-11 23:03:05 +01:00