Updated ISA support to RV32IMZcsr - Passes riscv-compliance.
Integer divide/rem in 34 cycles.
Integer multiply in 2 cycles (when using xilinx dsp blocks!)
Saved multiple cycles from fetch/memory load stages by short-cutting the start of memory requests.
Compliant misaligned exceptions for jumps,loads and stores. Addrs starting 0xFxxxxxxx ignore alignment requests (assumes mmio space).
Added CSRs for riscv-compliance requirements.
Source ran through a formatter for ease of use.
Added Interrupt handling support:
- Int enable masks
- external interrupt
- interrupt enable CSR
- illegal instruction
- system call instruction
- breakpoints
- interrupt CSR manipulation
- correct nextPC resume/branch target selection
Added debug data for CPU trace support
Added vexrisc IRQ csrs for testing with 3rd party sw
Added LINT unit locally arbitrates IRQs into priorities
FIX: correctly sign extend data from memory controller
FIX: set ALU to not branch on CSR unit ops
FIX: correctly detect invalid operations in decode stage
FIX: set signals not outputs in decode
Change to use two regs arrays in register set to infer two port rams
Core: disable interrupts by default, make O_DBG output 64 bit to allow for additional data field and rearranged signals. This allowes for instruction tracing implementation on the SoC side.
- Added Local interrupt unit which just collates all int sources.
- Added relevant core glue logic.
- Added M-level CSRs for trap handling.
- Disabled legacy interrupt handling from pc unit as interrupt vector is no longer fixed.
- ALU handles mret as a basic branch to epc.
- ECALL/EBREAK/MRET support added to decoder.
True RISC-V interrupt support still needs interrupt enables via CSR, and proper state flipping (IE/PIE etc)
