Exact

Exact Union RegExp

Colin Riley 4b16f9bf6f RPU 1.0 ... Updated ISA support to RV32IMZcsr - Passes riscv-compliance. Integer divide/rem in 34 cycles. Integer multiply in 2 cycles (when using xilinx dsp blocks!) Saved multiple cycles from fetch/memory load stages by short-cutting the start of memory requests. Compliant misaligned exceptions for jumps,loads and stores. Addrs starting 0xFxxxxxxx ignore alignment requests (assumes mmio space). Added CSRs for riscv-compliance requirements. Source ran through a formatter for ease of use.		2020-09-11 00:06:01 +01:00
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rpu_core_tb.vhd	RPU 1.0	2020-09-11 00:06:01 +01:00
tb_alu_int32_div.vhd	RPU 1.0	2020-09-11 00:06:01 +01:00
tb_unit_alu_RV32I_01.vhd	Initial commit. Tested on ArtyS7-RPU-SoC and passes SD bootloader and DDR3 memory testing.	2018-09-11 23:53:41 +01:00
tb_unit_decoder_RV32_01.vhd	Initial commit. Tested on ArtyS7-RPU-SoC and passes SD bootloader and DDR3 memory testing.	2018-09-11 23:53:41 +01:00