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Basic RISC-V CPU implementation in VHDL.
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Colin Riley bb6683092f RISC-V Machine level Interrupt support first pass. 
- Added Local interrupt unit which just collates all int sources.
- Added relevant core glue logic.
- Added M-level CSRs for trap handling.
- Disabled legacy interrupt handling from pc unit as interrupt vector is no longer fixed.
- ALU handles mret as a basic branch to epc.
- ECALL/EBREAK/MRET support added to decoder.

True RISC-V interrupt support still needs interrupt enables via CSR, and proper state flipping (IE/PIE etc)
2018-11-21 23:45:51 +00:00
tests Basic core execution simulator testbench. No memory subsystem, so will only execute from fixed array of instructions - but easy to use in the sim. 2018-11-16 22:43:47 +00:00
vhdl RISC-V Machine level Interrupt support first pass. 2018-11-21 23:45:51 +00:00
LICENSE Add License 2018-09-17 23:24:42 +01:00
README.md Update to readme clarifying diagram missing CSR unit, and laying out current areas of implementation effort. 2018-11-16 22:48:50 +00:00
rpu_core_diagram.png Initial commit. Tested on ArtyS7-RPU-SoC and passes SD bootloader and DDR3 memory testing. 2018-09-11 23:53:41 +01:00

README.md

RPU

Basic RISC-V CPU implementation in VHDL.

This is a RV32I ISA CPU implementation, based off of my TPU CPU design. It is very simple, is missing several features, but can run rv32i-compiled GCC toolchain binaries at over 200MHz on a Digilent Arty S7-50 board, built with Xilinx Spartan 7 tools.

Please let me know if you are using any of the RPU design in your own projects! I am contactable on twitter @domipheus.

Implementation

Diagram does not include recently added CSR unit.

RPU Core overview

Implementation detail is written about via blogs available at http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-15-introducing-rpu/

The tests in the repo are incredibly old and basic, and included only as a baseline to help. They will be expanded upon in time. The core_tb should work for basic simulator use and could be expanded for more complex debugging.

Currently working on: CSRs, Interrupts