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1.0.0

1.0.1

Mono Color

• 319d162f67 Merge remote-tracking branch 'origin/tigthlyCoupled' into dev Charles Papon 2019-10-03 12:33:27 +02:00
• 5df56bea79 Allow getDrivingReg to properly see i$ decode.input(INSTRUCTION) register (used to inject instruction from the debug plugin) tigthlyCoupled Charles Papon 2019-10-03 00:20:33 +02:00
• ca228a392e Merge branch 'short-pipeline-fixes' Charles Papon 2019-09-26 10:25:11 +02:00
• 8d8c301662 Merge branch 'short-pipeline-fixes-xobs' into short-pipeline-fixes short-pipeline-fixes Charles Papon 2019-09-23 15:22:27 +02:00
• 49944643d2 Add regression for data cache without writeback stage, seem to pass tests, including linux ones Charles Papon 2019-09-23 15:20:51 +02:00
• bf82829e9e Data cache can now be used without writeback stage Charles Papon 2019-09-23 15:20:20 +02:00
• ace963b542 Hazard on memory stage do not need to know if that's bypassable if the memory stage is the last one Charles Papon 2019-09-21 14:13:28 +02:00
• e1795e59d5 Enable RF bypass on MUL DIV with pipeline wihout writeback/memory stages Charles Papon 2019-09-21 13:00:54 +02:00
• e8236dfebe Add MulSimplePlugin regressions Charles Papon 2019-09-21 12:49:46 +02:00
• be18d8fa5a CSR access enables are also impacted by the MMU memory access Charles Papon 2019-09-21 10:28:52 +02:00
• b8b053e706 muldiviterative: fix build for short pipelines Sean Cross 2019-09-20 08:36:01 +08:00
• fdc95debef dbuscached: fix build for short pipelines Sean Cross 2019-09-20 08:35:49 +08:00
• 0b79c637b6 mulsimpleplugin: fix build for short pipelines Sean Cross 2019-09-20 08:35:23 +08:00
• fe385da850 Fix Artix7 FMax, my apologies for that, was due to a bad scripting using Kintex 7 instead Charles Papon 2019-09-16 14:22:33 +02:00
• 88eb8e4e47 Fix Artix7 FMax, my apologies for that, was due to a bad scripting using Kintex 7 instead Charles Papon 2019-09-16 14:22:33 +02:00
• 6ed41f7361 Improve CSR FMax Charles Papon 2019-09-16 13:53:55 +02:00
• d94cee13f0 Add dummy decoding, exception code/tval Add Cpu generation code Add support for always ready rsp cfu Charles Papon 2019-09-05 19:06:28 +02:00
• 5ac443b745 Manage cases where a rsp buffer is required Charles Papon 2019-09-05 10:30:33 +02:00
• 6951f5b8e6 CfuPlugin addition Dolu1990 2019-07-29 14:17:51 +02:00
• 84602f89b0 Merge pull request #80 from antmicro/fix_litex_target Dolu1990 2019-07-24 19:17:23 +02:00
• 86f5af5ca9 Fix handling LiteX uart and timer. Mateusz Holenko 2019-07-24 14:55:47 +02:00
• 0efcaa505d Merge pull request #79 from antmicro/litex_target Dolu1990 2019-07-20 02:59:42 +03:00
• 8813e071bc Add litex target Mateusz Holenko 2019-07-10 10:39:26 +02:00
• 64a2815544 Create makefile targets Mateusz Holenko 2019-07-10 10:39:47 +02:00
• e76435c6c6 Allow to set custom DTB/OS_CALL addresses Mateusz Holenko 2019-07-10 10:38:58 +02:00
• c8280a9a88 Allow to set custom RAM base address for emulator Mateusz Holenko 2019-07-10 10:38:38 +02:00
• 94f1707d65 Merge branch 'dev' Charles Papon 2019-06-16 20:50:43 +02:00
• b65ef189eb sync with SpinalHDL SDRAM changes Charles Papon 2019-08-29 16:03:20 +02:00
• b91df10b21 Merge branch 'master' of github.com:SpinalHDL/VexRiscv into HEAD Sean Cross 2019-07-27 21:27:16 +08:00
• b0199297fd caches: work without writeBack stage Sean Cross 2019-04-26 18:02:43 +08:00
• 955e70206c MmuPlugin: fix generation without writeBack stage Sean Cross 2019-04-26 18:01:35 +08:00
• 5f0c7a7faf
  Merge pull request #80 from antmicro/fix_litex_target Dolu1990 2019-07-24 19:17:23 +02:00
• 5085877eed Fix handling LiteX uart and timer. Mateusz Holenko 2019-07-24 14:55:47 +02:00
• 6124ec7b14
  Merge pull request #79 from antmicro/litex_target Dolu1990 2019-07-20 02:59:42 +03:00
• 6a2584b840 Add litex target Mateusz Holenko 2019-07-10 10:39:26 +02:00
• 39c3f408e5 Create makefile targets Mateusz Holenko 2019-07-10 10:39:47 +02:00
• 423355ecbf Allow to set custom DTB/OS_CALL addresses Mateusz Holenko 2019-07-10 10:38:58 +02:00
• 28a11976da Allow to set custom RAM base address for emulator Mateusz Holenko 2019-07-10 10:38:38 +02:00
• a2569e76c0 Update sdram ctrl package Charles Papon 2019-07-08 11:23:48 +02:00
• 624c641af5 xip refractoring Charles Papon 2019-06-28 10:23:39 +02:00
• b2e06ae198 Back into unreleased SpinalHDL Charles Papon 2019-06-17 17:19:11 +02:00
• 20cbd4012f Merge branch 'dev' Charles Papon 2019-06-16 20:50:43 +02:00
• 1257b056dc Revert "test only dynamic_target for intensive test" Charles Papon 2019-06-16 18:24:59 +02:00
• 12c3ab16ae Update readme perf Charles Papon 2019-06-16 18:07:04 +02:00
• 635ef51f82 test only dynamic_target for intensive test Charles Papon 2019-06-16 17:43:07 +02:00
• 9656604848 rework dynamic_target failure correction Charles Papon 2019-06-16 17:42:39 +02:00
• 4cf7e5b98f SpinalHDL 1.3.6 Charles Papon 2019-06-16 00:42:59 +02:00
• 60c9c094a7 Merge remote-tracking branch 'origin/rework_jump_flush' into dev Charles Papon 2019-06-15 18:09:38 +02:00
• 46e9d5566a Merge branch 'rework_jump_flush' Charles Papon 2019-06-15 18:05:04 +02:00
• 7c3c4e8c81 Update readme benches rework_jump_flush Charles Papon 2019-06-15 14:23:09 +02:00
• a3a0c402bc Remove broken freertos test and add zephyr instead Charles Papon 2019-06-15 10:46:10 +02:00
• 617f4742cd Fix dynamic branch prediction correction on misspredicted fetch which are done on a 32 bits instruction crossing two words in configs which have at least 2 cycle latency fetch Charles Papon 2019-06-14 08:13:22 +02:00
• d603de1bfe Fix recent changes Charles Papon 2019-06-13 16:55:24 +02:00
• c8ab99cd0b Cleaning and remove BlockQ regression Charles Papon 2019-06-12 00:00:38 +02:00
• 21ec368927 Fix DYNAMIC_TARGET by fixing decode PC updates Charles Papon 2019-06-11 19:56:33 +02:00
• afbf0ea777 Fix regression makefile Charles Papon 2019-06-11 01:05:49 +02:00
• 066ddc23e6 Add regression concurrent os executions flag to avoid running debug plugin tests Charles Papon 2019-06-11 00:22:38 +02:00
• 21c8933bbb Fix DYNAMIC_TARGET prediction correction in BranchPlugin Charles Papon 2019-06-11 00:12:29 +02:00
• 5b53440d27 DYNAMIC_TARGET prediction datapath/control path are now splited Charles Papon 2019-06-10 22:20:32 +02:00
• 0e95154869 individual regression : more env control Charles Papon 2019-06-10 21:01:41 +02:00
• bd46dd88aa Fix RVC fetcher pc branches Charles Papon 2019-06-10 20:48:04 +02:00
• 24e1e3018c Fix exception handeling Charles Papon 2019-06-09 23:40:37 +02:00
• a6a8004489
  Merge 39471ed29c into 0e2d40c37f Tom Verbeure 2019-06-09 19:16:23 +00:00
• 5243e46ffb Fix BranchPlugin when SRC can have hazard in execute stage Charles Papon 2019-06-09 20:15:36 +02:00
• af0755d8cf rework flush with flushNext and flushIt static branch prediction jump do not depend on stage fireing anymore Charles Papon 2019-06-09 15:44:05 +02:00
• 0e2d40c37f Merge remote-tracking branch 'origin/pipelinedInterrupt' Charles Papon 2019-06-09 12:29:20 +02:00
• 357681a5c6 csrPlugin add pipelinedInterrupt, set by default pipelinedInterrupt Charles Papon 2019-06-08 22:22:16 +02:00
• 0df4ec45ad Merge remote-tracking branch 'origin/master' into dev Charles Papon 2019-06-05 00:35:41 +02:00
• 56f7c27d18 Fix WFI. Not sensitive anymore to global interrupt enables, delegation and privilege Charles Papon 2019-06-05 00:32:38 +02:00
• 64e8919e89
  Update README.md Dolu1990 2019-05-28 11:28:07 +02:00
• 38a464a829 DataCache now allocate ways randomly Charles Papon 2019-05-25 00:28:30 +02:00
• 4a40184b35 Add cache Bandwidth counter, previous commit was about random instruction cache way allocation Charles Papon 2019-05-25 00:22:27 +02:00
• 94606d38e2 Add cache bandwidth counter Charles Papon 2019-05-25 00:21:48 +02:00
• 206c7ca638 Fix Bmb datacache bridge Charles Papon 2019-05-24 00:22:58 +02:00
• f6f94ad7c1 Fix InstructionCache Bmb bridge Charles Papon 2019-05-22 19:03:26 +02:00
• 9b49638654 Allow CsrPlugin config access Charles Papon 2019-05-22 17:27:47 +02:00
• 8abc06c8f2 Add Bmb support for i$/d$ Charles Papon 2019-05-22 17:04:36 +02:00
• 49b4b61a1a Update Bmb bridges Charles Papon 2019-05-20 14:14:42 +02:00
• f249bbc60a Merge remote-tracking branch 'origin/tmp' Charles Papon 2019-05-18 20:35:28 +02:00
• b40dc06b29 SpinalHDL 1.3.5 tmp Charles Papon 2019-05-18 19:56:03 +02:00
• 0301ced000 Fix dBusSimplePlugin to bmb bridge Charles Papon 2019-05-16 19:49:13 +02:00
• 4ce9d805b4 Switch to unreleased SpinalHDL Charles Papon 2019-05-14 00:41:14 +02:00
• 3753f64429 Fix Bmb compilation Charles Papon 2019-05-13 23:44:20 +02:00
• abb7bd99ab
  Merge pull request #75 from SpinalHDL/dev Dolu1990 2019-05-10 17:28:09 +02:00
• 8201cff7ff SpinalHDL 1.3.4 Charles Papon 2019-05-10 14:27:14 +02:00
• db307075cf Merge branch 'AHB' into dev Charles Papon 2019-05-07 17:21:52 +02:00
• 39471ed29c Disable memory2Stage by default. Tom Verbeure 2019-05-07 07:04:05 -07:00
• 89de3fe5ae Fix memory2 compilation. Tom Verbeure 2019-05-07 06:59:43 -07:00
• a07ddc3b85 Merge branch 'master' into memory2 Tom Verbeure 2019-05-07 06:37:44 -07:00
• 01db217ab9 Add supervisor support in the ExternalInterruptArrayPlugin Charles Papon 2019-05-06 16:23:43 +02:00
• 3094f8b349 Merge remote-tracking branch 'origin/dBusCachedRelaxMmuTranslation' Dolu1990 2019-05-06 01:36:56 +02:00
• 91f6bf5139 Merge branch 'dBusCachedRelaxMmuTranslation' dBusCachedRelaxMmuTranslation Dolu1990 2019-05-06 01:36:11 +02:00
• d27fa4766d DBusCachedPlugin add earlyWaysHits in regressions Charles Papon 2019-05-06 00:05:40 +02:00
• d12decde80 Remove test which had issues with the testbench ref checks because of getting passed delayed Charles Papon 2019-05-05 22:46:46 +02:00
• 8f1b980337 Revert "Add DBusCachedPlugin.relaxedMemoryTranslationRegister option" Charles Papon 2019-05-05 22:29:33 +02:00
• 5f18705358 Add DBusCachedPlugin.relaxedMemoryTranslationRegister option Charles Papon 2019-05-05 21:19:48 +02:00
• c738246610 Remove the legacy pipelining from Axi4 cacheless bridges Charles Papon 2019-05-01 12:03:01 +02:00
• 7d99a70e9c Switch to released SpinalHDL Charles Papon 2019-05-01 12:02:27 +02:00
• 02db756b21 Merge remote-tracking branch 'origin/master' into dev Charles Papon 2019-04-29 16:56:04 +02:00
• fa13e46e87
  Merge pull request #71 from xobs/mmu-2-stage Dolu1990 2019-04-26 14:25:29 +02:00