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89 lines
No EOL
3 KiB
Systemverilog
89 lines
No EOL
3 KiB
Systemverilog
/*
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* Copyright © 2020 Eric Matthews, Lesley Shannon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Eric Matthews <ematthew@sfu.ca>
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*/
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module writeback
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import cva5_config::*;
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import riscv_types::*;
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import cva5_types::*;
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# (
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parameter cpu_config_t CONFIG = EXAMPLE_CONFIG,
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parameter int unsigned NUM_WB_UNITS = 5,
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parameter unit_id_enum_t [MAX_NUM_UNITS-1:0] WB_INDEX = '{0: ALU_ID, 1: MUL_ID, 2: DIV_ID, 3: LS_ID, 4: CSR_ID, default: NON_WRITEBACK_ID}
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)
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(
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input logic clk,
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input logic rst,
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//Unit writeback
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unit_writeback_interface.wb unit_wb[MAX_NUM_UNITS],
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//WB output
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output wb_packet_t wb_packet
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);
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//aliases for write-back-interface signals
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id_t [NUM_WB_UNITS-1:0] unit_instruction_id;
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logic [NUM_WB_UNITS-1:0] unit_done;
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logic [31:0] unit_rd [NUM_WB_UNITS];
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logic [NUM_WB_UNITS-1:0] unit_ack;
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localparam int unsigned LOG2_NUM_WB_UNITS = (NUM_WB_UNITS == 1) ? 1 : $clog2(NUM_WB_UNITS);
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logic [LOG2_NUM_WB_UNITS-1:0] unit_sel;
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////////////////////////////////////////////////////
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//Implementation
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//Re-assigning interface inputs to array types so that they can be dynamically indexed
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generate for (genvar i = 0; i < NUM_WB_UNITS; i++) begin : gen_wb_unit_unpacking
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assign unit_instruction_id[i] = unit_wb[WB_INDEX[i]].id;
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assign unit_done[i] = unit_wb[WB_INDEX[i]].done;
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assign unit_rd[i] = unit_wb[WB_INDEX[i]].rd;
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assign unit_wb[WB_INDEX[i]].ack = unit_ack[i];
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end endgenerate
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////////////////////////////////////////////////////
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//Unit select for register file
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//Iterating through all commit ports:
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// Search for complete units (in fixed unit order)
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// Assign to a commit port, mask that unit and commit port
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priority_encoder #(.WIDTH(NUM_WB_UNITS))
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unit_done_encoder
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(
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.priority_vector (unit_done),
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.encoded_result (unit_sel)
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);
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assign wb_packet = '{
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valid : |unit_done,
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id : unit_instruction_id[unit_sel],
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data : unit_rd[unit_sel]
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};
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assign unit_ack = NUM_WB_UNITS'(wb_packet.valid) << unit_sel;
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////////////////////////////////////////////////////
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//End of Implementation
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////////////////////////////////////////////////////
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////////////////////////////////////////////////////
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//Assertions
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endmodule |