cva5/core
Eric Matthews 8769842249 Add dcache cbo instruction support
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-05-02 14:58:26 -04:00
..
common_components Consolidate BRAM implementations 2023-04-17 13:15:24 -04:00
execution_units Add dcache cbo instruction support 2023-05-02 14:58:26 -04:00
fetch_stage Consolidate BRAM implementations 2023-04-17 13:15:24 -04:00
memory_sub_units Reorganize source files 2023-04-14 20:21:05 -04:00
types_and_interfaces Add dcache cbo instruction support 2023-05-02 14:58:26 -04:00
cva5.sv Move write-back group config into cpu_config struct 2023-04-29 18:37:42 -04:00
decode_and_issue.sv Autogenerate decode_wb_group from config data 2023-05-01 16:42:41 -04:00
instruction_metadata_and_id_management.sv Convert id_metadata from inferred LUTRAMs to LUTRAM modules 2023-04-11 19:35:04 -04:00
l1_arbiter.sv Switch L1 arbitration to round-robin 2022-11-14 13:36:50 -05:00
mmu.sv renamed occurrences of taiga to cva5 2022-03-05 12:53:49 -08:00
register_file.sv Consolidate struct-to-bits type conversion into FIFO/LUTRAMs 2023-04-11 14:43:39 -04:00
register_free_list.sv Consolidate struct-to-bits type conversion into FIFO/LUTRAMs 2023-04-11 14:43:39 -04:00
renamer.sv Consolidate struct-to-bits type conversion into FIFO/LUTRAMs 2023-04-11 14:43:39 -04:00
tlb_lut_ram.sv Consolidate struct-to-bits type conversion into FIFO/LUTRAMs 2023-04-11 14:43:39 -04:00
writeback.sv Move write-back group config into cpu_config struct 2023-04-29 18:37:42 -04:00