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Add riscv front-end server

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This commit is contained in:
Florian Zaruba 2017-06-04 14:04:44 +02:00
parent ccd0188670
commit 5384fcdaca
5 changed files with 11 additions and 1 deletions
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3
.gitmodules vendored
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@ -1,3 +1,6 @@
[submodule "uvm-scaffold"]
path = uvm-scaffold
url = git@iis-git.ee.ethz.ch:floce/uvm-scaffold.git
[submodule "lib/riscv-fesvr"]
path = lib/riscv-fesvr
url = git@iis-git.ee.ethz.ch:floce/riscv-fesvr.git

1
lib/riscv-fesvr Submodule

@ -0,0 +1 @@
Subproject commit 14f61ce4833126b1327926ad12f7d7bc653702b6

2
src/pcgen.sv
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@ -49,7 +49,7 @@ module pcgen (
assign fetch_address_o = npc_q;
btb #(
.NR_ENTRIES(64),
.NR_ENTRIES(4096),
.BITS_SATURATION_COUNTER(2)
)
btb_i

3
src/util/instruction_trace_item.svh
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@ -153,8 +153,11 @@ class instruction_trace_item;
INSTR_CSRRC: s = this.printCSRInstr("csrrc");
INSTR_CSRC: s = this.printCSRInstr("csrc");
INSTR_CSRWI: s = this.printCSRInstr("csrwi");
INSTR_CSRRWI: s = this.printCSRInstr("csrrwi");
INSTR_CSRSI: s = this.printCSRInstr("csrsi");
INSTR_CSRRSI: s = this.printCSRInstr("csrrsi");
INSTR_CSRCI: s = this.printCSRInstr("csrci");
INSTR_CSRRCI: s = this.printCSRInstr("csrrci");
// SYSTEM (others)
INSTR_ECALL: s = this.printMnemonic("ecall");

3
src/util/instruction_tracer_defines.svh
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@ -83,8 +83,11 @@ parameter INSTR_CSRS = { 12'b?, 5'b?, 3'b010, 5'b0, OPCODE_SYSTEM };
parameter INSTR_CSRRC = { 12'b?, 5'b?, 3'b011, 5'b?, OPCODE_SYSTEM };
parameter INSTR_CSRC = { 12'b?, 5'b?, 3'b011, 5'b0, OPCODE_SYSTEM };
parameter INSTR_CSRWI = { 17'b?, 3'b101, 5'b0, OPCODE_SYSTEM };
parameter INSTR_CSRRWI = { 17'b?, 3'b101, 5'b?, OPCODE_SYSTEM };
parameter INSTR_CSRSI = { 17'b?, 3'b110, 5'b0, OPCODE_SYSTEM };
parameter INSTR_CSRRSI = { 17'b?, 3'b110, 5'b?, OPCODE_SYSTEM };
parameter INSTR_CSRCI = { 17'b?, 3'b111, 5'b0, OPCODE_SYSTEM };
parameter INSTR_CSRRCI = { 17'b?, 3'b111, 5'b?, OPCODE_SYSTEM };
parameter INSTR_ECALL = { 12'b000000000000, 13'b0, OPCODE_SYSTEM };