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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

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Florian Zaruba 5384fcdaca Add riscv front-end server		2017-06-04 14:04:44 +02:00
docs	[WIP] Implement return from exception	2017-06-01 16:55:15 +02:00
include	FENCE as NOP and 🐛 in flush CSR	2017-06-03 19:10:27 +02:00
lib	Add riscv front-end server	2017-06-04 14:04:44 +02:00
src	Add riscv front-end server	2017-06-04 14:04:44 +02:00
tb	Implement clear on mis-predict flag	2017-06-03 18:52:02 +02:00
test	[WIP] Implement ecall and ebreak instructions	2017-06-01 10:43:26 +02:00
uvm-scaffold@d59b8d6a51	Instantiated dcache interface for store queue test	2017-05-29 19:09:14 +02:00
.gitignore	Adapt dcache arbiter testbench using new dcache if	2017-05-29 15:51:31 +02:00
.gitlab-ci.yml	Fix .gitlab-ci.yml	2017-05-29 16:46:19 +02:00
.gitmodules	Add riscv front-end server	2017-06-04 14:04:44 +02:00
CHANGELOG	📝 Add CHANGELOG to gitlab, manually created	2017-04-21 11:09:30 +02:00
CONTRIBUTING.md	Fix issue #8	2017-05-05 11:06:37 +02:00
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Makefile	Re-add test target to Makefile	2017-05-29 19:34:12 +02:00
mkdocs.yml	📝 Add timing diagram for memory interface	2017-05-07 13:09:05 +02:00
README.md	📝 Add small getting started section	2017-06-04 13:00:33 +02:00

Ariane RISC-V CPU

For detailed documentation refer to the online documentation (Login: zarubaf Password: zaruba).

Getting Started

Checkout the repository and initialize all submodules

git checkout git@iis-git.ee.ethz.ch:floce/ariane.git
git submodule update --init --recursive

Build Ariane by using the Makefile:

make build

Start the simulation using Modelsim:

make sim

Or start any of the unit tests by:

make dcache_arbiter