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Merge branch 'master' into branch-for-prabha

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Mike Thompson 2023-06-23 12:25:47 -04:00 • committed by GitHub
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42
.github/workflows/dashboard-done.yml vendored Normal file
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@ -0,0 +1,42 @@
# Copyright 2023 Thales Silicon Security
#
# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
# You may obtain a copy of the License at https://solderpad.org/licenses/
#
# Original Author: Côme ALLART - Thales
on:
workflow_dispatch:
inputs:
pr_number:
description: 'ID of the PR to comment'
required: true
type: string
success:
description: 'Is the workflow successful?'
required: true
type: boolean
permissions:
pull-requests: write
jobs:
welcome:
runs-on: ubuntu-latest
steps:
- uses: actions/github-script@v6
with:
script: |
const inputs = context.payload.inputs
const pr = inputs.pr_number
const success = inputs.success == 'true'
const status_text = success ? ":heavy_check_mark: successful" : ":x: failed"
const url = `https://riscv-ci.pages.thales-invia.fr/dashboard/dashboard_core-v-verif_${pr}.html`
await github.rest.issues.createComment({
issue_number: pr,
owner: context.repo.owner,
repo: context.repo.repo,
body: `${status_text} run, report available [here](${url}).`
})

3
.gitlab-ci.yml
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@ -36,6 +36,9 @@ variables:
workflow:
rules:
- if: '$CI_WEIGHT == "forced" && $CI_COMMIT_REF_NAME =~ /^cvvdev\/.*/' #bypass workflow + cvvdev
variables:
CVA6_BRANCH: $CI_COMMIT_REF_NAME
- if: '$CI_WEIGHT == "forced"' #bypass workflow
- if: '$CI_COMMIT_REF_NAME =~ /^master.*|^hotfix.*|^rc.*|^cva6\/dev.*|^github-pr.*/'
variables:

176
.gitlab-ci/cva6.yml
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@ -66,6 +66,7 @@ variables:
stages:
- .pre
- build_tools
- one
- two
- three
@ -91,9 +92,8 @@ initjob:
reports:
dotenv: .env
pub_check_env:
stage: one
stage: .pre
extends:
- .template_job_low_footprint
- .template_job_full_ci
@ -102,7 +102,9 @@ pub_check_env:
- echo $RISCV
- echo $RISCV_PREFIX
- echo $VERILATOR_ROOT
- echo $VERILATOR_INSTALL_DIR
- echo $SPIKE_ROOT
- echo $SPIKE_INSTALL_DIR
- echo $BBL_ROOT
- echo $SYN_VCS_BASHRC
- echo $SYN_DCSHELL_BASHRC
@ -133,12 +135,36 @@ pub_check_env:
- echo $SYNTH_PERIOD
- echo $LIB_VERILOG
pub_build_tools:
stage: build_tools
extends:
- .template_job_full_ci
needs: []
script:
# ROOT_PROJECT is used by Spike installer and designates the toplevel of core-v-verif tree.
- 'export ROOT_PROJECT=$(pwd)'
# If a local build of Spike is requested, clean up build and installation directories.
- '[ -n "$SPIKE_INSTALL_DIR" -a "$SPIKE_INSTALL_DIR" = "__local__" ] && rm -rf vendor/riscv/riscv-isa-sim/build'
- '[ -n "$SPIKE_INSTALL_DIR" -a "$SPIKE_INSTALL_DIR" = "__local__" ] && rm -rf tools/spike'
# Create default directory corresponding to the artifact path.
- mkdir -p tools/spike
# Set up Spike, whether locally built or pre-installed.
# If initially set to "__local__", SPIKE_INSTALL_DIR will be resolved
# to an absolute path by the installation script.
- source cva6/regress/install-spike.sh
# Strip locally built binaries and customext library to reduce artifact size.
- '[ -f $(pwd)/tools/spike/bin/spike ] && strip $(pwd)/tools/spike/bin/spike* $(pwd)/tools/spike/lib/libcustomext.so'
artifacts:
paths:
- tools/spike/
pub_smoke:
stage: one
extends:
- .template_job_full_ci
needs: []
needs:
- job: pub_build_tools
artifacts: true
parallel:
matrix:
- DV_SIMULATORS: ["veri-testharness,spike","vcs-testharness,spike","vcs-uvm,spike" ]
@ -148,21 +174,87 @@ pub_smoke:
DASHBOARD_SORT_INDEX: 0
DASHBOARD_JOB_CATEGORY: "Basic"
script:
- mkdir -p artifacts/reports
- mkdir -p artifacts/reports artifacts/logs
- python3 .gitlab-ci/scripts/report_fail.py
- echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC
- source cva6/regress/smoke-tests.sh
# In order to capture logs in case of test failure, the test script cannot fail.
- source cva6/regress/smoke-tests.sh || true
# The list of files must NOT fail on various DV_SIMULATORS values, so use 'v*_sim' to match
# 'veri-testharness_sim', 'vcs-testharness_sim' and 'vcs-uvm_sim' (one of them always applies,
# at least until new RTL simulator configurations are added.)
- for i in cva6/sim/*/v*_sim/*.log.iss ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done
- python3 .gitlab-ci/scripts/report_simu.py cva6/sim/logfile.log
artifacts:
when: always
paths:
- artifacts/reports/*.yml
- artifacts/logs/*.log.iss.head
pub_riscv_arch_test:
stage: two
extends:
- .template_job_short_ci
needs:
- job: pub_build_tools
artifacts: true
- job: pub_smoke
artifacts: false
parallel:
matrix:
- DV_TARGET: [cv64a6_imafdc_sv39, cv32a60x]
variables:
DV_SIMULATORS: "veri-testharness,spike"
DASHBOARD_JOB_TITLE: "arch_test $DV_TARGET"
DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite"
DASHBOARD_SORT_INDEX: 0
DASHBOARD_JOB_CATEGORY: "Test suites"
script:
- mkdir -p artifacts/reports
- python3 .gitlab-ci/scripts/report_fail.py
- echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC
- source cva6/regress/dv-riscv-arch-test.sh
- python3 .gitlab-ci/scripts/report_simu.py cva6/sim/logfile.log
artifacts:
when: always
paths:
- "artifacts/reports/*.yml"
csr_test:
stage: two
extends:
- .template_job_short_ci
needs:
- job: pub_build_tools
artifacts: true
- job: pub_smoke
artifacts: false
parallel:
matrix:
- DV_TARGET: [cv32a60x]
variables:
DV_SIMULATORS: "veri-testharness,spike"
DASHBOARD_JOB_TITLE: "csr_test $DV_TARGET"
DASHBOARD_JOB_DESCRIPTION: "CSR regression suite"
DASHBOARD_SORT_INDEX: 0
DASHBOARD_JOB_CATEGORY: "Test suites"
script:
- mkdir -p artifacts/reports
- python3 .gitlab-ci/scripts/report_fail.py
- echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC
- source cva6/regress/dv-riscv-csr-access-test.sh
- python3 .gitlab-ci/scripts/report_simu.py cva6/sim/logfile.log
artifacts:
when: always
paths:
- "artifacts/reports/*.yml"
pub_hwconfig:
stage: two
extends:
- .template_job_short_ci
needs:
- job: pub_build_tools
artifacts: true
- job: pub_smoke
artifacts: false
parallel:
@ -191,6 +283,8 @@ pub_compliance:
extends:
- .template_job_short_ci
needs:
- job: pub_build_tools
artifacts: true
- job: pub_smoke
artifacts: false
parallel:
@ -219,6 +313,8 @@ pub_tests-v:
extends:
- .template_job_short_ci
needs:
- job: pub_build_tools
artifacts: true
- job: pub_smoke
artifacts: false
parallel:
@ -248,6 +344,8 @@ pub_tests-p:
extends:
- .template_job_short_ci
needs:
- job: pub_build_tools
artifacts: true
- job: pub_smoke
artifacts: false
parallel:
@ -274,6 +372,7 @@ pub_tests-p:
pub_synthesis:
stage: two
timeout: 2 hours
extends:
- .template_job_always_manual
needs:
@ -285,6 +384,8 @@ pub_synthesis:
PERIOD: ["1.1"]
- TARGET: [cv32a60x]
PERIOD: ["0.95"]
- TARGET: [cv32a6_embedded]
PERIOD: ["0.85"]
variables:
INPUT_DELAY: "0.46"
OUTPUT_DELAY: "0.11"
@ -365,7 +466,9 @@ pub_benchmarks:
DASHBOARD_JOB_DESCRIPTION: "Performance indicator of some benchmark"
DASHBOARD_SORT_INDEX: 7
DASHBOARD_JOB_CATEGORY: "Test suites"
needs: []
needs:
- job: pub_build_tools
artifacts: true
script:
- mkdir -p artifacts/reports
- python3 .gitlab-ci/scripts/report_fail.py
@ -379,11 +482,61 @@ pub_benchmarks:
paths:
- "artifacts/reports/*.yml"
pub_coremark:
stage: two
extends:
- .template_job_full_ci
needs:
- job: pub_build_tools
artifacts: true
- job: pub_smoke
artifacts: false
variables:
DASHBOARD_JOB_TITLE: "CoreMark"
DASHBOARD_JOB_DESCRIPTION: "Performance indicator"
DASHBOARD_SORT_INDEX: 5
DASHBOARD_JOB_CATEGORY: "Performance"
script:
- mkdir -p artifacts/reports
- python3 .gitlab-ci/scripts/report_fail.py
- bash cva6/regress/coremark.sh --no-print
- python3 .gitlab-ci/scripts/report_benchmark.py --coremark cva6/sim/out_*/veri-testharness_sim/core_main.log
artifacts:
when: always
paths:
- "artifacts/reports/*.yml"
pub_dhrystone:
stage: two
extends:
- .template_job_full_ci
needs:
- job: pub_build_tools
artifacts: true
- job: pub_smoke
artifacts: false
variables:
DASHBOARD_JOB_TITLE: "Dhrystone"
DASHBOARD_JOB_DESCRIPTION: "Performance indicator"
DASHBOARD_SORT_INDEX: 5
DASHBOARD_JOB_CATEGORY: "Performance"
script:
- mkdir -p artifacts/reports
- python3 .gitlab-ci/scripts/report_fail.py
- bash cva6/regress/dhrystone.sh
- python3 .gitlab-ci/scripts/report_benchmark.py --dhrystone cva6/sim/out_*/veri-testharness_sim/dhrystone_main.log
artifacts:
when: always
paths:
- "artifacts/reports/*.yml"
pub_wb_dcache:
stage: three
extends:
- .template_job_always_manual
needs: []
needs:
- job: pub_build_tools
artifacts: true
variables:
DASHBOARD_JOB_TITLE: "Writeback Data Cache test"
DASHBOARD_JOB_DESCRIPTION: "Test of IP wb_dcache"
@ -397,7 +550,8 @@ pub_wb_dcache:
- source ci/make-tmp.sh
- source ci/build-riscv-tests.sh
- cd ../../../
- make run-asm-tests-verilator defines=WB_DCACHE
# Use 'verilator --no-timing' until the timing issues in corev_apu RTL are fixed.
- make verilator="verilator --no-timing" run-asm-tests-verilator defines=WB_DCACHE
- cd ../..
- python3 .gitlab-ci/scripts/report_pass.py
artifacts:
@ -440,6 +594,8 @@ pub_generated_tests:
stage: two
tags: [$TAGS_RUNNER]
needs:
- job: pub_build_tools
artifacts: true
- job: pub_smoke
artifacts: false
variables:
@ -486,8 +642,8 @@ pub_fpga-boot:
- job: pub_fpga-build
artifacts: true
variables:
VERILATOR_ROOT: "/shares/tools/dummy/verilator" # to avoid install of verilator
SPIKE_ROOT: "/shares/tools/dummy/spike" # to avoid install of spike
VERILATOR_INSTALL_DIR: "NO" # Skip install and checks of verilator
SPIKE_ROOT: "NO" # Skip install and checks of spike
DASHBOARD_JOB_TITLE: "FPGA Linux64 Boot "
DASHBOARD_JOB_DESCRIPTION: "Test of Linux 64 bits boot on FPGA Genesys2"
DASHBOARD_SORT_INDEX: 10

63
.gitlab-ci/scripts/github_integration.py Normal file
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@ -0,0 +1,63 @@
"""
This module makes it possible to trigger GitHub workflows.
"""
from os import environ as env
import requests
def api_url(owner, repo):
"Build API url for a given repository"
return f"https://api.github.com/repos/{owner}/{repo}"
def pulls(owner, repo):
"Get (public) pull requests from a given repository"
url = api_url(owner, repo) + '/pulls'
headers = {}
if 'GH_TOKEN' in env:
headers["Authorization"] = f"Token {env['GH_TOKEN']}"
response = requests.get(url, headers=headers)
assert response.status_code == 200
return response.json()
class Workflow:
"GitHub Workflow that can be triggered on a dispatch event"
def __init__(self, owner, repo, workflow_id, ref):
dispatches = f"/actions/workflows/{workflow_id}/dispatches"
self.url = api_url(owner, repo) + dispatches
self.ref = ref
def _trigger(self, inputs):
"Trigger the workflow"
data = {
'ref': self.ref,
'inputs': inputs,
}
token = env['GH_TOKEN']
headers = {
'Accept': 'application/vnd.github+json',
'Authorization': f"Bearer {token}",
'X-GitHub-Api-Version': '2022-11-28',
}
return requests.post(url=self.url, json=data, headers=headers)
class DashboardDone(Workflow):
"`dashboard-done.yml` GitHub workflow"
def __init__(self, owner, repo, ref):
workflow_id = 'dashboard-done.yml'
Workflow.__init__(self, owner, repo, workflow_id, ref)
def send(self, pr, success):
"Send success or failure message"
inputs = {
'pr_number': str(pr),
'success': success,
}
return self._trigger(inputs)
def send_success(self, pr):
"Send message stating that job is successful"
return self.send(pr, True)
def send_failure(self, pr):
"Send message stating that job is failed"
return self.send(pr, False)

20
.gitlab-ci/scripts/merge_job_reports.py
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@ -14,6 +14,7 @@ import yaml
import datetime
import sys
import subprocess
import github_integration as gh
# arguments: inputdir outputfile
@ -105,12 +106,14 @@ pipeline = {
'jobs': []
}
success = True
dir_list = os.listdir(sys.argv[1])
for f in dir_list:
with open(sys.argv[1] + "/" + f, 'r') as job_report:
report = safe_load(job_report)
pipeline["jobs"].append(report)
if report['status'] != 'pass':
success = False
pipeline["status"] = 'fail'
pipeline["label"] = 'FAIL'
@ -139,3 +142,20 @@ cd -
''', shell=True))
except subprocess.CalledProcessError as e:
print(f"Error: {e.output}")
def find_pr(branch, prs):
match = re.search(r'(.*)_PR_([a-zA-Z0-9](?:[a-zA-Z0-9]|[-_](?=[a-zA-Z0-9])){0,38})', branch)
if match:
label = f'{match.group(2)}:{match.group(1)}'
for pr in prs:
if label == pr['head']['label']:
return pr
return None
pulls = gh.pulls('openhwgroup', workflow_repo)
pr = find_pr(workflow_commit_ref_name, pulls)
if pr is not None:
ref_branch = pr['base']['ref']
wf = gh.DashboardDone('openhwgroup', workflow_repo, ref_branch)
response = wf.send(pr['number'], success)
print(response.text)

65
.gitlab-ci/scripts/report_benchmark.py Normal file
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@ -0,0 +1,65 @@
# Copyright 2022 Thales Silicon Security
#
# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
# You may obtain a copy of the License at https://solderpad.org/licenses/
#
# Original Author: Côme Allart
import sys
import report_builder as rb
path = None
mode = None
iterations = None
# Keep it up-to-date with compiler version and core performance improvements
# Will fail if the number of cycles is different from this one
valid_cycles = {
'dhrystone': 221425,
'coremark': 697868,
}
for arg in sys.argv[1:]:
if arg == '--dhrystone':
mode = 'dhrystone'
iterations = 500
elif arg == '--coremark':
mode = 'coremark'
# Too few iterations to consider a score
else:
path = arg
# We do not want to have a report without a check
assert mode is not None
with open(path, 'r') as f:
log = [l.strip() for l in f.readlines()]
stopwatch = []
for index, line in enumerate(log):
if line.split()[-1] == 'mcycle':
stopwatch.append(int(log[index + 1].split()[-1], 16))
# There might be > 2 matches, we use the two at the center
N = len(stopwatch)
assert N % 2 == 0
cycles = stopwatch[N//2] - stopwatch[N//2-1]
score_metric = rb.TableMetric('Performance results')
score_metric.add_value('cycles', cycles)
if iterations is not None:
ipmhz = iterations * 1000000 / cycles
if mode == 'dhrystone':
score_metric.add_value('Dhrystone/MHz', ipmhz)
score_metric.add_value('DMIPS/MHz', ipmhz / 1757)
diff = cycles - valid_cycles[mode]
if diff != 0:
score_metric.fail()
score_metric.add_value('Cycles diff', diff)
report = rb.Report(f'{cycles//1000} kCycles')
report.add_metric(score_metric)
report.dump()

161
.gitlab-ci/scripts/report_builder.py Normal file
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@ -0,0 +1,161 @@
# Copyright 2022 Thales Silicon Security
#
# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
# You may obtain a copy of the License at https://solderpad.org/licenses/
#
# Original Author: Côme Allart
"""
Helpers to build CI reports
"""
import os
import re
from datetime import datetime as dt
import yaml
class Metric:
"A metric is a part of the body of the report"
def __init__(self, name):
self.name = name
self.sort_index = None
self.failed = False
self.values = []
def to_doc(self):
"Transform to a dictionary"
return {
'display_name': self.name,
'sort_index': self.sort_index,
'type': self._t(),
'status': "fail" if self.failed else "pass",
'value': self._values_to_doc(),
}
def fail(self):
"Mark metric as failed"
self.failed = True
def _values_to_doc(self):
raise NotImplementedError()
def _t(self):
raise NotImplementedError()
class LogMetric(Metric):
"Log lines"
def add_value(self, line):
"Insert a line in the log"
self.values.append(line)
def _values_to_doc(self):
return self.values
def _t(self):
return 'log'
class TableMetric(Metric):
"Table"
def add_value(self, *col):
"Insert a line in the table"
self.values.append(list(col))
def _values_to_doc(self):
return [{'col': v} for v in self.values]
def _t(self):
return 'table'
class TableStatusMetric(Metric):
"Table with status label for each line"
def add_pass_label(self, label, *col):
"Insert a 'pass' line with given label in the table"
self._add_value('pass', label, *col)
def add_fail_label(self, label, *col):
"Insert a 'fail' line with given label in the table"
self._add_value('fail', label, *col)
self.fail()
def add_pass(self, *col):
"Insert a 'pass' line in the table"
self.add_pass_label("PASS", *col)
def add_fail(self, *col):
"Insert a 'fail' line in the table"
self.add_fail_label("FAIL", *col)
def _add_value(self, status, label, *col):
self.values.append((status, label, list(col)))
def _values_to_doc(self):
return [{'status': s, 'label': l, 'col': c} for (s,l,c) in self.values]
def _t(self):
return 'table_status'
class Report:
"A report is the top level entity of the document"
def __init__(self, label=None):
self.label = label
self.failed = False
self.metrics = []
def add_metric(self, *metric):
"Add one or more metric(s) to the report body"
for m in metric:
if m.sort_index is None:
if len(self.metrics) > 0:
m.sort_index = self.metrics[-1].sort_index + 1
else:
m.sort_index = 1
self.metrics.append(m)
if m.failed:
self.fail()
def fail(self):
"Mark report as failed"
self.failed = True
def to_doc(self):
"Transform to a dictionary"
assert len(self.metrics) > 0, "A report must have at least one metric"
start = os.environ['CI_JOB_STARTED_AT']
start_fmt = '%Y-%m-%dT%H:%M:%S%z'
start = dt.strptime(start, start_fmt).timestamp()
pass_label = "FAIL" if self.failed else "PASS"
label = pass_label if self.label is None else self.label
return {
'title': os.environ["DASHBOARD_JOB_TITLE"],
'description': os.environ["DASHBOARD_JOB_DESCRIPTION"],
'category': os.environ["DASHBOARD_JOB_CATEGORY"],
'sort_index': os.environ["DASHBOARD_SORT_INDEX"],
'job_id': os.environ["CI_JOB_ID"],
'job_url': os.environ["CI_JOB_URL"],
'job_stage_name': os.environ["CI_JOB_STAGE"],
'job_started_at': int(start),
'job_end_at': int(dt.now().timestamp()),
'token': 'YC' + str(dt.now().timestamp()).replace('.', ''),
'status': "fail" if self.failed else "pass",
'metrics': [m.to_doc() for m in self.metrics],
'label': label,
}
def dump(self, path=None):
"""
Create report file
By default the output path is build from $CI_JOB_NAME
"""
if path is None:
filename = re.sub(r'[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"])
path = 'artifacts/reports/'+filename+'.yml'
with open(path, 'w') as f:
yaml.dump(self.to_doc(), f)

41
.gitlab-ci/scripts/report_fail.py
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@ -7,40 +7,11 @@
#
# Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com)
import re
from pprint import pprint
import yaml
import datetime
import os
import report_builder as rb
report = {'title': os.environ["DASHBOARD_JOB_TITLE"],
'description': os.environ["DASHBOARD_JOB_DESCRIPTION"],
'category': os.environ["DASHBOARD_JOB_CATEGORY"],
'sort_index': os.environ["DASHBOARD_SORT_INDEX"],
'job_id': os.environ["CI_JOB_ID"],
'job_url': os.environ["CI_JOB_URL"],
'job_stage_name': os.environ["CI_JOB_STAGE"],
'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()),
'job_end_at': int(datetime.datetime.now().timestamp()),
'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''),
'status': "fail",
'label': "FAIL",
'metrics': [{'display_name': '',
'sort_index': 1,
'type': 'table_status',
'status': "fail",
'value': [{
'status': 'fail',
'label': 'FAIL',
'col': ['Job has failed before end of script'],
}],
}],
}
metric = rb.TableStatusMetric('')
metric.add_fail('Job has failed before end of script')
pprint(report)
filename = re.sub('[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"])
print(filename)
with open('artifacts/reports/'+filename+'.yml', 'w+') as f:
yaml.dump(report, f)
report = rb.Report()
report.add_metric(metric)
report.dump()

69
.gitlab-ci/scripts/report_fpga.py
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@ -8,32 +8,13 @@
# Original Author: Guillaume Chauvon(guillaume.chauvon@thalesgroup.com)
import re
from pprint import pprint
import yaml
import datetime
import sys
import os
import report_builder as rb
with open(str(sys.argv[1]), "r") as f:
log = f.read()
global_pass = "pass"
report = {
'title': os.environ["DASHBOARD_JOB_TITLE"],
'description': os.environ["DASHBOARD_JOB_DESCRIPTION"],
'category': os.environ["DASHBOARD_JOB_CATEGORY"],
'sort_index': os.environ["DASHBOARD_SORT_INDEX"],
'job_id': os.environ["CI_JOB_ID"],
'job_url': os.environ["CI_JOB_URL"],
'job_stage_name': os.environ["CI_JOB_STAGE"],
'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()),
'job_end_at': int(datetime.datetime.now().timestamp()),
'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''),
'status': "pass",
'metrics': []
}
pattern = re.compile(
"\|(?P<ind> +)(?P<Instance>[\w()\[\].]+) +\| +(?P<Module>[\w()\[\].]+) \| +(?P<TotalLUTs>\d+) \| +(?P<LogicLUTs>\d+) \| +(?P<LUTRAMs>\d+) \| +(?P<SRLs>\d+) \| +(?P<FFs>\d+) \| +(?P<RAMB36>\d+) \| +(?P<RAMB18>\d+) \| +(?P<DSP48Blocks>\d+) \|"
)
@ -45,36 +26,26 @@ for line in pattern.finditer(log):
break
data.append(l)
metric = {
'display_name': 'Utilization Results',
'sort_index': 1,
'type': 'table',
'status': 'pass',
'value': [],
}
report = rb.Report()
metric = rb.TableMetric('Utilization Results')
for i in data:
value = {"col": []}
if (i["ind"]).count(" ") < 10:
value["col"].append(i["Instance"])
if i["Instance"] == "ariane_xilinx":
report["label"] = i["TotalLUTs"] + " TotalLUTs"
value["col"].append(i["Module"])
value["col"].append(i["TotalLUTs"] + " TotalLUTs")
value["col"].append(i["LogicLUTs"] + " LogicLUTs")
value["col"].append(i["LUTRAMs"] + " LUTRAMs")
value["col"].append(i["SRLs"] + " SRLs")
value["col"].append(i["FFs"] + " FFs")
value["col"].append(i["RAMB36"] + " RAMB36")
value["col"].append(i["RAMB18"] + " RAMB18")
value["col"].append(i["DSP48Blocks"] + " DSP48Blocks")
metric["value"].append(value)
total = int(i["TotalLUTs"]) // 1000
report.label = f"{total} kLUTs"
metric.add_value(
i["Instance"],
i["Module"],
i["TotalLUTs"] + " TotalLUTs",
i["LogicLUTs"] + " LogicLUTs",
i["LUTRAMs"] + " LUTRAMs",
i["SRLs"] + " SRLs",
i["FFs"] + " FFs",
i["RAMB36"] + " RAMB36",
i["RAMB18"] + " RAMB18",
i["DSP48Blocks"] + " DSP48Blocks",
)
report["metrics"].append(metric)
filename = re.sub("[^\w\.\\\/]", "_", os.environ["CI_JOB_NAME"])
print(filename)
with open('artifacts/reports/'+filename+'.yml', 'w+') as f:
yaml.dump(report, f)
report.add_metric(metric)
report.dump()

58
.gitlab-ci/scripts/report_fpga_boot.py
View file

@ -7,12 +7,8 @@
#
# Original Author: Guillaume Chauvon(guillaume.chauvon@thalesgroup.com)
import re
from pprint import pprint
import yaml
import datetime
import sys
import os
import report_builder as rb
with open(str(sys.argv[1]), "r") as f:
lastline = f.readlines()[-1]
@ -20,52 +16,12 @@ with open(str(sys.argv[1]), "r") as f:
with open(str(sys.argv[1]), "r") as f:
log = f.read()
global_pass = "pass"
report = {
'title': os.environ["DASHBOARD_JOB_TITLE"],
'description': os.environ["DASHBOARD_JOB_DESCRIPTION"],
'category': os.environ["DASHBOARD_JOB_CATEGORY"],
'sort_index': os.environ["DASHBOARD_SORT_INDEX"],
'job_id': os.environ["CI_JOB_ID"],
'job_url': os.environ["CI_JOB_URL"],
'job_stage_name': os.environ["CI_JOB_STAGE"],
'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()),
'job_end_at': int(datetime.datetime.now().timestamp()),
'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''),
'status': "pass",
'metrics': []
}
metric = {
'display_name': 'Linux boot log',
'sort_index': 1,
'type': 'table_status',
'status': 'pass',
'value': [],
}
value = {}
print(lastline)
metric = rb.TableStatusMetric('Linux boot log')
if not ("Linux buildroot" in lastline and "riscv" in lastline):
value["status"] = "fail"
value["label"] = "FAIL"
report["status"] = "fail"
report["label"] = "FAIL"
metric["status"] = "fail"
metric.add_fail(lastline)
else:
value["status"] = "pass"
value["label"] = "PASS"
report["status"] = "pass"
report["label"] = "PASS"
metric.add_pass(lastline)
value["col"] = [lastline]
metric["value"].append(value)
report["metrics"].append(metric)
filename = re.sub("[^\w\.\\\/]", "_", os.environ["CI_JOB_NAME"])
print(filename)
with open('artifacts/reports/'+filename+'.yml', 'w+') as f:
yaml.dump(report, f)
report = rb.Report()
report.add_metric(metric)
report.dump()

42
.gitlab-ci/scripts/report_pass.py
View file

@ -7,41 +7,11 @@
#
# Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com)
import re
from pprint import pprint
import yaml
import datetime
import os
import report_builder as rb
report = {'title': os.environ["DASHBOARD_JOB_TITLE"],
'description': os.environ["DASHBOARD_JOB_DESCRIPTION"],
'category': os.environ["DASHBOARD_JOB_CATEGORY"],
'sort_index': os.environ["DASHBOARD_SORT_INDEX"],
'job_id': os.environ["CI_JOB_ID"],
'job_url': os.environ["CI_JOB_URL"],
'job_stage_name': os.environ["CI_JOB_STAGE"],
'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()),
'job_end_at': int(datetime.datetime.now().timestamp()),
'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''),
'status': "pass",
'label': "PASS",
'metrics': [{'display_name': '',
'sort_index': 1,
'type': 'table_status',
'status': "fail",
'value': [{
'status': 'pass',
'label': 'PASS',
'col': ['Job completed without error. No metric extraction is configured'],
}],
}],
}
pprint(report)
filename = re.sub('[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"])
print(filename)
with open('artifacts/reports/'+filename+'.yml', 'w+') as f:
yaml.dump(report, f)
metric = rb.TableStatusMetric('')
metric.add_pass('Job completed without error. No metric extraction is configured')
report = rb.Report()
report.add_metric(metric)
report.dump()

65
.gitlab-ci/scripts/report_simu.py
View file

@ -7,75 +7,34 @@
#
# Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com)
import re
from pprint import pprint
import yaml
import datetime
import sys
import os
import re
import report_builder as rb
with open(str(sys.argv[1]), 'r') as f:
log = f.read()
global_pass = "pass"
report = {'title': os.environ["DASHBOARD_JOB_TITLE"],
'description': os.environ["DASHBOARD_JOB_DESCRIPTION"],
'category': os.environ["DASHBOARD_JOB_CATEGORY"],
'sort_index': os.environ["DASHBOARD_SORT_INDEX"],
'job_id': os.environ["CI_JOB_ID"],
'job_url': os.environ["CI_JOB_URL"],
'job_stage_name': os.environ["CI_JOB_STAGE"],
'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()),
'job_end_at': int(datetime.datetime.now().timestamp()),
'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''),
'status': "pass",
'metrics': []
}
pattern = re.compile(
"^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?Compiling (.*) : .*(tests\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?Found matching ISS: (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?ISA (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?\[(\w*)\]: (\d*) matched(?:, (\d*) mismatch)?$",
re.MULTILINE)
list_of_tests = pattern.findall(log)
metric = rb.TableStatusMetric('')
job_test_pass = 0
job_test_total = 0
metric = {'display_name': '',
'sort_index': 1,
'type': 'table_status',
'status': "pass",
'value': []
}
for i in list_of_tests:
value = {}
job_test_total += 1
col = [i[3], i[2], i[0], i[1]] # isa testbench testsuite test
if i[4] == "PASSED":
value['status'] = "pass"
value['label'] = "PASS"
metric.add_pass(*col)
job_test_pass += 1
else:
value['status'] = "fail" # row level
value['label'] = "FAIL"
metric['status'] = "fail" # table_status level
report['status'] = "fail" # job level
value['col'] = []
value['col'].append(i[3]) # isa
value['col'].append(i[2]) # testbench
value['col'].append(i[0]) # testsuite
value['col'].append(i[1]) # test
metric['value'].append(value)
metric.add_fail(*col)
report['metrics'].append(metric)
if job_test_total == 0:
metric.fail()
report['label'] = f'{job_test_pass}/{job_test_total}'
pprint(report)
filename = re.sub('[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"])
print(filename)
with open('artifacts/reports/'+filename+'.yml', 'w+') as f:
yaml.dump(report, f)
report = rb.Report(f'{job_test_pass}/{job_test_total}')
report.add_metric(metric)
report.dump()

103
.gitlab-ci/scripts/report_synth.py
View file

@ -8,11 +8,9 @@
# Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com)
import re
from pprint import pprint
import yaml
import datetime
import sys
import os
import report_builder as rb
with open(str(sys.argv[1]), 'r') as f:
log = f.read()
@ -22,31 +20,8 @@ with open(str(sys.argv[2]), 'r') as f:
kgate_ratio = int(os.environ["NAND2_AREA"])
global_pass = "pass"
report = {'title': os.environ["DASHBOARD_JOB_TITLE"],
'description': os.environ["DASHBOARD_JOB_DESCRIPTION"],
'category': os.environ["DASHBOARD_JOB_CATEGORY"],
'sort_index': os.environ["DASHBOARD_SORT_INDEX"],
'job_id': os.environ["CI_JOB_ID"],
'job_url': os.environ["CI_JOB_URL"],
'job_stage_name': os.environ["CI_JOB_STAGE"],
'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()),
'job_end_at': int(datetime.datetime.now().timestamp()),
'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''),
'status': "pass",
'metrics': []
}
#Compile & elaborate log:
metric = {'display_name': 'Synthesis full log',
'sort_index': 3,
'type': 'log',
'status': "pass",
'value': []
}
log_metric = rb.LogMetric('Synthesis full log')
error_log = []
warning_log = []
for line in synthesis_log.splitlines():
@ -58,14 +33,9 @@ for line in synthesis_log.splitlines():
error_log.append(line)
if 'Warning: ' in line:
warning_log.append(line)
metric['value'] = error_log + warning_log
report['metrics'].append(metric)
log_metric.values = error_log + warning_log
# Area repport:
pattern = re.compile(
"^(Combinational area|Buf/Inv area|Noncombinational area|Macro/Black Box area):\ *(\d*\.\d*)$",
re.MULTILINE)
@ -78,57 +48,24 @@ hier = pattern.findall(log)
total_area = float(hier[0][1])
metric = {'display_name': 'Global results',
'sort_index': 1,
'type': 'table',
'status': "pass",
'value': []
}
value = {'col': []}
value['col'].append("Total area") # Name
value['col'].append(f'{int(total_area/kgate_ratio)} kGates') # value
metric['value'].append(value)
result_metric = rb.TableMetric('Global results')
label = f'{int(total_area/kgate_ratio)} kGates'
result_metric.add_value("Total area", label)
for i in global_val:
value = {'col': []}
value['col'].append(i[0]) # Name
if total_area == 0:
value['col'].append('0 %')
else:
value['col'].append(f'{int(float((i[1]))/total_area*100)} %') # value
metric['value'].append(value)
report['metrics'].append(metric)
metric = {'display_name': 'Hierarchies details',
'sort_index': 2,
'type': 'table',
'status': "pass",
'value': []
}
rel_area = 0 if total_area == 0 else int(float(i[1]) / total_area * 100)
result_metric.add_value(i[0], f'{rel_area} %')
hier_metric = rb.TableMetric('Hierarchies details')
for i in hier:
value = {}
value['col'] = []
value['col'].append(i[0]) # hier
value['col'].append(f"{int(float(i[1])/kgate_ratio)} kGates") # area
value['col'].append(f"{int(float(i[2]))} %") # %
#value['col'].append(int(float(i[3]))/int(float(i[1])*100)) # % combi
#value['col'].append(int(float(i[4]))/int(float(i[1])*100)) # % reg
#value['col'].append(int(float(i[5]))/int(float(i[1])*100)) # % black box
metric['value'].append(value)
hier_metric.add_value(
i[0], # hier
f"{int(float(i[1])/kgate_ratio)} kGates", # area
f"{int(float(i[2]))} %", # %
#int(float(i[3]))/int(float(i[1])*100), # % combi
#int(float(i[4]))/int(float(i[1])*100), # % reg
#int(float(i[5]))/int(float(i[1])*100), # % black box
)
report['metrics'].append(metric)
report['label'] = f'{int(total_area/kgate_ratio)} kGates'
pprint(report)
filename = re.sub('[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"])
print(filename)
with open('artifacts/reports/'+filename+'.yml', 'w+') as f:
yaml.dump(report, f)
report = rb.Report(label)
report.add_metric(result_metric, hier_metric, log_metric)
report.dump()

4
.gitlab-ci/setup-ci-example/core-v-verif-cv32.yml
View file

@ -15,8 +15,8 @@ variables:
COMPLIANCE_HASH: 220e78542da4510e40eac31e31fdd4e77cdae437
COMPLIANCE_PATCH: ../../../cva6/riscv-compliance.patch
TESTS_REPO: https://github.com/riscv/riscv-tests.git
TEST_BRANCH: master
TEST_HASH: f92842f91644092960ac7946a61ec2895e543cec
TESTS_BRANCH: master
TESTS_HASH: f92842f91644092960ac7946a61ec2895e543cec
DV_REPO: https://github.com/google/riscv-dv.git
DV_BRANCH: master
NUM_JOBS: 24

4
.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml
View file

@ -16,8 +16,8 @@ variables:
COMPLIANCE_HASH: 220e78542da4510e40eac31e31fdd4e77cdae437
COMPLIANCE_PATCH: ../../../cva6/riscv-compliance.patch
TESTS_REPO: https://github.com/riscv/riscv-tests.git
TEST_BRANCH: master
TEST_HASH: f92842f91644092960ac7946a61ec2895e543cec
TESTS_BRANCH: master
TESTS_HASH: f92842f91644092960ac7946a61ec2895e543cec
DV_REPO: https://github.com/google/riscv-dv.git
DV_BRANCH: master
NUM_JOBS: 24

4
bin/ci_check
View file

@ -47,7 +47,7 @@ import subprocess
import pprint
import yaml
import re
import distutils.spawn
import shutil
if (sys.version_info < (3,0,0)):
print ('Requires python 3')
@ -243,7 +243,7 @@ if (args.verilator):
elif (args.simulator == None):
print ('Must specify a simulator. Type `ci_check -h` to see how')
exit(0)
elif (not(distutils.spawn.find_executable(args.simulator))):
elif (not(shutil.which(args.simulator))):
print ('ERROR: simulator='+args.simulator+' but executable not found')
exit(0)
else:

3
cv32e40p/bsp/Makefile
View file

@ -6,7 +6,7 @@ RISCV_AR = $(RISCV_EXE_PREFIX)ar
SRC = crt0.S handlers.S syscalls.c vectors.S
OBJ = crt0.o handlers.o syscalls.o vectors.o
LIBCV-VERIF = libcv-verif.a
CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(RISCV_MARCH) -Wall -pedantic
CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(CV_SW_MARCH) -Wall -pedantic
all: $(LIBCV-VERIF)
@ -26,6 +26,7 @@ clean:
vars:
@echo "make bsp variables:"
@echo " CV_SW_TOOLCHAIN = $(CV_SW_TOOLCHAIN)"
@echo " CV_SW_MARCH = $(CV_SW_MARCH)"
@echo " RISCV = $(RISCV)"
@echo " RISCV_EXE_PREFIX = $(RISCV_EXE_PREFIX)"
@echo " RISCV_GCC = $(RISCV_GCC)"

222
cva6/docs/UVM_verif_env.md Normal file
View file

@ -0,0 +1,222 @@
<!--_ Copyright (c) 2023 10x-Engineers
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-->
# The CVA6 UVM Verification Environment
This document describes the uvm verification environment of the CVA6 core. This environment is intended to be able to verify the CVA6 core and run different test cases by the minimal modification to the environment itself. The environment is shown below:
![alt_text](images/CVA6_env.drawio.drawio.png "image_tooltip")
***
This environment consist of the following
1. Simple two uvm agents for the uvma_clknrst_if and uvma_cvxif_intf .
2. Result checking capability is built into the environment so the test cases do not need to determine and check for the pass/fail criteria.
The environment consists of disjoint components. When a user invokes a command to run a test case a set of scripts and makefile rules are invoked to compile the environment and tests, run the simulation and check the results. On running a particular test it generates a .bin file which then is loaded into the main memory in the tb_top at the Boot_address of the core and the instructions are then start executing.
## uvmt_cva6_tb
In this module we instantiate the agent interfaces and the `uvmt_cva6_dut_wrap` module. We set the interfaces for the uvma_clknrst and uvma_cvxif using the configuration database set method. In this module we get the `sim_finished` database object set in the `uvmt_cva6_base_test_c` class. To check whether the simulation passed or failed we check the `err_count` and `fatal_count` along with `sim_finished`.
## uvmt_cva6_base_test_c
This class extends from `uvm_test`. It randomise the `uvmt_cva6_test_cfg_c` and `uvme_cva6_cfg_c` objects. The class's build_phase, connect_phase functions handle the setup and configuration of the testbench environment, connecting it to the CVA6, and executing the test. We start the `uvme_cva6_reset_vseq_c` sequence in the reset phase on the `uvme_cva6_vsqr_c` sequencer.
## uvme_cva6_env_c
This class extends from the `uvm_env` class. The class's build_phase,connect_phase functions handle the setup and configuration of the `uvma_clknrst_agent_c`,`uvma_cvxif_agent_c` agents.The class's run_phase task start the `cvxif_seq` sequence on the uvma_cvxif_agent sequencer. We get the configuration and context information for the environment in this class using the get method.
### Environment_objects
There are two uvm_objects that are `uvme_cva6_cfg_c` and `uvme_cva6_cntxt_c`. The Objects contain configuration and context information for the environment.
### uvme_cva6_cfg_c
This class extends from the `uvm_object` class. The object encapsulates all parameters for creating, connecting and running CVA6 environment (`uvme_cva6_env_c`) components. This class also includes a constraint block that defines default values for some of its fields and other constraints on its fields such as, `enabled` and `is_active` fields are set to 0 and 'UVM_PASSIVE' respectively by default. `clknrst_cfg.enabled` and `clknrst_cfg.is_active` are set to 1 if `enabled` and `is_active` fields are set to 1. `clknrst_cfg.trn_log_enabled` is set to 1 if `trn_log_enabled` is set to 1. `cvxif_cfg.cov_model_enabled` is set to 1 if `cov_model_enabled` is set to 1.
<table>
<tr>
<td><strong>signal</strong>
</td>
<td><strong>Description</strong>
</td>
</tr>
<tr>
<td>enabled
</td>
<td> is set to 1, the environment is enabled and the components within the environment can be instantiated, built, and connected.
</td>
</tr>
<tr>
<td>is_active
</td>
<td>This is set to UVM_PASSIVE.
</td>
</tr>
<tr>
<td>scoreboarding_enabled
</td>
<td> It enables the scoreboard and predictor in the environment class.
</td>
</tr>
<tr>
<td>cov_model_enabled
</td>
<td> It enables the coverage collection for environment and cvxif_agent.
</td>
</tr>
<tr>
<td>trn_log_enabled
</td>
<td> It enables the trace log for the clk_rst_agent
</td>
</tr>
</table>
### uvme_cva6_cntxt_c
The class uvme_cva6_cntxt_c is an object that encapsulates all state variables for CVA6 environment (`uvme_cva6_env_c`) components. It inherits from the `uvm_object` base class.It also contains two events, `sample_cfg_e` and `sample_cntxt_e`, that can be used to synchronize the sampling of configuration and context information.
### uvme_cva6_vsqr_c
This class extends from the `uvm_sequencer` base class. It also has two sequencer handles, "clknrst_sequencer" and "cvxif_sequencer" of the types `uvma_clknrst_sqr_c` and `uvma_cvxif_sqr_c`, respectively. This class is used to start the virtual sequence.
### uvme_cva6_reset_vseq_c
This class `uvme_cva6_reset_vseq_c` extends a class called `uvme_cva6_base_vseq_c`. The purpose of this sequence is to start the system clock and issue the initial reset pulse to the Device Under Test (DUT). The class has three random variables, `num_clk_before_reset`, `rst_deassert_period`, and `post_rst_wait`. These variables are used to specify the number of clock cycles between the start of the clock and the reset assert.The class has a default constructor and a virtual task called "body" which is responsible for starting the clock, waiting for a specified amount of time, and then resetting the DUT.
## Clock & Reset Agent
This agent controls the clock and reset signal of the CVA6 core.
### uvma_clknrst_if
The `uvma_clknrst_if` interface has two logic signals, `clk` and `reset_n`. The `clk` signal represents the system clock, while the `reset_n` signal is the active-low reset signal.The interface includes an initial block that contains a forever loop that generates the clock signal, based on the value of `clk_active` and `clk_period`. If `clk_active` is set to 1 and `clk_period` is 0, the function will raise a fatal error. The interface also includes three functions: set_period, which sets the value of `clk_period`; start_clk, which sets `clk_active` to 1; and stop_clk, which sets `clk_active` to 0.
<table>
<tr>
<td><strong>signal</strong>
</td>
<td><strong>Description</strong>
</td>
</tr>
<tr>
<td>clk
</td>
<td>Controls the Clock fed to the design under test.
</td>
</tr>
<tr>
<td>reset_n
</td>
<td>Control the reset state of the design under test.
</td>
</tr>
</table>
### uvma_clknrst_uvm_objects
The uvm_objects `uvma_clknrst_cfg_c` , `uvma_clknrst_cntxt_c` contain the configuration and context information of the uvma_clknrst_agent.
### uvma_clknrst_seq_item_c
The class represents an object created by Clock & Reset agent sequences that extend the `uvma_clknrst_seq_base_c` class.
The class contains several randomized variables:
* `action` is an enumerated variable of type "uvma_clknrst_seq_item_action_enum" that represents the operation to perform (e.g. start clock, stop clock, assert reset, de-assert reset).
* `initial_value` is an enumerated variable of type "uvma_clknrst_seq_item_initial_value_enum" that represents the initial value of the signals (if starting or asserting).
* `clk_period` is an unsigned 32-bit integer variable representing the period of the clock signal.
* `rst_deassert_period` is an unsigned 32-bit integer variable representing the amount of time (in picoseconds) after which to de-assert reset.
* The class also includes a constraint "default_cons" which sets the default values for `clk_period` to 0 and `rst_deassert_period` to a value defined by `uvma_clknrst_default_rst_deassert_period`
The class has a default constructor which calls the superclass constructor.
### uvma_clknrst_Sequence
It consists of two main sequences: `uvma_clknrst_stop_clk_seq_c` and `uvma_clknrst_restart_clk_seq_c`.
* The `uvma_clknrst_stop_clk_seq_c` create an instance of the `uvma_clknrst_seq_item_c` and set the its action to the `UVMA_CLKNRST_SEQ_ITEM_ACTION_STOP_CLK` and start and finish the item.
* The `uvma_clknrst_restart_clk_seq_c` create an instance of the `uvma_clknrst_seq_item_c` and set the its action to the `UVMA_CLKNRST_SEQ_ITEM_ACTION_RESTART_CLK` and start and finish the item.
### uvma_clknrst_drv_c
This class `uvma_clknrst_drv_c` is used for driving the interface of the clknrst agent. It get reqs from the sequence item port and calls the `drv_req` task. The `drv_req` task drives the virtual interface's (`cntxt.vif`) signals using req's contents. And then call the write method for the analysis port to send the req transaction to the coverage model.
### uvma_clknrst_mon_c
This class `uvma_clknrst_mon_c` is used for monitoring the virtual interface of the Clock & Reset agent. The class extends the `uvm_monitor` class and contains objects for configuration (cfg) and context (cntxt), as well as an analysis port (ap) for transaction analysis.The run_phase() task in the `uvma_clknrst_mon_c` class is responsible for overseeing the monitoring process of the Clock and Reset virtual interface. It does this by executing the monitor_clk() and monitor_reset() tasks in parallel forks.
### uvma_clknrst_cov_model_c
This class `uvma_clknrst_cov_model_c` extends from the `uvm_component` base class. The overall functionality of this class is to provide the coverage model for the clknrst_agent. It contains objects for configuration, context, monitor transaction, and sequence item, as well as two analysis FIFOs for holding transactions coming from the monitor and sequence item respectively. This section is in progress.
### uvma_clknrst_agent_c
This class `uvma_clknrst_agent_c` extends from `uvm_agent` base class. This class encapsulates ,builds and connects all the other components for driving and monitoring a Clock & reset interface. This class gets the `cfg` , `cntxt` using configuration database get method. It creates a driver,monitor,cov_model and sequencer. This class connects the driver with a sequencer.
## Cvxif Agent
Cv-xif agent supports custom instructions. Upon receiving the issue request it drives the response one clock cycle after the issue request.
### uvma_cvxif_intf
The interface includes inputs for clock and reset_n signal, as well as two data input/output called `cvxif_req_i` and `cvxif_resp_o`. It includes a clocking block for the monitor `monitor_cb` to sample the `cvxif_req_i` and `cvxif_resp_o` signal at the rising edge of the clock.
<table>
<tr>
<td><strong>Enum Variable</strong>
</td>
<td><strong>Description</strong>
</td>
</tr>
<tr>
<td> Cvxif_req_i
</td>
<td>The request is send to get a response
</td>
</tr>
<tr>
<td>Cvxif_resp_o
</td>
<td>The response is generated according to the request.
</td>
</tr>
</table>
### uvma_cvxif_uvm_objects
There are two uvm_objects `uvma_cvxif_cfg_c` and `uvma_cvxif_cntxt_c`. `uvma_cvxif_cfg_c` encapsulates all the parameters for creating ,connecting and running the `uvma_cvxif_agent_c` agent . `uvma_cvxif_cntxt_c` confine all the state variables for all the CVXIF agent components.
### uvma_cvxif_Sequence_items
Cvxif agent has two sequence items one `uvma_cvxif_req_item_c`and `uvma_cvxif_resp_item_c` for the request and response transaction.
### uvma_cvxif_sqr_c
`uvma_cvxif_sqr_c` class extends from `uvm_sequencer` base class. It is a typical sequencer. This class instantiates a FIFO to receive the `uvma_cvxif_req_item_c`.
### uvma_cvxif_sequences
* `uvma_cvxif_base_seq_c` class extends from `uvm_sequence` . This class simply implements a decode function that checks whether the instructions are legal or illegal.
* `uvma_cvxif_seq_c` class extends from `uvma_cvxif_base_seq_c` class. This class gets the `uvma_cvxif_req_item_c` from the FIFO in sequencer using the p_sequencer handle. In this sequence class, we send the response according to the request item received . If we receive an instruction from the req_item that is illegal then we drive zero's on the response signals. Otherwise we drive response accordingly.
### uvma_cvxif_drv_c
This class `uvma_cvxif_drv_c` extends from the `uvm_driver` class. This class has several tasks that perform different actions such as generating a random ready signal, getting response_item, driving an issue response to the `VIF` , driving results in order and out of order fashion, and de-asserting signals.
### uvma_cvxif_mon_c
`uvma_cvxif_mon_c` class extends from the `uvm_monitor` . It monitors the virtual interface `vif`. It monitors transaction requests and responses, and sends transaction requests to `uvma_cvxif_sqr_c` and responses to the coverage model. It has several fields, including objects for configuration and context, and analysis ports for transaction requests and responses.
### uvma_cvxif_cov_model_c
`uvma_cvxif_cov_model_c` is derived from the `uvm_component` class. This class defines various objects and covergroups with different coverpoints, and it also uses the UVM library to sample these coverpoints and measure coverage.The main purpose of this class is to measure the functional coverage of a specific interface in the design and ensure that it has been fully tested.
### uvma_cvxif_agent_c
`uvma_cvxif_agent_c` class extends from `uvm_agent` class. This class represents an agent that is responsible for the test execution and communication between the virtual interface (VIF) and the testbench components. The main role of this class is to create and connect the different components of the testbench and manage the communication between them and the virtual interface (VIF) during the test execution.

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!Feature
next_elt_id: 2
name: Burst
id: 5
display_order: 5
subfeatures: !!omap
- 000_Control_Signals: !Subfeature
name: 000_Control_Signals
tag: VP_IP005_P000
next_elt_id: 12
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_1_F005_S000_I000
description: All transaction performed by CVA6 are of type INCR. AxBURST =
0b01
reqt_doc: AXI Design doc - Address structure
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that AxBURST == 0b01 is always true while AX_VALID is
asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_1_F005_S000_I001
description: All Read transaction performed by CVA6 are of burst lenght less
or equal to 2. ARLEN = 0b01
reqt_doc: AXI Design doc - Address structure
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that ARLEN == 0b01 is always true while AR_VALID is asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_1_F005_S000_I002
description: All write transaction performed by CVA6 are of burst lenght equal
to 1. AWLEN = 0b00
reqt_doc: AXI Design doc - Address structure
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that AWLEN == 0b00 is always true while AW_VALID is asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_1_F005_S000_I003
description: The size of a read transfer does not exceed the width of the
data interface. The maximum value can be taking by AxSIZE is 3.
reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.4.1)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that AxSIZE <= log2(AXI_DATA_WIDTH/8) is always true while
AR_VALID is asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- '007': !VerifItem
name: '007'
tag: VP_1_F005_S000_I007
description: Exclusive access transactions cannot have a length greater than
16 beats
reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A7.2.4)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that AxLOCK && AxLEN <= 15 is always true while AX_VALID
is asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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!Feature
next_elt_id: 9
name: Signals
id: 6
display_order: 6
subfeatures: !!omap
- 000_ID: !Subfeature
name: 000_ID
tag: VP_IP006_P000
next_elt_id: 3
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_1_F006_S000_I000
description: The CVA6 identify read transaction with an ID equal to 0 or 1
reqt_doc: AXI Design doc - Transaction Identifiers
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that ARID == 0b01 || ARID == 0b00 is always true while
AR_VALID is asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_1_F006_S000_I001
description: The CVA6 identify write transaction with an ID equal to 1
reqt_doc: AXI Design doc - Transaction Identifiers
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that AWID == 0b01 is always true while AW_VALID is asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- 001_User: !Subfeature
name: 001_User
tag: VP_IP006_P001
next_elt_id: 2
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_1_F006_S001_I000
description: User-defined extension for the write and read address channel
is not supported. AxUSER = 0b00
reqt_doc: AXI Design doc - (table 2.2 and 2.5)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that AxUSER = 0b00 is always true while AX_VALID is asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_1_F006_S001_I001
description: User-defined extension for the write response channel is not
supported.
reqt_doc: AXI Design doc - (table 2.4)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that BUSER = 0b00 is always true while B_VALID is asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- 002_Quality_of_Service: !Subfeature
name: 002_Quality_of_Service
tag: VP_IP006_P002
next_elt_id: 2
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_1_F006_S002_I000
description: Quality of Service identifier is not supported. AxQOS = 0b0000
reqt_doc: AXI Design doc - (table 2.2 and 2.5)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that AxQOS = 0b0000 is always true while AX_VALID is asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- 003_Cache: !Subfeature
name: 003_Cache
tag: VP_IP006_P003
next_elt_id: 2
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_1_F006_S003_I000
description: AxCACHE always take 0b0000.
reqt_doc: 'AXI Design Doc - Transaction Attributes: Memory types'
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that AxCACHE = 0b0000 is always true while AX_VALID is
asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- 004_Protection: !Subfeature
name: 004_Protection
tag: VP_IP006_P004
next_elt_id: 1
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_1_F006_S004_I000
description: Protection attributes always take the 0b000
reqt_doc: AXI Design Doc - (Table 2.2 and 2.5)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that AxPROT = 0b000 is always true while AX_VALID is asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- 008_Region: !Subfeature
name: 008_Region
tag: VP_IP006_P008
next_elt_id: 1
display_order: 8
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_1_F006_S008_I000
description: Region indicator is not supported. AxREGION = 0b0000
reqt_doc: AXI Design doc - (table 2.2 and 2.5)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that AxREGION = 0b0000 is always true while AX_VALID is
asserted.
pfc: 4
test_type: 3
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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!Feature
next_elt_id: 1
name: Clock and Reset
id: 7
display_order: 7
subfeatures: !!omap
- 000_Signals_Value: !Subfeature
name: 000_Signals_Value
tag: VP_IP007_P000
next_elt_id: 3
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_1_F007_S000_I000
description: A value of X on [Ax | x]VALID is not permitted when not in reset
reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that reset && [Ax | x]VALID != X is always true
pfc: 4
test_type: 4
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_1_F007_S000_I001
description: A value of X on [Ax | x]READY is not permitted when not in reset
reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that reset && [Ax | x]READY != X is always true
pfc: 4
test_type: 4
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_1_F007_S000_I002
description: '[Ax | x]VALID is LOW for the first cycle after RESET goes HIGH'
reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Figure A3-1)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that [Ax | x]VALID is low the first cycle after RESET
pfc: 4
test_type: 4
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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!Feature
next_elt_id: 3
name: Handshake_Process
id: 8
display_order: 8
subfeatures: !!omap
- '000_Stability ': !Subfeature
name: '000_Stability '
tag: VP_IP008_P000
next_elt_id: 2
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_1_F008_S000_I000
description: All signals must remain stable when [Ax | x]VALID is asserted
and [Ax | x]READY is LOW
reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.2)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that all the signals does not change while [Ax | x]VALID
is asserted and [Ax | x]READY not yet asserted.
pfc: 4
test_type: 4
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_1_F008_S000_I001
description: '[Ax | x]VALID must remain asserted until [Ax | x]READY is HIGH'
reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.1)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Ensure that [Ax | x]VALID does not change while [Ax | x]READY
is low.
pfc: 4
test_type: 4
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- 001_Timing: !Subfeature
name: 001_Timing
tag: VP_IP008_P001
next_elt_id: 8
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_1_F008_S001_I000
description: The Manager must not wait for the Subordinate to assert ARREADY
before asserting ARVALID
reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "Ensure that no errors are encountered as the testbench injects\
\ random Ready-to-Valid delays. There are two cases to consider:\n\nARREADY\
\ is asserted on or after same cycle as ARVALID\nARREADY is asserted and\
\ deasserted during an interval when ARVALID is de-asserted"
pfc: 0
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_1_F008_S001_I002
description: The Manager must not wait for the Subordinate to assert AWREADY
before asserting AWVALID or WVALID.
reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "Ensure that no errors are encountered as the testbench injects\
\ random Ready-to-Valid delays. There are four cases to consider: \n \
\ \nAWREADY is asserted on or after\
\ same cycle as AWVALID and WVALID is de-asserted\nAWREADY is asserted on\
\ or after same cycle as WVALID and AWVALID is de-asserted\nAWREADY is\
\ asserted on or after same cycle as AWVALID and WVALID\nAWREADY is asserted\
\ and deasserted during an interval when AWVALID and WVALID is de-asserted"
pfc: 0
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_1_F008_S001_I003
description: The Manager must not wait for the Subordinate to assert WREADY
before asserting AWVALID or WVALID.
reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "Ensure that no errors are encountered as the testbench injects\
\ random Ready-to-Valid delays. There are four cases to consider: \n \
\ \nWREADY is asserted on or\
\ after same cycle as AWVALID and WVALID is de-asserted\nWREADY is asserted\
\ on or after same cycle as WVALID and AWVALID is de-asserted\nWREADY is\
\ asserted on or after same cycle as AWVALID and WVALID\nWREADY is asserted\
\ and deasserted during an interval when AWVALID and WVALID is de-asserted"
pfc: 0
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '005': !VerifItem
name: '005'
tag: VP_1_F008_S001_I005
description: The Subordinate must not wait for the Manager to assert [B |
R]READY before asserting [B | R]VALID
reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1)
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: No specific “observable checks” to be made in simulation. Testbench
will always provide response data independently of [B | R]READY.
pfc: 0
test_type: 10
cov_method: 10
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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#############################################################################
# Copyright (C) 2022 Thales DIS France SAS
#
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0.
#
# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com)
#############################################################################
#!/bin/sh
# Location of project-specific directories
ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")`
# Set up platform location. It can be anywhere but should contain
# a valid `vp_config.py` file in `vptool` directory.
# Here we use the verification tree from the example directory.
export PLATFORM_TOP_DIR="$ROOTDIR"
# Set the printable name for the project that will be used
# in the human-readable documentation.
export PROJECT_NAME="AXI"
# Set the alphanumerical identifier of the project that
# will be used to construct file names etc.
export PROJECT_IDENT="AXI"
# Set the destination directory of Markdown files for this project.
# Since it will be used by VPTOOL, it shall NOT be a relative path.
export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"`
# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'.
# FIXME: Introduce a suitably named shell variable that points to the root
# directory of the tool set (TOOL_TOP etc.)
# FORNOW use a hardcoded relative path.
sh $ROOTDIR/../../../../tools/vptool/vptool.sh $*

998
cva6/docs/VerifPlans/CVXIF/VP_IP000.pck Normal file
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@ -0,0 +1,998 @@
(VIssue Interface
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I9
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I0
sVwid_order
p12
I0
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_issue_req signals stable
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I1
sg8
g17
sVtag
p23
VVP_CVXIF_F000_S000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_CVXIF_F000_S000_I000
p34
sVdescription
p35
VThe \u201cinstr\u201d and \u201cmode\u201d signals remain stable during an Issue request transaction.
p36
sVpurpose
p37
V
p38
sVverif_goals
p39
VCheck that \u201cmode\u201d and \u201cinstr\u201d are stable during an issue transaction (cannot be modified by an instruction when transaction issue is in process)
p40
sVcoverage_loc
p41
g38
sVref_mode
p42
Vpage
p43
sVref_page
p44
g38
sVref_section
p45
g38
sVref_viewer
p46
Vfirefox
p47
sVpfc
p48
I4
sVtest_type
p49
I3
sVcov_method
p50
I2
sVcores
p51
I56
sVcomments
p52
g38
sVstatus
p53
g38
sVsimu_target_list
p54
(lp55
sg15
(lp56
sVrfu_list_2
p57
(lp58
sg13
(dp59
Vlock_status
p60
I0
ssbtp61
asVrfu_list_1
p62
(lp63
sg57
(lp64
sg13
(dp65
sbtp66
a(V001_mode signal value
p67
g1
(g18
g3
Ntp68
Rp69
(dp70
g22
I2
sg8
g67
sg23
VVP_CVXIF_F000_S001
p71
sg25
(dp72
sg12
I1
sg15
(lp73
(V000
p74
g1
(g29
g3
Ntp75
Rp76
(dp77
g8
V000
p78
sg23
VVP_CVXIF_F000_S001_I000
p79
sg35
VWhen issue transaction starts, instruction and current CPU mode are provided
p80
sg37
g38
sg39
VCheck that a mode modification coming from execution of a first instruction is well provided to the following offloaded instruction
p81
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I3
sg49
I3
sg50
I1
sg51
I56
sg52
g38
sg53
g38
sg54
(lp82
sg15
(lp83
sg57
(lp84
sg13
(dp85
g60
I0
ssbtp86
a(V001
p87
g1
(g29
g3
Ntp88
Rp89
(dp90
g8
V001
p91
sg23
VVP_CVXIF_F000_S001_I001
p92
sg35
VCheck \u201cmode\u201d signal values.
p93
sg37
g38
sg39
VCheck that mode take a value that the CPU supports : Privilege level (2\u2019b00 = User, 2\u2019b01 = Supervisor, 2\u2019b10 = Reserved,\u000a 2\u2019b11 = Machine).
p94
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I-1
sg49
I-1
sg50
I-1
sg51
I56
sg52
g38
sg53
g38
sg54
(lp95
sg15
(lp96
sg57
(lp97
sg13
(dp98
g60
I0
ssbtp99
asg62
(lp100
sg57
(lp101
sg13
(dp102
sbtp103
a(V002_rs_valid signal transition order
p104
g1
(g18
g3
Ntp105
Rp106
(dp107
g22
I1
sg8
g104
sg23
VVP_CVXIF_F000_S002
p108
sg25
(dp109
sg12
I2
sg15
(lp110
(V000
p111
g1
(g29
g3
Ntp112
Rp113
(dp114
g8
V000
p115
sg23
VVP_CVXIF_F000_S002_I000
p116
sg35
VDuring a transaction, each bit of \u201crs_valid\u201d can transition from 0 to 1 but are not allowed to transition back to 0.
p117
sg37
g38
sg39
VFor issue transaction which lasts more than one cycle, check that asserted \u201crs_valid\u201d signals do not transition back to 0.(for i in [0;2] if rs_valid[i] = 1 then rs_valid[i] \u2192 0 cannot happen)
p118
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I4
sg49
I3
sg50
I2
sg51
I56
sg52
g38
sg53
g38
sg54
(lp119
sg15
(lp120
sg57
(lp121
sg13
(dp122
g60
I0
ssbtp123
asg62
(lp124
sg57
(lp125
sg13
(dp126
sbtp127
a(V003_rs signal value
p128
g1
(g18
g3
Ntp129
Rp130
(dp131
g22
I3
sg8
g128
sg23
VVP_CVXIF_F000_S003
p132
sg25
(dp133
sg12
I3
sg15
(lp134
(V000
p135
g1
(g29
g3
Ntp136
Rp137
(dp138
g8
V000
p139
sg23
VVP_CVXIF_F000_S003_I000
p140
sg35
VIf XLEN = X_RFR_WIDTH, then rs[X_NUM_RS-1:0] correspond to rs1 and rs2 CPU registers (and rs3 if X_NUM_RS = 3).
p141
sg37
g38
sg39
VFor every issue transaction check that rs signal correspond to rs1,rs2(rs3) value in CPU register file.
p142
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I3
sg49
I3
sg50
I1
sg51
I56
sg52
g38
sg53
g38
sg54
(lp143
sg15
(lp144
sg57
(lp145
sg13
(dp146
g60
I0
ssbtp147
a(V001
p148
g1
(g29
g3
Ntp149
Rp150
(dp151
g8
V001
p152
sg23
VVP_CVXIF_F000_S003_I001
p153
sg35
Vrs signals are only required to be stable during the part of a transaction in which these signals are considered to be valid.
p154
sg37
g38
sg39
VCheck that rs signals are stable when issue_valid==1 && the corresponding bit in rs_valid is 1.
p155
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I4
sg49
I-1
sg50
I2
sg51
I56
sg52
g38
sg53
g38
sg54
(lp156
sg15
(lp157
sg57
(lp158
sg13
(dp159
g60
I0
ssbtp160
a(V002
p161
g1
(g29
g3
Ntp162
Rp163
(dp164
g8
V002
p165
sg23
VVP_CVXIF_F000_S003_I002
p166
sg35
VIf XLEN != X_RFR_WIDTH , then rs[X_NUM_RS-1:0] correspond to even/odd register pair with rs1, rs2, (rs3) are even register and even register is provided in the 32 lower bits of rs signal.
p167
sg37
g38
sg39
VFor every issue transaction check that rs signal correspond to the concatenation of rs1/rs1+1,rs2/rs2+1, (rs3/rs3+1) value in CPU register file and even register is in the 32 lower bits of rs.
p168
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I-1
sg49
I-1
sg50
I-1
sg51
I56
sg52
g38
sg53
g38
sg54
(lp169
sg15
(lp170
sg57
(lp171
sg13
(dp172
g60
I0
ssbtp173
asg62
(lp174
sg57
(lp175
sg13
(dp176
sbtp177
a(V004_Default value for unaccepted instruction
p178
g1
(g18
g3
Ntp179
Rp180
(dp181
g22
I1
sg8
g178
sg23
VVP_CVXIF_F000_S004
p182
sg25
(dp183
sg12
I4
sg15
(lp184
(V000
p185
g1
(g29
g3
Ntp186
Rp187
(dp188
g8
V000
p189
sg23
VVP_CVXIF_F000_S004_I000
p190
sg35
VIf accept == 0 :\u000aWriteback == 0; dualwrite == 0; dualread == 0; loadstore == 0; exc = 0.
p191
sg37
g38
sg39
VCheck that for writeback; dualwrite; dualread; loadstore; exc signals if accept == 0 then all those signals are 0.
p192
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I4
sg49
I3
sg50
I2
sg51
I56
sg52
g38
sg53
g38
sg54
(lp193
sg15
(lp194
sg57
(lp195
sg13
(dp196
g60
I0
ssbtp197
asg62
(lp198
sg57
(lp199
sg13
(dp200
sbtp201
a(V005_Illegal Instruction causes
p202
g1
(g18
g3
Ntp203
Rp204
(dp205
g22
I1
sg8
g202
sg23
VVP_CVXIF_F000_S005
p206
sg25
(dp207
sg12
I5
sg15
(lp208
(V000
p209
g1
(g29
g3
Ntp210
Rp211
(dp212
g8
V000
p213
sg23
VVP_CVXIF_F000_S005_I000
p214
sg35
VThe CPU shall cause an illegal instruction if:\u000a- an instruction is considered to be valid by the CPU and accepted by the coprocessor (accept = 1)\u000a- neither to be valid by the CPU nor accepted by the coprocessor (accept = 0)
p215
sg37
g38
sg39
V- CPU causes illegal instruction for instruction accepted by the core and the coprocessor.\u000a- CPU causes illegal instruction exception for instruction that are not valid for coprocessor and CPU
p216
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I3
sg49
I3
sg50
I1
sg51
I56
sg52
g38
sg53
g38
sg54
(lp217
sg15
(lp218
sg57
(lp219
sg13
(dp220
g60
I0
ssbtp221
asg62
(lp222
sg57
(lp223
sg13
(dp224
sbtp225
a(V006_issue uniquness
p226
g1
(g18
g3
Ntp227
Rp228
(dp229
g22
I1
sg8
g226
sg23
VVP_CVXIF_F000_S006
p230
sg25
(dp231
sg12
I6
sg15
(lp232
(V000
p233
g1
(g29
g3
Ntp234
Rp235
(dp236
g8
V000
p237
sg23
VVP_CVXIF_F000_S006_I000
p238
sg35
VCheck for issue id validity.
p239
sg37
g38
sg39
VCheck that the issue interface doesn't issue an "id" that isn't legal to be used (has not fully completed).
p240
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I11
sg49
I3
sg50
I10
sg51
I56
sg52
g38
sg53
g38
sg54
(lp241
sg15
(lp242
sg57
(lp243
sg13
(dp244
g60
I0
ssbtp245
asg62
(lp246
sg57
(lp247
sg13
(dp248
sbtp249
a(V007_coprocessor decoding
p250
g1
(g18
g3
Ntp251
Rp252
(dp253
g22
I1
sg8
g250
sg23
VVP_CVXIF_F000_S007
p254
sg25
(dp255
sg12
I7
sg15
(lp256
(V000
p257
g1
(g29
g3
Ntp258
Rp259
(dp260
g8
V000
p261
sg23
VVP_CVXIF_F000_S007_I000
p262
sg35
VAccept = 1 if: \u000a- coprocessor can handle the instruction based on decoding \u201cinstr\u201dand "mode".\u000a- \u201cissue_valid\u201d == 1 and required bit(s) of \u201crs_valid\u201d are 1.
p263
sg37
g38
sg39
VTo be checked in coprocessor.
p264
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I3
sg49
I3
sg50
I1
sg51
I56
sg52
g38
sg53
g38
sg54
(lp265
sg15
(lp266
sg57
(lp267
sg13
(dp268
g60
I0
ssbtp269
asg62
(lp270
sg57
(lp271
sg13
(dp272
sbtp273
a(V008_Transaction definition
p274
g1
(g18
g3
Ntp275
Rp276
(dp277
g22
I1
sg8
g274
sg23
VVP_CVXIF_F000_S008
p278
sg25
(dp279
sg12
I8
sg15
(lp280
(V000
p281
g1
(g29
g3
Ntp282
Rp283
(dp284
g8
V000
p285
sg23
VVP_CVXIF_F000_S008_I000
p286
sg35
V\u201cissue_resp\u201d signals and \u201cissue_req\u201d signals are accepted when \u201cissue_valid\u201d == \u201cissue_ready\u201d == 1\u000a\u201cissue_resp\u201d is valid when "valid==ready==1".\u000a\u201cissue_req\u201d is valid when "valid==1"
p287
sg37
g38
sg39
VThe definition of a transaction. \u000aNot to be verified.
p288
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I11
sg49
I10
sg50
I10
sg51
I56
sg52
g38
sg53
g38
sg54
(lp289
sg15
(lp290
sg57
(lp291
sg13
(dp292
g60
I0
ssbtp293
asg62
(lp294
sg57
(lp295
sg13
(dp296
sbtp297
asVrfu_list_0
p298
(lp299
sg62
(lp300
sVvptool_gitrev
p301
V$Id: a782de3eec3de5ff99661fb165c09f541b4228d0 $
p302
sVio_fmt_gitrev
p303
V$Id: 2f6f9e7bc800d8b831382463dc706473c6c6ad8c $
p304
sVconfig_gitrev
p305
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p306
sVymlcfg_gitrev
p307
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p308
sbtp309
.

418
cva6/docs/VerifPlans/CVXIF/VP_IP001.pck Normal file
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@ -0,0 +1,418 @@
(VCommit Interface
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I4
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I1
sVwid_order
p12
I1
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_commit_valid pulse
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I1
sg8
g17
sVtag
p23
VVP_CVXIF_F001_S000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_CVXIF_F001_S000_I000
p34
sVdescription
p35
VThe \u201ccommit_valid\u201d == 1 exactly one clk cycle for every offloaded Instruction by the coprocessor (whether accepted or not).
p36
sVpurpose
p37
V
p38
sVverif_goals
p39
VFor every offloaded instruction, check that commit_valid is asserted exactly one clk cycle ( is a pulse ).
p40
sVcoverage_loc
p41
g38
sVref_mode
p42
Vpage
p43
sVref_page
p44
g38
sVref_section
p45
g38
sVref_viewer
p46
Vfirefox
p47
sVpfc
p48
I4
sVtest_type
p49
I3
sVcov_method
p50
I2
sVcores
p51
I56
sVcomments
p52
g38
sVstatus
p53
g38
sVsimu_target_list
p54
(lp55
sg15
(lp56
sVrfu_list_2
p57
(lp58
sg13
(dp59
Vlock_status
p60
I0
ssbtp61
asVrfu_list_1
p62
(lp63
sg57
(lp64
sg13
(dp65
sbtp66
a(V001_commit transaction uniquness
p67
g1
(g18
g3
Ntp68
Rp69
(dp70
g22
I1
sg8
g67
sg23
VVP_CVXIF_F001_S001
p71
sg25
(dp72
sg12
I1
sg15
(lp73
(V000
p74
g1
(g29
g3
Ntp75
Rp76
(dp77
g8
V000
p78
sg23
VVP_CVXIF_F001_S001_I000
p79
sg35
VThere is a unique commit transaction for every issue transaction (unique until an instruction has "fully completed" = its result has been submitted).
p80
sg37
g38
sg39
VCheck that the commit interface doesn't commit an "id" that isn't legal to be used (hasn't been seen in earlier stages, or has not fully completed).
p81
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I1
sg49
I10
sg50
I10
sg51
I56
sg52
g38
sg53
g38
sg54
(lp82
sg15
(lp83
sg57
(lp84
sg13
(dp85
g60
I0
ssbtp86
asg62
(lp87
sg57
(lp88
sg13
(dp89
sbtp90
a(V002_commit transaction for every issue transaction
p91
g1
(g18
g3
Ntp92
Rp93
(dp94
g22
I1
sg8
g91
sg23
VVP_CVXIF_F001_S002
p95
sg25
(dp96
sg12
I2
sg15
(lp97
(V000
p98
g1
(g29
g3
Ntp99
Rp100
(dp101
g8
V000
p102
sg23
VVP_CVXIF_F001_S002_I000
p103
sg35
V- The CPU shall perform a commit transaction for every issue transaction, independent of the accept value of the issue transaction.\u000a- For each offloaded and accepted instruction the core is guaranteed to (eventually) signal that such an instruction is either no longer speculative and can be committed (commit_valid is 1 and commit_kill is 0) or that the instruction must be killed (commit_valid is 1 and commit_kill is 1).
p104
sg37
g38
sg39
VCheck that for each issue transaction, the commit transaction is sent at the same clock cycle than the issue transaction, or at any clock cycle after the issue transaction.
p105
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I4
sg49
I3
sg50
I2
sg51
I56
sg52
g38
sg53
g38
sg54
(lp106
sg15
(lp107
sg57
(lp108
sg13
(dp109
g60
I0
ssbtp110
asg62
(lp111
sg57
(lp112
sg13
(dp113
sbtp114
a(V003_Transaction definition
p115
g1
(g18
g3
Ntp116
Rp117
(dp118
g22
I1
sg8
g115
sg23
VVP_CVXIF_F001_S003
p119
sg25
(dp120
sg12
I3
sg15
(lp121
(V000
p122
g1
(g29
g3
Ntp123
Rp124
(dp125
g8
V000
p126
sg23
VVP_CVXIF_F001_S003_I000
p127
sg35
VThe signals in commit are valid when commit_valid is 1.
p128
sg37
g38
sg39
VThe definition of a transaction.\u000aNot to be verified.
p129
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I11
sg49
I-1
sg50
I10
sg51
I56
sg52
g38
sg53
g38
sg54
(lp130
sg15
(lp131
sg57
(lp132
sg13
(dp133
g60
I0
ssbtp134
asg62
(lp135
sg57
(lp136
sg13
(dp137
sbtp138
asVrfu_list_0
p139
(lp140
sg62
(lp141
sVvptool_gitrev
p142
V$Id: a782de3eec3de5ff99661fb165c09f541b4228d0 $
p143
sVio_fmt_gitrev
p144
V$Id: 2f6f9e7bc800d8b831382463dc706473c6c6ad8c $
p145
sVconfig_gitrev
p146
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p147
sVymlcfg_gitrev
p148
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p149
sbtp150
.

860
cva6/docs/VerifPlans/CVXIF/VP_IP002.pck Normal file
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@ -0,0 +1,860 @@
(VResult Interface
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I8
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I2
sVwid_order
p12
I2
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_no speculative result transaction
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I1
sg8
g17
sVtag
p23
VVP_CVXIF_F002_S000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_CVXIF_F002_S000_I000
p34
sVdescription
p35
VA coprocessor is not allowed to perform speculative result transactions.
p36
sVpurpose
p37
V
p38
sVverif_goals
p39
VThere is no result transaction for instructions that haven't been committed. Check that Result valid is only asserted for instructions that were committed (commit_valid == 1 && commit_kill == 0).
p40
sVcoverage_loc
p41
g38
sVref_mode
p42
Vpage
p43
sVref_page
p44
g38
sVref_section
p45
g38
sVref_viewer
p46
Vfirefox
p47
sVpfc
p48
I11
sVtest_type
p49
I10
sVcov_method
p50
I10
sVcores
p51
I56
sVcomments
p52
g38
sVstatus
p53
g38
sVsimu_target_list
p54
(lp55
sg15
(lp56
sVrfu_list_2
p57
(lp58
sg13
(dp59
Vlock_status
p60
I0
ssbtp61
asVrfu_list_1
p62
(lp63
sg57
(lp64
sg13
(dp65
sbtp66
a(V001_out of order result transaction
p67
g1
(g18
g3
Ntp68
Rp69
(dp70
g22
I1
sg8
g67
sg23
VVP_CVXIF_F002_S001
p71
sg25
(dp72
sg12
I1
sg15
(lp73
(V000
p74
g1
(g29
g3
Ntp75
Rp76
(dp77
g8
V000
p78
sg23
VVP_CVXIF_F002_S001_I000
p79
sg35
VA coprocessor is allowed to provide results to the core in an out of order fashion.
p80
sg37
g38
sg39
VCheck that the CPU is able to receive the result in an out of order fashion.
p81
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I3
sg49
I3
sg50
I1
sg51
I56
sg52
g38
sg53
g38
sg54
(lp82
sg15
(lp83
sg57
(lp84
sg13
(dp85
g60
I0
ssbtp86
asg62
(lp87
sg57
(lp88
sg13
(dp89
sbtp90
a(V002_result transaction uniquness
p91
g1
(g18
g3
Ntp92
Rp93
(dp94
g22
I1
sg8
g91
sg23
VVP_CVXIF_F002_S002
p95
sg25
(dp96
sg12
I2
sg15
(lp97
(V000
p98
g1
(g29
g3
Ntp99
Rp100
(dp101
g8
V000
p102
sg23
VVP_CVXIF_F002_S002_I000
p103
sg35
VEach accepted offloaded (committed and not killed) instruction shall have exactly one result group transaction (even if no data needs to be written back to the CPU\u2019s register file).
p104
sg37
g38
sg39
VThere is an unique result transaction for every accepted and commit instruction.
p105
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I11
sg49
I10
sg50
I10
sg51
I56
sg52
g38
sg53
g38
sg54
(lp106
sg15
(lp107
sg57
(lp108
sg13
(dp109
g60
I0
ssbtp110
asg62
(lp111
sg57
(lp112
sg13
(dp113
sbtp114
a(V003_result packet stability
p115
g1
(g18
g3
Ntp116
Rp117
(dp118
g22
I1
sg8
g115
sg23
VVP_CVXIF_F002_S003
p119
sg25
(dp120
sg12
I3
sg15
(lp121
(V000
p122
g1
(g29
g3
Ntp123
Rp124
(dp125
g8
V000
p126
sg23
VVP_CVXIF_F002_S003_I000
p127
sg35
VThe signals in result shall remain stable during a result transaction (except data ...)
p128
sg37
g38
sg39
VCheck that result signals (except data) are stable during result transaction (result_valid==1 jusqu'à valid==ready ==1)
p129
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I4
sg49
I3
sg50
I2
sg51
I56
sg52
g38
sg53
g38
sg54
(lp130
sg15
(lp131
sg57
(lp132
sg13
(dp133
g60
I0
ssbtp134
asg62
(lp135
sg57
(lp136
sg13
(dp137
sbtp138
a(V004_data stability
p139
g1
(g18
g3
Ntp140
Rp141
(dp142
g22
I1
sg8
g139
sg23
VVP_CVXIF_F002_S004
p143
sg25
(dp144
sg12
I4
sg15
(lp145
(V000
p146
g1
(g29
g3
Ntp147
Rp148
(dp149
g8
V000
p150
sg23
VVP_CVXIF_F002_S004_I000
p151
sg35
VData is only required to remain stable during result transactions in which "we" is not 0.
p152
sg37
g38
sg39
VCheck that "data" remains stable when we==1.
p153
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I4
sg49
I3
sg50
I2
sg51
I56
sg52
g38
sg53
g38
sg54
(lp154
sg15
(lp155
sg57
(lp156
sg13
(dp157
g60
I0
ssbtp158
asg62
(lp159
sg57
(lp160
sg13
(dp161
sbtp162
a(V005_synchronous exception
p163
g1
(g18
g3
Ntp164
Rp165
(dp166
g22
I3
sg8
g163
sg23
VVP_CVXIF_F002_S005
p167
sg25
(dp168
sg12
I5
sg15
(lp169
(V000
p170
g1
(g29
g3
Ntp171
Rp172
(dp173
g8
V000
p174
sg23
VVP_CVXIF_F002_S005_I000
p175
sg35
VThe exc is used to signal synchronous exceptions. A synchronous exception will lead to a trap in CPU unless the corresponding instruction is killed.
p176
sg37
g38
sg39
VCheck that synchronous exception (exc ==1) leads to a trap in the CPU if the instruction is committed.
p177
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I3
sg49
I3
sg50
I1
sg51
I56
sg52
g38
sg53
g38
sg54
(lp178
sg15
(lp179
sg57
(lp180
sg13
(dp181
g60
I0
ssbtp182
a(V001
p183
g1
(g29
g3
Ntp184
Rp185
(dp186
g8
V001
p187
sg23
VVP_CVXIF_F002_S005_I001
p188
sg35
Vexccode provides the least significant bits of the exception code bitfield of the mcause CSR.
p189
sg37
g38
sg39
VCheck that exccode signal is the value of the mcause CSR when exc == 1.
p190
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I-1
sg49
I-1
sg50
I-1
sg51
I56
sg52
g38
sg53
g38
sg54
(lp191
sg15
(lp192
sg57
(lp193
sg13
(dp194
g60
I0
ssbtp195
a(V002
p196
g1
(g29
g3
Ntp197
Rp198
(dp199
g8
V002
p200
sg23
VVP_CVXIF_F002_S005_I002
p201
sg35
V "we" shall be driven to 0 by the coprocessor for synchronous exceptions.
p202
sg37
g38
sg39
VCheck that "we" signal == 0 when exc == 1.
p203
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I4
sg49
I-1
sg50
I2
sg51
I56
sg52
g38
sg53
g38
sg54
(lp204
sg15
(lp205
sg57
(lp206
sg13
(dp207
g60
I0
ssbtp208
asg62
(lp209
sg57
(lp210
sg13
(dp211
sbtp212
a(V006_"we" value when dualwrite
p213
g1
(g18
g3
Ntp214
Rp215
(dp216
g22
I1
sg8
g213
sg23
VVP_CVXIF_F002_S006
p217
sg25
(dp218
sg12
I6
sg15
(lp219
(V000
p220
g1
(g29
g3
Ntp221
Rp222
(dp223
g8
V000
p224
sg23
VVP_CVXIF_F002_S006_I000
p225
sg35
Vwe is 2 bits wide when XLEN` = 32 and X_RFW_WIDTH = 64, and 1 bit wide otherwise. If "we" is 2 bits wide, then we[1] is only allowed to be 1 if we[0] is 1 as well (i.e. for dual writeback).
p226
sg37
g38
sg39
VFor dualwrite instruction, check that we[1]==1 is only allowed if we[0] == 1.
p227
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I4
sg49
I3
sg50
I2
sg51
I56
sg52
g38
sg53
g38
sg54
(lp228
sg15
(lp229
sg57
(lp230
sg13
(dp231
g60
I0
ssbtp232
asg62
(lp233
sg57
(lp234
sg13
(dp235
sbtp236
a(V007_proper result transaction
p237
g1
(g18
g3
Ntp238
Rp239
(dp240
g22
I1
sg8
g237
sg23
VVP_CVXIF_F002_S007
p241
sg25
(dp242
sg12
I7
sg15
(lp243
(V000
p244
g1
(g29
g3
Ntp245
Rp246
(dp247
g8
V000
p248
sg23
VVP_CVXIF_F002_S007_I000
p249
sg35
VResult transaction starts in the cycle that result_valid = 1 and ends in the cycle that both result_valid == result_ready == 1.
p250
sg37
g38
sg39
VCheck that result transaction ends properly.
p251
sg41
g38
sg42
g43
sg44
g38
sg45
g38
sg46
g47
sg48
I4
sg49
I3
sg50
I2
sg51
I56
sg52
g38
sg53
g38
sg54
(lp252
sg15
(lp253
sg57
(lp254
sg13
(dp255
g60
I0
ssbtp256
asg62
(lp257
sg57
(lp258
sg13
(dp259
sbtp260
asVrfu_list_0
p261
(lp262
sg62
(lp263
sVvptool_gitrev
p264
V$Id: a782de3eec3de5ff99661fb165c09f541b4228d0 $
p265
sVio_fmt_gitrev
p266
V$Id: 2f6f9e7bc800d8b831382463dc706473c6c6ad8c $
p267
sVconfig_gitrev
p268
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p269
sVymlcfg_gitrev
p270
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p271
sbtp272
.

34
cva6/docs/VerifPlans/CVXIF/runme.sh Normal file
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#############################################################################
# Copyright (C) 2022 Thales DIS France SAS
#
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0.
#
# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com)
#############################################################################
#!/bin/sh
# Location of project-specific directories
ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")`
# Set up platform location. It can be anywhere but should contain
# a valid `vp_config.py` file in `vptool` directory.
# Here we use the verification tree from the example directory.
export PLATFORM_TOP_DIR="$ROOTDIR"
# Set the printable name for the project that will be used
# in the human-readable documentation.
export PROJECT_NAME="CVXIF"
# Set the alphanumerical identifier of the project that
# will be used to construct file names etc.
export PROJECT_IDENT="CVXIF"
# Set the destination directory of Markdown files for this project.
# Since it will be used by VPTOOL, it shall NOT be a relative path.
export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"`
# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'.
# FIXME: Introduce a suitably named shell variable that points to the root
# directory of the tool set (TOOL_TOP etc.)
# FORNOW use a hardcoded relative path.
sh $ROOTDIR/../../../../tools/vptool/vptool.sh $*

35
cva6/docs/VerifPlans/FENCEI/VP_IP000.yml Normal file
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!Feature
next_elt_id: 1
name: 'Fetching '
id: 0
display_order: 0
subfeatures: !!omap
- 000_Fetching: !Subfeature
name: 000_Fetching
tag: VP_FENCEI_F000_S000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F000_S000_I000
description: Instruction data for the next PC must be fetched after the fence.i
instruction has executed (because only then can data-side stores have completed
and caches have been updated).
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Check that after a fence.i instruction retires then instr-side
obi fetches the next instruction to be executed.
pfc: 4
test_type: 4
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

104
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!Feature
next_elt_id: 1
name: StoresVisible
id: 1
display_order: 1
subfeatures: !!omap
- 000_StoresVisible: !Subfeature
name: 000_StoresVisible
tag: VP_FENCEI_F001_S000
next_elt_id: 4
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F001_S000_I000
description: After a fence.i instruction has been executed, all preceding
store instructions shall have their effects visible to the instruction fetch
of the instructions that are to be executed after the fence.i instruction.
reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\
Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf"
ref_mode: section
ref_page: '31'
ref_section: Chapter 3
ref_viewer: firefox
verif_goals: Do a fencei, but right before the fencei do a store to the instruction
following the fencei, then see that the newly stored value is executed instead
of the old instruction (e.g. change addi to use a different immediate).
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: TODO must be added to regression lists!
- '001': !VerifItem
name: '001'
tag: VP_FENCEI_F001_S000_I001
description: After a fence.i instruction has been executed, all preceding
store instructions shall have their effects visible to the instruction fetch
of the instructions that are to be executed after the fence.i instruction.
reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\
Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf"
ref_mode: section
ref_page: '31'
ref_section: Chapter 3
ref_viewer: firefox
verif_goals: Do a fencei followed by any instruction, but let the environment
detect when the fencei is being executed and change the memory holding the
next instruction, then see that the old instruction is not executed.
pfc: -1
test_type: 2
cov_method: -1
cores: 56
coverage_loc: ''
comments: TODO missing cover!
- '002': !VerifItem
name: '002'
tag: VP_FENCEI_F001_S000_I002
description: After a fence.i instruction has been executed, all preceding
store instructions shall have their effects visible to the instruction fetch
of the instructions that are to be executed after the fence.i instruction.
reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\
Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf"
ref_mode: section
ref_page: '31'
ref_section: Chapter 3
ref_viewer: firefox
verif_goals: Let the instruction right before a fence.i write a different
instruction to the address following the fence.i, then observe that the
written instruction is executed instead of the original one and that no
side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit
instructions to force a noticable difference).
pfc: 1
test_type: 1
cov_method: 0
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_FENCEI_F001_S000_I003
description: After a fence.i instruction has been executed, all preceding
store instructions shall have their effects visible to the instruction fetch
of the instructions that are to be executed after the fence.i instruction.
reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\
Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf"
ref_mode: section
ref_page: '31'
ref_section: Chapter 3
ref_viewer: firefox
verif_goals: Check that after having read one value from an address, then
after storing a value to that same address, if executing that address then
the value shall always be that which was written (should work well in both
sim/formal).
pfc: 4
test_type: 4
cov_method: 2
cores: 56
coverage_loc: ''
comments: TODO missing assert. (Note was ignored because of the difficulty
of writing this as an assert for fv.)!
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

279
cva6/docs/VerifPlans/FENCEI/VP_IP002.yml Normal file
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!Feature
next_elt_id: 10
name: ExternalHandshake
id: 2
display_order: 2
subfeatures: !!omap
- 000_ReqHigh: !Subfeature
name: 000_ReqHigh
tag: VP_FENCEI_F002_S000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F002_S000_I000
description: When executing a fence.i instruction, fencei_flush_req_o shall
rise sometime before executing the next instruction.
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Check that when executing a fence.i instruction there will be
a rising req before has retired.
pfc: 4
test_type: 4
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- 001_ReqWaitLsu: !Subfeature
name: 001_ReqWaitLsu
tag: VP_FENCEI_F002_S001
next_elt_id: 1
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F002_S001_I000
description: When executing a fence.i instruction, if there is an ongoing
store instruction (not limited to rv32i) that has not completed (data_rvalid_i
clocked in as 1), then fencei_flush_req_o shall be low.
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis
is a pointer to the source Requirements document of the Features in question. The
pointer should state the version of the target document. It is free-form,
so it can also indicate the specific section/page/paragraph.
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Make sure a store instruction is run right before a fence.i,
and (possibly using obi stalls) ensure that the fence.i is pending retirement
but holds off until the store's data_rvalid_i is clocked in and that fencei_flush_req_o
was low until this point where it now goes high.
pfc: 4
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: TODO missing cover!
- 002_ReqWaitWritebuffer: !Subfeature
name: 002_ReqWaitWritebuffer
tag: VP_FENCEI_F002_S002
next_elt_id: 1
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F002_S002_I000
description: When executing a fence.i instruction, if the write buffer is
not empty, then fencei_flush_req_o shall be low until the write buffer has
been emptied and the corresponding data_rvalid_i have been clocked in as
1.
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Fill up the write buffer prior to executing a fence.i and ensure
that fencei_flush_req_o holds off going high until the write buffer to has
been emptied.
pfc: 4
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: TODO missing cover!
- 003_ReqWaitXinterface: !Subfeature
name: 003_ReqWaitXinterface
tag: VP_FENCEI_F002_S003
next_elt_id: 1
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F002_S003_I000
description: When executing a fence.i instruction, if the X interface is busy
with any store operations, then fencei_flush_req_o shall be low until all
the store operations are done
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Issue one or more store instructions that uses the X interface
and ensure that fencei_flush_req_o waits until the stores have all completed
before going high.
pfc: 4
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 004_ReqWaitObi: !Subfeature
name: 004_ReqWaitObi
tag: VP_FENCEI_F002_S004
next_elt_id: 1
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F002_S004_I000
description: fencei_flush_req_o shall not go high while there are outstanding
stores on the obi bus.
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis
is a pointer to the source Requirements document of the Features in question. The
pointer should state the version of the target document. It is free-form,
so it can also indicate the specific section/page/paragraph.
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Check vs the OBI monitors that there are no outstanding stores
at the time fencei_flush_req_o goes high.
pfc: 4
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 005_ReqLow: !Subfeature
name: 005_ReqLow
tag: VP_FENCEI_F002_S005
next_elt_id: 1
display_order: 5
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F002_S005_I000
description: When fencei_flush_req_o is high, it shall stay high until fencei_flush_req_o
and fencei_flush_ack_i has been sampled high simultaneously, and then then
it shall go low.
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis
is a pointer to the source Requirements document of the Features in question. The
pointer should state the version of the target document. It is free-form,
so it can also indicate the specific section/page/paragraph.
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Check that when fencei_flush_req_o is high, then it behaves correctly
with regards to fencei_flush_ack_i.
pfc: 4
test_type: 4
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
- 006_AckChange: !Subfeature
name: 006_AckChange
tag: VP_FENCEI_F002_S006
next_elt_id: 1
display_order: 6
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F002_S006_I000
description: 'fencei_flush_ack_i is allowed to change freely on any clock
cycle: It can be permanently high, go high without fence.i and retract,
go high at the same cycle as the req, it can delay arbitrarily after req
and then go high, etc'
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis
is a pointer to the source Requirements document of the Features in question. The
pointer should state the version of the target document. It is free-form,
so it can also indicate the specific section/page/paragraph.
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Drive ack to test all permutations of rising/falling before/after/on
req, acking without req, retracting an early ack, delaying ack after req,
etc.
pfc: 0
test_type: 4
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 007_AckWithold: !Subfeature
name: 007_AckWithold
tag: VP_FENCEI_F002_S007
next_elt_id: 1
display_order: 7
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F002_S007_I000
description: If req is high, but ack never comes, then the core keeps on stalling
and the fence.i is blocked from completing.
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Upon a req, try witholding ack for a long time and see that the
fence.i can be stalled arbitrarily long (should have covers for ack delays
of at least {[0:5]}).
pfc: 4
test_type: 4
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 008_BranchInitiated: !Subfeature
name: 008_BranchInitiated
tag: VP_FENCEI_F002_S008
next_elt_id: 1
display_order: 8
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F002_S008_I000
description: After req and ack has been sampled simultaneously high and when
req is low again, then the core takes a branch to the instruction after
the fence.i instruction.
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis
is a pointer to the source Requirements document of the Features in question. The
pointer should state the version of the target document. It is free-form,
so it can also indicate the specific section/page/paragraph.
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Check that the branch is taken at the point after req and ack
has been simultaneously high.
pfc: 4
test_type: 4
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 009_ShadowingBranch: !Subfeature
name: 009_ShadowingBranch
tag: VP_FENCEI_F002_S009
next_elt_id: 1
display_order: 9
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F002_S009_I000
description: If the fence.i ends up not retiring because it was preceeded
by a taken branch or a jump, then the fencei_flush_req_o shall not go high
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Take a branch or do a jump to skip a fence.i, and ensure that
fencei_flush_req_o doesn't go high.
pfc: 4
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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!Feature
next_elt_id: 1
name: MultiCycle
id: 3
display_order: 3
subfeatures: !!omap
- 000_MultiCycle: !Subfeature
name: 000_MultiCycle
tag: VP_FENCEI_F003_S000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F003_S000_I000
description: Given zero stalls on neither instr-side and data-side obi nor
on fencei_flush_ack_i, then the execution of fence.i takes a fixed number
of cycles.
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Check that, given ideal conditions, the cycle count of fence.i
is as expected.
pfc: 4
test_type: 4
cov_method: 2
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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!Feature
next_elt_id: 2
name: StoresComplete
id: 4
display_order: 4
subfeatures: !!omap
- 000_StoresComplete: !Subfeature
name: 000_StoresComplete
tag: VP_FENCEI_F004_S000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F004_S000_I000
description: Any store instruction that is successfully executed before a
fence.i will fully complete and have its effect visible (this is not about
syncronization with instruction fetch, but rather seeing that the stores
are not aborted).
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis
is a pointer to the source Requirements document of the Features in question. The
pointer should state the version of the target document. It is free-form,
so it can also indicate the specific section/page/paragraph.
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Check that all stores (either to next pc or other places) preceding
a fence.i will complete on the bus (excluding exceptions/interrupts/etc)
and be readable afterwards (particularly, ensure that the write buffer isn't
just purged).
pfc: 1
test_type: 1
cov_method: 0
cores: 56
coverage_loc: ''
comments: ''
- 001_StoresComplete: !Subfeature
name: 001_StoresComplete
tag: VP_FENCEI_F004_S001
next_elt_id: 1
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F004_S001_I000
description: Any store instruction that is successfully executed before a
fence.i will fully complete and have its effect visible (this is not about
syncronization with instruction fetch, but rather seeing that the stores
are not aborted).
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Check that all stores (either to next pc or other places) preceding
a fence.i will complete on the bus (excluding exceptions/interrupts/etc)
and be readable afterwards (particularly, ensure that the write buffer isn't
just purged).
pfc: 3
test_type: 3
cov_method: 0
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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!Feature
next_elt_id: 1
name: Flush
id: 5
display_order: 5
subfeatures: !!omap
- 000_Flush: !Subfeature
name: 000_Flush
tag: VP_FENCEI_F005_S000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F005_S000_I000
description: When fence.i is executed, then any prefetched instructions shall
be flushed; meaning that pipeline stages are flushed, prefetcher is flushed,
write buffer is flushed, and data_req_o is eventually supressed.
reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Check that a fence.i will cause flushing of the pipeline, prefetcher,
write buffer, and data_req_o.
pfc: 4
test_type: 4
cov_method: 2
cores: 56
coverage_loc: ''
comments: TODO missing assert. (Have not checked/covered that the pipeline/writebuffer
content is actually purged. Or that any memory change WILL be the next instr
word.)!
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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!Feature
next_elt_id: 1
name: UnusedFields
id: 6
display_order: 6
subfeatures: !!omap
- 000_UnusedFields: !Subfeature
name: 000_UnusedFields
tag: VP_FENCEI_F006_S000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FENCEI_F006_S000_I000
description: imm[11:0], rs1, rd are reserved for future extensions, and implementations
shall ignore them
reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\
Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf"
ref_mode: section
ref_page: '31'
ref_section: Chapter 3
ref_viewer: firefox
verif_goals: Try giving random values in those fields and see that all else
works as expected
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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#############################################################################
# Copyright (C) 2022 Thales DIS France SAS
#
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0.
#
# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com)
#############################################################################
#!/bin/sh
# Location of project-specific directories
ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")`
# Set up platform location. It can be anywhere but should contain
# a valid `vp_config.py` file in `vptool` directory.
# Here we use the verification tree from the example directory.
export PLATFORM_TOP_DIR="$ROOTDIR"
# Set the printable name for the project that will be used
# in the human-readable documentation.
export PROJECT_NAME="FENCEI"
# Set the alphanumerical identifier of the project that
# will be used to construct file names etc.
export PROJECT_IDENT="FENCEI"
# Set the destination directory of Markdown files for this project.
# Since it will be used by VPTOOL, it shall NOT be a relative path.
export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"`
# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'.
# FIXME: Introduce a suitably named shell variable that points to the root
# directory of the tool set (TOOL_TOP etc.)
# FORNOW use a hardcoded relative path.
sh $ROOTDIR/../../../../tools/vptool/vptool.sh $*

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!Feature
next_elt_id: 10
name: PC generation stage
id: 3
display_order: 3
subfeatures: !!omap
- 001_BTB: !Subfeature
name: 001_BTB
tag: VP_IP003_P001
next_elt_id: 6
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F003_S001_I000
description: If instruction is a JALR and BTB (Branch Target Buffer) returns
a valid address, next PC is predicted by BTB. Else JALR is not considered
as a control flow instruction, which will generate a mispredict.
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a JALR instruction with a valid address in BTB which
is not a misprediction. Check that instruction queue is not flushed.
pfc: 4
test_type: 0
cov_method: 1
cores: 16
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_FRONTEND_F003_S001_I001
description: If instruction is a JALR and BTB (Branch Target Buffer) returns
a valid address, next PC is predicted by BTB. Else JALR is not considered
as a control flow instruction, which will generate a mispredict.
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a JALR instruction with a valid address in BTB which
is a misprediction.
pfc: 3
test_type: 0
cov_method: 1
cores: 16
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_FRONTEND_F003_S001_I002
description: "If instruction is a JALR and BTB (Branch Target Buffer) returns\
\ a valid address, next PC is predicted by BTB.\n\nElse JALR is not considered\
\ as a control flow instruction, which will generate a mispredict."
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: 'Execute test with JALR instructions. Functional cov: JALR is
executed and BTB output is not valid.'
pfc: 3
test_type: 0
cov_method: 1
cores: 8
coverage_loc: ''
comments: ''
- 002_BHT: !Subfeature
name: 002_BHT
tag: VP_IP003_P002
next_elt_id: 4
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F003_S002_I000
description: If instruction is a branch and BTH (Branch History table) returns
a valid address, next PC is predicted by BHT. Else branch is not considered
as an control flow instruction, which will generate a mispredict when branch
is taken.
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a BRANCH instruction with a valid address in BHT which
is not a misprediction. Check that instruction queue is not flushed.
pfc: 4
test_type: 0
cov_method: 1
cores: 16
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_FRONTEND_F003_S002_I001
description: If instruction is a branch and BTH (Branch History table) returns
a valid address, next PC is predicted by BHT. Else branch is not considered
as an control flow instruction, which will generate a mispredict when branch
is taken.
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a BRANCH instruction with a valid address in BHT which
is a misprediction.
pfc: 3
test_type: 0
cov_method: 1
cores: 16
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_FRONTEND_F003_S002_I002
description: If instruction is a branch and BTH (Branch History table) returns
a valid address, next PC is predicted by BHT. Else branch is not considered
as an control flow instruction, which will generate a mispredict when branch
is taken.
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: 'Execute test with BRANCH instructions. Functional cov: a BRANCH
is executed, BTB output is not valid and the branch is taken.'
pfc: 3
test_type: 0
cov_method: 1
cores: 8
coverage_loc: ''
comments: ''
- 003_RAS: !Subfeature
name: 003_RAS
tag: VP_IP003_P003
next_elt_id: 4
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F003_S003_I000
description: If instruction is a RET and RAS (Return Address Stack) returns
a valid address and RET has already been consummed by instruction queue.
Else RET is considered as a control flow instruction but next PC is not
predicted. A mispredict wil be generated.
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a RET instruction with a valid address in RAS. Check
that instruction queue is not flushed.
pfc: 3
test_type: 0
cov_method: 1
cores: 16
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_FRONTEND_F003_S003_I001
description: If instruction is a RET and RAS (Return Address Stack) returns
a valid address and RET has already been consummed by instruction queue.
Else RET is considered as a control flow instruction but next PC is not
predicted. A mispredict wil be generated.
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a RET instruction with a valid address in RAS which is
a misprediction.
pfc: 3
test_type: 0
cov_method: 1
cores: 16
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_FRONTEND_F003_S003_I002
description: If instruction is a RET and RAS (Return Address Stack) returns
a valid address and RET has already been consummed by instruction queue.
Else RET is considered as a control flow instruction but next PC is not
predicted. A mispredict wil be generated.
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: 'Execute test with RET instructions. Functional cov: RET is executed
and RAS output is not valid.'
pfc: 3
test_type: 0
cov_method: 1
cores: 8
coverage_loc: ''
comments: ''
- 004_Return from environment call: !Subfeature
name: 004_Return from environment call
tag: VP_IP003_P004
next_elt_id: 2
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F003_S004_I000
description: When CSR asks a return from an environment call, the PC is assigned
to the successive PC to the one stored in the CSR [m-s]epc register.
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Return from
env call
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "Set two different addresses for mepc and sepc in CSR registers.\
\ Use a arc_test returning from machine env call.\n\n* Check by assertion\
\ that when machine return occurs the mepc address is fetched.\n* Functional\
\ cov: execute a machine return."
pfc: 4
test_type: 0
cov_method: 1
cores: 8
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_FRONTEND_F003_S004_I001
description: When CSR asks a return from an environment call, the PC is assigned
to the successive PC to the one stored in the CSR [m-s]epc register.
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Return from
env call
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "Set two different addresses for mepc and sepc in CSR registers.\
\ Use a returning from supervisor env call.\n\n* Check by assertion that\
\ when supervisor return occurs the sepc address is fetched.\n* Functional\
\ cov: execute a supervisor return."
pfc: 4
test_type: 0
cov_method: 1
cores: 24
coverage_loc: ''
comments: ''
- 005_Exception/Interrupt: !Subfeature
name: 005_Exception/Interrupt
tag: VP_IP003_P005
next_elt_id: 2
display_order: 5
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F003_S005_I000
description: If an exception (or interrupt, which is in the context of RISC-V
systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned
to the CSR trap vector base address. The trap vector base address can be
different depending on whether the exception traps to S-Mode or M-Mode (user
mode exceptions are currently not supported)
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Exception
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: 'Set two different addresses for machine and supervisor handlers
in CSR registers. Use a test which executes in machine mode and generates
a machine exception by UVM. Check by assertion that when machine exception
occurs the machine address is fetched. Functional cov: exception occurs
in machine mode.'
pfc: 4
test_type: 0
cov_method: 1
cores: 8
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_FRONTEND_F003_S005_I001
description: If an exception (or interrupt, which is in the context of RISC-V
systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned
to the CSR trap vector base address. The trap vector base address can be
different depending on whether the exception traps to S-Mode or M-Mode (user
mode exceptions are currently not supported)
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Exception
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: 'Set two different addresses for machine and supervisor handlers
in CSR registers. Use a test which executes in supervisor mode and generates
a supervisor exception by UVM. Check by assertion that when supervisor exception
occurs the supervisor address is fetched. functional cov: exception occurs
in supervisor mode.'
pfc: 3
test_type: 0
cov_method: 1
cores: 16
coverage_loc: ''
comments: ''
- 006_Pipeline flush: !Subfeature
name: 006_Pipeline flush
tag: VP_IP003_P006
next_elt_id: 2
display_order: 6
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F003_S006_I000
description: FRONTEND starts fetching from the next instruction again in order
to take the up-dated information into account
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Pipeline flush
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: '[no need to verify this point]'
pfc: -1
test_type: -1
cov_method: -1
cores: 8
coverage_loc: ''
comments: ''
- 007_Debug: !Subfeature
name: 007_Debug
tag: VP_IP003_P007
next_elt_id: 1
display_order: 7
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F003_S007_I000
description: The debug jump is requested by CSR. The address to be jumped
into is HW coded.
reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Debug
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: 'UVM generates a debug request to jump into debug handler. Check
by assertion that the HW coded debug address is fetched. Functional cov:
debug mode occurs'
pfc: 4
test_type: 0
cov_method: 1
cores: 32
coverage_loc: ''
comments: ''
- 008_Address mapping change: !Subfeature
name: 008_Address mapping change
tag: VP_IP003_P008
next_elt_id: 1
display_order: 8
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F003_S008_I000
description: All program counters are logical addressed. If the logical to
physical mapping changes a fence.vm instruction should used to flush the
pipeline and TLBs
reqt_doc: FRONTEND sub-system/functionality/PC generation stage
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a address mapping change, then execute a fence.vm instruction,
and continue the execution.
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
- 009_Pc gen priority: !Subfeature
name: 009_Pc gen priority
tag: VP_IP003_P009
next_elt_id: 3
display_order: 9
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F003_S009_I000
description: The next PC can originate from the following sources (listed
in order of precedence)
reqt_doc: FRONTEND sub-system/functionality/PC generation stage
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: 'Use arc_test executing return from env call and generate Exceptions
by UVM during reset, Branch predict, default, mispredict, replay and return
from env call. Functional cov: monitor the 6 events'
pfc: 3
test_type: 0
cov_method: 1
cores: 8
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_FRONTEND_F003_S009_I002
description: The next PC can originate from the following sources (listed
in order of precedence)
reqt_doc: FRONTEND sub-system/functionality/PC generation stage
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: '[other cases to be elaborated]'
pfc: -1
test_type: -1
cov_method: -1
cores: 8
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

384
cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck
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@ -1,384 +0,0 @@
(VBTB
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I4
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I4
sVwid_order
p12
I4
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_flush
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I1
sg8
g17
sVtag
p23
VVP_IP004_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_FRONTEND_F004_S000_I000
p34
sVdescription
p35
VThe BTB is never flushed.
p36
sVpurpose
p37
VFRONTEND sub-system/Architecture and Modules/BTB
p38
sVverif_goals
p39
VNA\u000a\u000a[Does it make sense?]
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I-1
sVtest_type
p44
I-1
sVcov_method
p45
I-1
sVcores
p46
I0
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
asVrfu_list_1
p57
(lp58
sg52
(lp59
sg13
(dp60
sbtp61
a(V001_table depth
p62
g1
(g18
g3
Ntp63
Rp64
(dp65
g22
I1
sg8
g62
sg23
VVP_IP004_P001
p66
sg25
(dp67
sg12
I1
sg15
(lp68
(V000
p69
g1
(g29
g3
Ntp70
Rp71
(dp72
g8
V000
p73
sg23
VVP_FRONTEND_F004_S001_I000
p74
sg35
VThe information is stored in a 8 entry table.
p75
sg37
VFRONTEND sub-system/Architecture and Modules/BTB
p76
sg39
VConfirm that the best configuration for BTB entry number is 8 by monitoring the Coremark performance and silicon footprint, the configuration without BTB is to be challenged too.
p77
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp78
sg15
(lp79
sg52
(lp80
sg13
(dp81
g55
I0
ssbtp82
asg57
(lp83
sg52
(lp84
sg13
(dp85
sbtp86
a(V002_Table update
p87
g1
(g18
g3
Ntp88
Rp89
(dp90
g22
I1
sg8
g87
sg23
VVP_IP004_P002
p91
sg25
(dp92
sg12
I2
sg15
(lp93
(V000
p94
g1
(g29
g3
Ntp95
Rp96
(dp97
g8
V000
p98
sg23
VVP_FRONTEND_F004_S002_I000
p99
sg35
VWhen a unconditional jumps to a register (JALR instruction) is mispredicted by the EXECUTE, the relative information is stored into the BTB, that is to say the JALR PC and the target address.
p100
sg37
VFRONTEND sub-system/Architecture and Modules/BTB
p101
sg39
VWhen a mis predict occurs caused by JALR, check that info is stored in BTB
p102
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp103
sg15
(lp104
sg52
(lp105
sg13
(dp106
g55
I0
ssbtp107
asg57
(lp108
sg52
(lp109
sg13
(dp110
sbtp111
a(V003_debug is not intrusive
p112
g1
(g18
g3
Ntp113
Rp114
(dp115
g22
I1
sg8
g112
sg23
VVP_IP004_P003
p116
sg25
(dp117
sg12
I3
sg15
(lp118
(V000
p119
g1
(g29
g3
Ntp120
Rp121
(dp122
g8
V000
p123
sg23
VVP_FRONTEND_F004_S003_I000
p124
sg35
VThe BTB is not updated if processor is in debug mode.
p125
sg37
VFRONTEND sub-system/Architecture and Modules/BTB
p126
sg39
VExecute a debug session, check that the table content is not modified
p127
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I32
sg47
g42
sg48
g42
sg49
(lp128
sg15
(lp129
sg52
(lp130
sg13
(dp131
g55
I0
ssbtp132
asg57
(lp133
sg52
(lp134
sg13
(dp135
sbtp136
asVrfu_list_0
p137
(lp138
sg57
(lp139
sVvptool_gitrev
p140
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p141
sVio_fmt_gitrev
p142
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p143
sVconfig_gitrev
p144
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p145
sVymlcfg_gitrev
p146
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p147
sbtp148
.

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@ -0,0 +1,104 @@
!Feature
next_elt_id: 4
name: BTB
id: 4
display_order: 4
subfeatures: !!omap
- 000_flush: !Subfeature
name: 000_flush
tag: VP_IP004_P000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F004_S000_I000
description: The BTB is never flushed.
reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "NA\n\n[Does it make sense?]"
pfc: -1
test_type: -1
cov_method: -1
cores: 0
coverage_loc: ''
comments: ''
- 001_table depth: !Subfeature
name: 001_table depth
tag: VP_IP004_P001
next_elt_id: 1
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F004_S001_I000
description: The information is stored in a 8 entry table.
reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Confirm that the best configuration for BTB entry number is 8
by monitoring the Coremark performance and silicon footprint, the configuration
without BTB is to be challenged too.
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
- 002_Table update: !Subfeature
name: 002_Table update
tag: VP_IP004_P002
next_elt_id: 1
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F004_S002_I000
description: When a unconditional jumps to a register (JALR instruction) is
mispredicted by the EXECUTE, the relative information is stored into the
BTB, that is to say the JALR PC and the target address.
reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: When a mis predict occurs caused by JALR, check that info is
stored in BTB
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
- 003_debug is not intrusive: !Subfeature
name: 003_debug is not intrusive
tag: VP_IP004_P003
next_elt_id: 1
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F004_S003_I000
description: The BTB is not updated if processor is in debug mode.
reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a debug session, check that the table content is not
modified
pfc: -1
test_type: -1
cov_method: -1
cores: 32
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

508
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@ -1,508 +0,0 @@
(VBHT
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I6
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I5
sVwid_order
p12
I5
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_flush
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I1
sg8
g17
sVtag
p23
VVP_IP005_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_FRONTEND_F005_S000_I000
p34
sVdescription
p35
VThe BTB is never flushed.
p36
sVpurpose
p37
VFRONTEND sub-system/Architecture and Modules/BHT
p38
sVverif_goals
p39
VNA\u000a\u000a[Does it make sense?]
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I-1
sVtest_type
p44
I-1
sVcov_method
p45
I-1
sVcores
p46
I0
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
asVrfu_list_1
p57
(lp58
sg52
(lp59
sg13
(dp60
sbtp61
a(V002_table update
p62
g1
(g18
g3
Ntp63
Rp64
(dp65
g22
I1
sg8
g62
sg23
VVP_IP005_P002
p66
sg25
(dp67
sg12
I2
sg15
(lp68
(V000
p69
g1
(g29
g3
Ntp70
Rp71
(dp72
g8
V000
p73
sg23
VVP_FRONTEND_F005_S002_I000
p74
sg35
VWhen a branch instruction is resolved by the EXECUTE, the relative information is stored in the Branch History Table.
p75
sg37
VFRONTEND sub-system/Architecture and Modules/BHT
p76
sg39
VWhen a mis predict occurs caused by BRANCH, check that info is stored in BHT
p77
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp78
sg15
(lp79
sg52
(lp80
sg13
(dp81
g55
I0
ssbtp82
asg57
(lp83
sg52
(lp84
sg13
(dp85
sbtp86
a(V003_saturation
p87
g1
(g18
g3
Ntp88
Rp89
(dp90
g22
I2
sg8
g87
sg23
VVP_IP005_P003
p91
sg25
(dp92
sg12
I3
sg15
(lp93
(V000
p94
g1
(g29
g3
Ntp95
Rp96
(dp97
g8
V000
p98
sg23
VVP_FRONTEND_F005_S003_I000
p99
sg35
VThe Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure.
p100
sg37
VFRONTEND sub-system/Architecture and Modules/BHT
p101
sg39
VExecute a serie of taken and not taken branch to check the saturation mechanism
p102
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I-1
sg47
g42
sg48
g42
sg49
(lp103
sg15
(lp104
sg52
(lp105
sg13
(dp106
g55
I0
ssbtp107
a(V001
p108
g1
(g29
g3
Ntp109
Rp110
(dp111
g8
V001
p112
sg23
VVP_FRONTEND_F005_S003_I001
p113
sg35
VThe Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure.
p114
sg37
VFRONTEND sub-system/Architecture and Modules/BHT
p115
sg39
VVerify the saturation mechnism is optimal. Modify the saturation mechanism by removing/adding one stage, and check the Coremark performance evolution
p116
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp117
sg15
(lp118
sg52
(lp119
sg13
(dp120
g55
I0
ssbtp121
asg57
(lp122
sg52
(lp123
sg13
(dp124
sbtp125
a(V004_Table depth
p126
g1
(g18
g3
Ntp127
Rp128
(dp129
g22
I1
sg8
g126
sg23
VVP_IP005_P004
p130
sg25
(dp131
sg12
I4
sg15
(lp132
(V000
p133
g1
(g29
g3
Ntp134
Rp135
(dp136
g8
V000
p137
sg23
VVP_FRONTEND_F005_S004_I000
p138
sg35
VThe information is stored in a 1024 entry table.
p139
sg37
VFRONTEND sub-system/Architecture and Modules/BHT
p140
sg39
VConfirm that the best configuration for BHT entry number is 1024 by monitoring the Coremark performance and silicon footprint, the configuration without BHT is to be challenged too.
p141
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp142
sg15
(lp143
sg52
(lp144
sg13
(dp145
g55
I0
ssbtp146
asg57
(lp147
sg52
(lp148
sg13
(dp149
sbtp150
a(V005_Debug is not intrusive
p151
g1
(g18
g3
Ntp152
Rp153
(dp154
g22
I1
sg8
g151
sg23
VVP_IP005_P005
p155
sg25
(dp156
sg12
I5
sg15
(lp157
(V000
p158
g1
(g29
g3
Ntp159
Rp160
(dp161
g8
V000
p162
sg23
VVP_FRONTEND_F005_S005_I000
p163
sg35
VThe BHT is not updated if processor is in debug mode.
p164
sg37
VFRONTEND sub-system/Architecture and Modules/BHT
p165
sg39
VExecute a debug session, check that the table content is not modified
p166
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I32
sg47
g42
sg48
g42
sg49
(lp167
sg15
(lp168
sg52
(lp169
sg13
(dp170
g55
I0
ssbtp171
asg57
(lp172
sg52
(lp173
sg13
(dp174
sbtp175
asVrfu_list_0
p176
(lp177
sg57
(lp178
sVvptool_gitrev
p179
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p180
sVio_fmt_gitrev
p181
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p182
sVconfig_gitrev
p183
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p184
sVymlcfg_gitrev
p185
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p186
sbtp187
.

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!Feature
next_elt_id: 6
name: BHT
id: 5
display_order: 5
subfeatures: !!omap
- 000_flush: !Subfeature
name: 000_flush
tag: VP_IP005_P000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F005_S000_I000
description: The BTB is never flushed.
reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "NA\n\n[Does it make sense?]"
pfc: -1
test_type: -1
cov_method: -1
cores: 0
coverage_loc: ''
comments: ''
- 002_table update: !Subfeature
name: 002_table update
tag: VP_IP005_P002
next_elt_id: 1
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F005_S002_I000
description: When a branch instruction is resolved by the EXECUTE, the relative
information is stored in the Branch History Table.
reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: When a mis predict occurs caused by BRANCH, check that info is
stored in BHT
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
- 003_saturation: !Subfeature
name: 003_saturation
tag: VP_IP005_P003
next_elt_id: 2
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F005_S003_I000
description: The Branch History table is a two-bit saturation counter that
takes the virtual address of the current fetched instruction by the CACHE.
It states whether the current branch request should be taken or not. The
two bit counter is updated by the successive execution of the current instructions
as shown in the following figure.
reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a serie of taken and not taken branch to check the saturation
mechanism
pfc: -1
test_type: -1
cov_method: -1
cores: -1
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_FRONTEND_F005_S003_I001
description: The Branch History table is a two-bit saturation counter that
takes the virtual address of the current fetched instruction by the CACHE.
It states whether the current branch request should be taken or not. The
two bit counter is updated by the successive execution of the current instructions
as shown in the following figure.
reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Verify the saturation mechnism is optimal. Modify the saturation
mechanism by removing/adding one stage, and check the Coremark performance
evolution
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
- 004_Table depth: !Subfeature
name: 004_Table depth
tag: VP_IP005_P004
next_elt_id: 1
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F005_S004_I000
description: The information is stored in a 1024 entry table.
reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Confirm that the best configuration for BHT entry number is 1024
by monitoring the Coremark performance and silicon footprint, the configuration
without BHT is to be challenged too.
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
- 005_Debug is not intrusive: !Subfeature
name: 005_Debug is not intrusive
tag: VP_IP005_P005
next_elt_id: 1
display_order: 5
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F005_S005_I000
description: The BHT is not updated if processor is in debug mode.
reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a debug session, check that the table content is not
modified
pfc: -1
test_type: -1
cov_method: -1
cores: 32
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

384
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@ -1,384 +0,0 @@
(VRAS
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I4
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I6
sVwid_order
p12
I6
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_flush
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I1
sg8
g17
sVtag
p23
VVP_IP006_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_FRONTEND_F006_S000_I000
p34
sVdescription
p35
VThe RAS is never flushed.
p36
sVpurpose
p37
VFRONTEND sub-system/Architecture and Modules/RAS
p38
sVverif_goals
p39
VNA\u000a\u000a[Does it make sense?]
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I-1
sVtest_type
p44
I-1
sVcov_method
p45
I-1
sVcores
p46
I0
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
asVrfu_list_1
p57
(lp58
sg52
(lp59
sg13
(dp60
sbtp61
a(V001_table depth
p62
g1
(g18
g3
Ntp63
Rp64
(dp65
g22
I1
sg8
g62
sg23
VVP_IP006_P001
p66
sg25
(dp67
sg12
I1
sg15
(lp68
(V000
p69
g1
(g29
g3
Ntp70
Rp71
(dp72
g8
V000
p73
sg23
VVP_FRONTEND_F006_S001_I000
p74
sg35
VThe RAS FIFO depth is 2.
p75
sg37
VFRONTEND sub-system/Architecture and Modules/RAS
p76
sg39
VConfirm that the best configuration for RAS entry number is 2 by monitoring the Coremark performance and silicon footprint, the configuration without RAS is to be challenged too.
p77
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp78
sg15
(lp79
sg52
(lp80
sg13
(dp81
g55
I0
ssbtp82
asg57
(lp83
sg52
(lp84
sg13
(dp85
sbtp86
a(V002_Table update
p87
g1
(g18
g3
Ntp88
Rp89
(dp90
g22
I1
sg8
g87
sg23
VVP_IP006_P002
p91
sg25
(dp92
sg12
I2
sg15
(lp93
(V000
p94
g1
(g29
g3
Ntp95
Rp96
(dp97
g8
V000
p98
sg23
VVP_FRONTEND_F006_S002_I000
p99
sg35
VWhen an unconditional jumps to a known target address (JAL instruction) is consummed by the instr_queue, the next pc after the JAL instruction and the return address are stored into a FIFO.
p100
sg37
VFRONTEND sub-system/Architecture and Modules/RAS
p101
sg39
VWhen a JAL instruction is executed, check that info is stored in RAS
p102
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp103
sg15
(lp104
sg52
(lp105
sg13
(dp106
g55
I0
ssbtp107
asg57
(lp108
sg52
(lp109
sg13
(dp110
sbtp111
a(V003_Debug is not intrusive
p112
g1
(g18
g3
Ntp113
Rp114
(dp115
g22
I1
sg8
g112
sg23
VVP_IP006_P003
p116
sg25
(dp117
sg12
I3
sg15
(lp118
(V000
p119
g1
(g29
g3
Ntp120
Rp121
(dp122
g8
V000
p123
sg23
VVP_FRONTEND_F006_S003_I000
p124
sg35
VNo dedicated specification
p125
sg37
VFRONTEND sub-system/Architecture and Modules/RAS
p126
sg39
VExecute a debug session, check that the table content is not modified
p127
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I32
sg47
g42
sg48
g42
sg49
(lp128
sg15
(lp129
sg52
(lp130
sg13
(dp131
g55
I0
ssbtp132
asg57
(lp133
sg52
(lp134
sg13
(dp135
sbtp136
asVrfu_list_0
p137
(lp138
sg57
(lp139
sVvptool_gitrev
p140
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p141
sVio_fmt_gitrev
p142
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p143
sVconfig_gitrev
p144
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p145
sVymlcfg_gitrev
p146
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p147
sbtp148
.

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!Feature
next_elt_id: 4
name: RAS
id: 6
display_order: 6
subfeatures: !!omap
- 000_flush: !Subfeature
name: 000_flush
tag: VP_IP006_P000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F006_S000_I000
description: The RAS is never flushed.
reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "NA\n\n[Does it make sense?]"
pfc: -1
test_type: -1
cov_method: -1
cores: 0
coverage_loc: ''
comments: ''
- 001_table depth: !Subfeature
name: 001_table depth
tag: VP_IP006_P001
next_elt_id: 1
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F006_S001_I000
description: The RAS FIFO depth is 2.
reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Confirm that the best configuration for RAS entry number is 2
by monitoring the Coremark performance and silicon footprint, the configuration
without RAS is to be challenged too.
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
- 002_Table update: !Subfeature
name: 002_Table update
tag: VP_IP006_P002
next_elt_id: 1
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F006_S002_I000
description: When an unconditional jumps to a known target address (JAL instruction)
is consummed by the instr_queue, the next pc after the JAL instruction and
the return address are stored into a FIFO.
reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: When a JAL instruction is executed, check that info is stored
in RAS
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
- 003_Debug is not intrusive: !Subfeature
name: 003_Debug is not intrusive
tag: VP_IP006_P003
next_elt_id: 1
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F006_S003_I000
description: No dedicated specification
reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a debug session, check that the table content is not
modified
pfc: -1
test_type: -1
cov_method: -1
cores: 32
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

232
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@ -1,232 +0,0 @@
(VInstr_realign
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I2
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I7
sVwid_order
p12
I7
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_C extension
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I1
sg8
g17
sVtag
p23
VVP_IP007_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_FRONTEND_F007_S000_I000
p34
sVdescription
p35
VThe 32-bit aligned block coming from the CACHE sub-system enters the instr_realign module. This module extracts the instructions from the 32-bit blocks, up to two instructions because it is possible to fetch two instructions when C extension is used. If the instructions are not compressed, it is possible that the instruction is not aligned on the block size but rather interleaved with two cache blocks. In that case, two cache accesses are needed. The instr_realign module provides at maximum one instruction per cycle. Not complete instruction is stored in instr_realign module before being provided in the next cycles.
p36
sVpurpose
p37
VFRONTEND sub-system/Architecture and Modules/Instr_realign
p38
sVverif_goals
p39
VExecute program compiled with C extension. Cover the case when 2 instructions are fetched in the same cache block and when an instruction is interleaved with two cache block\u000a\u000a[NO NEED TO VERIFY THIS CASE]
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I-1
sVtest_type
p44
I-1
sVcov_method
p45
I-1
sVcores
p46
I0
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
asVrfu_list_1
p57
(lp58
sg52
(lp59
sg13
(dp60
sbtp61
a(V001_Flush
p62
g1
(g18
g3
Ntp63
Rp64
(dp65
g22
I1
sg8
g62
sg23
VVP_IP007_P001
p66
sg25
(dp67
sg12
I1
sg15
(lp68
(V000
p69
g1
(g29
g3
Ntp70
Rp71
(dp72
g8
V000
p73
sg23
VVP_FRONTEND_F007_S001_I000
p74
sg35
VIn case of mispredict, flush, replay or branch predict, the instr_realign is re-initialized, the internal register storing the instruction alignment state is reset.
p75
sg37
VFRONTEND sub-system/Architecture and Modules/Instr_realign
p76
sg39
V[NO NEED TO VERIFY THIS CASE]
p77
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I0
sg47
g42
sg48
g42
sg49
(lp78
sg15
(lp79
sg52
(lp80
sg13
(dp81
g55
I0
ssbtp82
asg57
(lp83
sg52
(lp84
sg13
(dp85
sbtp86
asVrfu_list_0
p87
(lp88
sg57
(lp89
sVvptool_gitrev
p90
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p91
sVio_fmt_gitrev
p92
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p93
sVconfig_gitrev
p94
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p95
sVymlcfg_gitrev
p96
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p97
sbtp98
.

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!Feature
next_elt_id: 2
name: Instr_realign
id: 7
display_order: 7
subfeatures: !!omap
- 000_C extension: !Subfeature
name: 000_C extension
tag: VP_IP007_P000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F007_S000_I000
description: The 32-bit aligned block coming from the CACHE sub-system enters
the instr_realign module. This module extracts the instructions from the
32-bit blocks, up to two instructions because it is possible to fetch two
instructions when C extension is used. If the instructions are not compressed,
it is possible that the instruction is not aligned on the block size but
rather interleaved with two cache blocks. In that case, two cache accesses
are needed. The instr_realign module provides at maximum one instruction
per cycle. Not complete instruction is stored in instr_realign module before
being provided in the next cycles.
reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_realign
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "Execute program compiled with C extension. Cover the case when\
\ 2 instructions are fetched in the same cache block and when an instruction\
\ is interleaved with two cache block\n\n[NO NEED TO VERIFY THIS CASE]"
pfc: -1
test_type: -1
cov_method: -1
cores: 0
coverage_loc: ''
comments: ''
- 001_Flush: !Subfeature
name: 001_Flush
tag: VP_IP007_P001
next_elt_id: 1
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F007_S001_I000
description: In case of mispredict, flush, replay or branch predict, the instr_realign
is re-initialized, the internal register storing the instruction alignment
state is reset.
reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_realign
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: '[NO NEED TO VERIFY THIS CASE]'
pfc: -1
test_type: -1
cov_method: -1
cores: 0
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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@ -1,308 +0,0 @@
(VInstr_queue
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I3
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I8
sVwid_order
p12
I8
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_FIFO depth
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I1
sg8
g17
sVtag
p23
VVP_IP008_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_FRONTEND_F008_S000_I000
p34
sVdescription
p35
VThe instruction queue contains max 4 instructions.
p36
sVpurpose
p37
VFRONTEND sub-system/Architecture and Modules/Instr_queue
p38
sVverif_goals
p39
VConfirm that the best configuration for instruction queue entry number is 4 by monitoring the Coremark performance and silicon footprint
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I11
sVtest_type
p44
I10
sVcov_method
p45
I10
sVcores
p46
I8
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
asVrfu_list_1
p57
(lp58
sg52
(lp59
sg13
(dp60
sbtp61
a(V001_Page fault exception
p62
g1
(g18
g3
Ntp63
Rp64
(dp65
g22
I1
sg8
g62
sg23
VVP_IP008_P001
p66
sg25
(dp67
sg12
I1
sg15
(lp68
(V000
p69
g1
(g29
g3
Ntp70
Rp71
(dp72
g8
V000
p73
sg23
VVP_FRONTEND_F008_S001_I000
p74
sg35
VIn instruction queue, exception can only correspond to page-fault exception.
p75
sg37
VFRONTEND sub-system/Architecture and Modules/Instr_queue
p76
sg39
VExecute following exception and check that only page-fault can be stored in instruction queue: bus errors, invalid accesses or instruction page faults.
p77
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp78
sg15
(lp79
sg52
(lp80
sg13
(dp81
g55
I0
ssbtp82
asg57
(lp83
sg52
(lp84
sg13
(dp85
sbtp86
a(V002_Flush
p87
g1
(g18
g3
Ntp88
Rp89
(dp90
g22
I1
sg8
g87
sg23
VVP_IP008_P002
p91
sg25
(dp92
sg12
I2
sg15
(lp93
(V000
p94
g1
(g29
g3
Ntp95
Rp96
(dp97
g8
V000
p98
sg23
VVP_FRONTEND_F008_S002_I000
p99
sg35
VThe instruction queue can be flushed by CONTROLLER.
p100
sg37
VFRONTEND sub-system/Architecture and Modules/Instr_queue
p101
sg39
V[NO NEED TO VERIFY THIS CASE]
p102
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I0
sg47
g42
sg48
g42
sg49
(lp103
sg15
(lp104
sg52
(lp105
sg13
(dp106
g55
I0
ssbtp107
asg57
(lp108
sg52
(lp109
sg13
(dp110
sbtp111
asVrfu_list_0
p112
(lp113
sg57
(lp114
sVvptool_gitrev
p115
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p116
sVio_fmt_gitrev
p117
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p118
sVconfig_gitrev
p119
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p120
sVymlcfg_gitrev
p121
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p122
sbtp123
.

80
cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml Normal file
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@ -0,0 +1,80 @@
!Feature
next_elt_id: 3
name: Instr_queue
id: 8
display_order: 8
subfeatures: !!omap
- 000_FIFO depth: !Subfeature
name: 000_FIFO depth
tag: VP_IP008_P000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F008_S000_I000
description: The instruction queue contains max 4 instructions.
reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Confirm that the best configuration for instruction queue entry
number is 4 by monitoring the Coremark performance and silicon footprint
pfc: 11
test_type: 10
cov_method: 10
cores: 8
coverage_loc: ''
comments: ''
- 001_Page fault exception: !Subfeature
name: 001_Page fault exception
tag: VP_IP008_P001
next_elt_id: 1
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F008_S001_I000
description: In instruction queue, exception can only correspond to page-fault
exception.
reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: 'Execute following exception and check that only page-fault can
be stored in instruction queue: bus errors, invalid accesses or instruction
page faults.'
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
- 002_Flush: !Subfeature
name: 002_Flush
tag: VP_IP008_P002
next_elt_id: 1
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F008_S002_I000
description: The instruction queue can be flushed by CONTROLLER.
reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: '[NO NEED TO VERIFY THIS CASE]'
pfc: -1
test_type: -1
cov_method: -1
cores: 0
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

59
cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck
View file

@ -1,59 +0,0 @@
(VInstr_scan
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I0
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I9
sVwid_order
p12
I9
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
sVrfu_list_0
p17
(lp18
sVrfu_list_1
p19
(lp20
sVvptool_gitrev
p21
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p22
sVio_fmt_gitrev
p23
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p24
sVconfig_gitrev
p25
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p26
sVymlcfg_gitrev
p27
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p28
sbtp29
.

10
cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml Normal file
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@ -0,0 +1,10 @@
!Feature
next_elt_id: 0
name: Instr_scan
id: 9
display_order: 9
subfeatures: !!omap []
vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

376
cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck
View file

@ -1,376 +0,0 @@
(VFetch stage
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I3
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I10
sVwid_order
p12
I10
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V001_MMU translation
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I2
sg8
g17
sVtag
p23
VVP_IP010_P001
p24
sVitem_list
p25
(dp26
sg12
I1
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_FRONTEND_F010_S001_I000
p34
sVdescription
p35
VThe Fetch stage asks the MMU to translate the requested address.
p36
sVpurpose
p37
VFRONTEND sub-system/functionality/Fetch stage
p38
sVverif_goals
p39
VExecute a program with virtual PC
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I-1
sVtest_type
p44
I-1
sVcov_method
p45
I-1
sVcores
p46
I16
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
a(V001
p57
g1
(g29
g3
Ntp58
Rp59
(dp60
g8
V001
p61
sg23
VVP_FRONTEND_F010_S001_I001
p62
sg35
VThe Fetch stage asks the MMU to translate the requested address.
p63
sg37
VFRONTEND sub-system/functionality/Fetch stage
p64
sg39
VCheck the translation does not impact execution time by executing Coremark in pphysical and virtual modes.
p65
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp66
sg15
(lp67
sg52
(lp68
sg13
(dp69
g55
I0
ssbtp70
asVrfu_list_1
p71
(lp72
sg52
(lp73
sg13
(dp74
sbtp75
a(V002_Exceptions
p76
g1
(g18
g3
Ntp77
Rp78
(dp79
g22
I4
sg8
g76
sg23
VVP_IP010_P002
p80
sg25
(dp81
sg12
I2
sg15
(lp82
(V000
p83
g1
(g29
g3
Ntp84
Rp85
(dp86
g8
V000
p87
sg23
VVP_FRONTEND_F010_S002_I000
p88
sg35
VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults.
p89
sg37
VFRONTEND sub-system/functionality/Fetch stage
p90
sg39
VGenerate a bus error exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: a bus error exception occurs.
p91
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I8
sg47
g42
sg48
g42
sg49
(lp92
sg15
(lp93
sg52
(lp94
sg13
(dp95
g55
I0
ssbtp96
a(V002
p97
g1
(g29
g3
Ntp98
Rp99
(dp100
g8
V002
p101
sg23
VVP_FRONTEND_F010_S002_I002
p102
sg35
VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults.
p103
sg37
VFRONTEND sub-system/functionality/Fetch stage
p104
sg39
VGenerate an invalid access exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: an invalid access exception occurs.
p105
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I8
sg47
g42
sg48
g42
sg49
(lp106
sg15
(lp107
sg52
(lp108
sg13
(dp109
g55
I0
ssbtp110
a(V003
p111
g1
(g29
g3
Ntp112
Rp113
(dp114
g8
V003
p115
sg23
VVP_FRONTEND_F010_S002_I003
p116
sg35
VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults.
p117
sg37
VFRONTEND sub-system/functionality/Fetch stage
p118
sg39
VGenerate an instruction page faults and check that the exception is triggered
p119
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp120
sg15
(lp121
sg52
(lp122
sg13
(dp123
g55
I0
ssbtp124
asg71
(lp125
sg52
(lp126
sg13
(dp127
sbtp128
asVrfu_list_0
p129
(lp130
sg71
(lp131
sVvptool_gitrev
p132
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p133
sVio_fmt_gitrev
p134
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p135
sVconfig_gitrev
p136
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p137
sVymlcfg_gitrev
p138
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p139
sbtp140
.

114
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@ -0,0 +1,114 @@
!Feature
next_elt_id: 3
name: Fetch stage
id: 10
display_order: 10
subfeatures: !!omap
- 001_MMU translation: !Subfeature
name: 001_MMU translation
tag: VP_IP010_P001
next_elt_id: 2
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F010_S001_I000
description: The Fetch stage asks the MMU to translate the requested address.
reqt_doc: FRONTEND sub-system/functionality/Fetch stage
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Execute a program with virtual PC
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_FRONTEND_F010_S001_I001
description: The Fetch stage asks the MMU to translate the requested address.
reqt_doc: FRONTEND sub-system/functionality/Fetch stage
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Check the translation does not impact execution time by executing
Coremark in pphysical and virtual modes.
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
- 002_Exceptions: !Subfeature
name: 002_Exceptions
tag: VP_IP010_P002
next_elt_id: 4
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_FRONTEND_F010_S002_I000
description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback
potential exceptions generated by the memory fetch request. They can be
bus errors, invalid accesses or instruction page faults.
reqt_doc: FRONTEND sub-system/functionality/Fetch stage
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: 'Generate a bus error exception by UVM or by test (to be decided)
and check that the exception address is fetched. Functional cov: a bus error
exception occurs.'
pfc: -1
test_type: -1
cov_method: -1
cores: 8
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_FRONTEND_F010_S002_I002
description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback
potential exceptions generated by the memory fetch request. They can be
bus errors, invalid accesses or instruction page faults.
reqt_doc: FRONTEND sub-system/functionality/Fetch stage
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: 'Generate an invalid access exception by UVM or by test (to be
decided) and check that the exception address is fetched. Functional cov:
an invalid access exception occurs.'
pfc: -1
test_type: -1
cov_method: -1
cores: 8
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_FRONTEND_F010_S002_I003
description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback
potential exceptions generated by the memory fetch request. They can be
bus errors, invalid accesses or instruction page faults.
reqt_doc: FRONTEND sub-system/functionality/Fetch stage
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: Generate an instruction page faults and check that the exception
is triggered
pfc: -1
test_type: -1
cov_method: -1
cores: 16
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

2
cva6/docs/VerifPlans/FRONTEND/runme.sh
View file

@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"`
# FIXME: Introduce a suitably named shell variable that points to the root
# directory of the tool set (TOOL_TOP etc.)
# FORNOW use a hardcoded relative path.
python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py -t winxpblue
sh $ROOTDIR/../../../../tools/vptool/vptool.sh $*

1365
cva6/docs/VerifPlans/ISA_RV32/RISCV_Instructions.rst Normal file
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1999
cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck
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697
cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml Normal file
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@ -0,0 +1,697 @@
!Feature
next_elt_id: 11
name: RV32I Register-Immediate Instructions
id: 0
display_order: 0
subfeatures: !!omap
- 000_ADDI: !Subfeature
name: 000_ADDI
tag: VP_IP011_P000
next_elt_id: 3
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F000_S000_I000
description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\
\ overflow is lost and ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_addi_cg.cp_rs1\nisacov.rv32i_addi_cg.cp_rd\nisacov.rv32i_addi_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F000_S000_I001
description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\
\ overflow is lost and ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\
\ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_addi_cg.cp_rs1_value\nisacov.rv32i_addi_cg.cp_immi_value\n\
isacov.rv32i_addi_cg.cross_rs1_immi_value\nisacov.rv32i_addi_cg.cp_rs1_toggle\n\
isacov.rv32i_addi_cg.cp_immi_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F000_S000_I002
description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\
\ overflow is lost and ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_addi_cg.cp_rd_value\nisacov.rv32i_addi_cg.cp_rd_toggle"
comments: ''
- 001_XORI: !Subfeature
name: 001_XORI
tag: VP_IP011_P001
next_elt_id: 5
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F000_S001_I000
description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\
\ is a bitwise, not logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_xori_cg.cp_rs1\nisacov.rv32i_xori_cg.cp_rd\nisacov.rv32i_xori_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F000_S001_I001
description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\
\ is a bitwise, not logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\
\ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_xori_cg.cp_rs1_value\nisacov.rv32i_xori_cg.cp_immi_value\n\
isacov.rv32i_xori_cg.cross_rs1_immi_value\nisacov.rv32i_xori_cg.cp_rs1_toggle\n\
isacov.rv32i_xori_cg.cp_immi_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F000_S001_I002
description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\
\ is a bitwise, not logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_xori_cg.cp_rd_value\nisacov.rv32i_xori_cg.cp_rd_toggle"
comments: ''
- 002_ORI: !Subfeature
name: 002_ORI
tag: VP_IP011_P002
next_elt_id: 4
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F000_S002_I000
description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\
\ is a bitwise, not logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_ori_cg.cp_rs1\nisacov.rv32i_ori_cg.cp_rd\nisacov.rv32i_ori_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F000_S002_I001
description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\
\ is a bitwise, not logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\
\ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_ori_cg.cp_rs1_value\nisacov.rv32i_ori_cg.cp_immi_value\n\
isacov.rv32i_ori_cg.cross_rs1_immi_value\nisacov.rv32i_ori_cg.cp_rs1_toggle\n\
isacov.rv32i_ori_cg.cp_immi_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F000_S002_I002
description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\
\ is a bitwise, not logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_ori_cg.cp_rd_value\nisacov.rv32i_ori_cg.cp_rd_toggle"
comments: ''
- 003_ANDI: !Subfeature
name: 003_ANDI
tag: VP_IP011_P003
next_elt_id: 3
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F000_S003_I000
description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\
\ this is a bitwise, not logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_andi_cg.cp_rs1\nisacov.rv32i_andi_cg.cp_rd\nisacov.rv32i_andi_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F000_S003_I001
description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\
\ this is a bitwise, not logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\
\ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_andi_cg.cp_rs1_value\nisacov.rv32i_andi_cg.cp_immi_value\n\
isacov.rv32i_andi_cg.cross_rs1_immi_value\nisacov.rv32i_andi_cg.cp_rs1_toggle\n\
isacov.rv32i_andi_cg.cp_immi_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F000_S003_I002
description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\
\ this is a bitwise, not logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_andi_cg.cp_rd_value\nisacov.rv32i_andi_cg.cp_rd_toggle"
comments: ''
- 004_SLTI: !Subfeature
name: 004_SLTI
tag: VP_IP011_P004
next_elt_id: 3
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F000_S004_I000
description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\
Both imm and rs1 treated as signed numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_slti_cg.cp_rs1\nisacov.rv32i_slti_cg.cp_rd\nisacov.rv32i_slti_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F000_S004_I001
description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\
Both imm and rs1 treated as signed numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\
\ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_slti_cg.cp_rs1_value\nisacov.rv32i_slti_cg.cp_immi_value\n\
isacov.rv32i_slti_cg.cross_rs1_immi_value\nisacov.rv32i_slti_cg.cp_rs1_toggle\n\
isacov.rv32i_slti_cg.cp_immi_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F000_S004_I002
description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\
Both imm and rs1 treated as signed numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is in [0,1]"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_slti_cg.cp_rd_value
comments: ''
- 005_SLTIU: !Subfeature
name: 005_SLTIU
tag: VP_IP011_P005
next_elt_id: 3
display_order: 5
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F000_S005_I000
description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\
\ 0\nBoth imm and rs1 treated as unsigned numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sltiu_cg.cp_rs1\nisacov.rv32i_sltiu_cg.cp_rd\n\
isacov.rv32i_sltiu_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F000_S005_I001
description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\
\ 0\nBoth imm and rs1 treated as unsigned numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\
\ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sltiu_cg.cp_rs1_value\nisacov.rv32i_sltiu_cg.cp_immi_value\n\
isacov.rv32i_sltiu_cg.cross_rs1_immi_value\nisacov.rv32i_sltiu_cg.cp_rs1_toggle\n\
isacov.rv32i_sltiu_cg.cp_immi_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F000_S005_I002
description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\
\ 0\nBoth imm and rs1 treated as unsigned numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is in [0,1]"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_sltiu_cg.cp_rd_value
comments: ''
- 006_SLLI: !Subfeature
name: 006_SLLI
tag: VP_IP011_P006
next_elt_id: 3
display_order: 6
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F000_S006_I000
description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\
\ into lower bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_slli_cg.cp_rs1\nisacov.rv32i_slli_cg.cp_rd\nisacov.rv32i_slli_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F000_S006_I001
description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\
\ into lower bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\
\ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\
\ zero values are used\nAll bits of rs1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_slli_cg.cp_rs1_value\nisacov.rv32i_slli_cg.cp_immi_value\n\
isacov.rv32i_slli_cg.cross_rs1_immi_value\nisacov.rv32i_slli_cg.cp_rs1_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F000_S006_I002
description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\
\ into lower bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_slli_cg.cp_rd_value\nisacov.rv32i_slli_cg.cp_rd_toggle"
comments: ''
- 007_SRLI: !Subfeature
name: 007_SRLI
tag: VP_IP011_P007
next_elt_id: 4
display_order: 7
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F000_S007_I000
description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\
\ into upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_srli_cg.cp_rs1\nisacov.rv32i_srli_cg.cp_rd\nisacov.rv32i_srli_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F000_S007_I001
description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\
\ into upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\
\ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\
\ zero values are used\nAll bits of rs1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_srli_cg.cp_rs1_value\nisacov.rv32i_srli_cg.cp_immi_value\n\
isacov.rv32i_srli_cg.cross_rs1_immi_value\nisacov.rv32i_srli_cg.cp_rs1_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F000_S007_I002
description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\
\ into upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_srli_cg.cp_rd_value\nisacov.rv32i_srli_cg.cp_rd_toggle"
comments: ''
- 008_SRAI: !Subfeature
name: 008_SRAI
tag: VP_IP011_P008
next_elt_id: 3
display_order: 8
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F000_S008_I000
description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\
\ bit is copied into the vacated upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_srai_cg.cp_rs1\nisacov.rv32i_srai_cg.cp_rd\nisacov.rv32i_srai_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F000_S008_I001
description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\
\ bit is copied into the vacated upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\
\ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\
\ zero values are used\nAll bits of rs1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_srai_cg.cp_rs1_value\nisacov.rv32i_srai_cg.cp_immi_value\n\
isacov.rv32i_srai_cg.cross_rs1_immi_value\nisacov.rv32i_srai_cg.cp_rs1_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F000_S008_I002
description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\
\ into upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_srai_cg.cp_rd_value\nisacov.rv32i_srai_cg.cp_rd_toggle"
comments: ''
- 009_LUI: !Subfeature
name: 009_LUI
tag: VP_IP011_P009
next_elt_id: 3
display_order: 9
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F000_S009_I000
description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_lui_cg.cp_rd
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F000_S009_I001
description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\
\ value is zero and non-zero\nAll bits of immu are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lui_cg.cp_immu_value\nisacov.rv32i_lui_cg.cp_immu_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F000_S009_I002
description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is zero and non-zero\nAll bits of\
\ rd[31:12] are toggled (11:0 are deposited with 0)"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lui_cg.cp_rd_value\nisacov.rv32i_lui_cg.cp_rd_toggle"
comments: ''
- 010_AUIPC: !Subfeature
name: 010_AUIPC
tag: VP_IP011_P010
next_elt_id: 3
display_order: 10
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F000_S010_I000
description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\
\ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_auipc_cg.cp_rd
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F000_S010_I001
description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\
\ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\
\ value is zero and non-zero\nAll bits of immu are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_auipc_cg.cp_immu_value\nisacov.rv32i_auipc_cg.cp_immu_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F000_S010_I002
description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\
\ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is zero and non-zero\nAll bits of\
\ rd[31:12] are toggled (11:0 are deposited with 0)"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_auipc_cg.cp_rd_value\nisacov.rv32i_auipc_cg.cp_rd_toggle"
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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!Feature
next_elt_id: 10
name: RV32I Register-Register Instructions
id: 1
display_order: 1
subfeatures: !!omap
- 000_ADD: !Subfeature
name: 000_ADD
tag: VP_IP001_P000
next_elt_id: 4
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F001_S000_I000
description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\
\ and ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_add_cg.cp_rs1\nisacov.rv32i_add_cg.cp_rs2\nisacov.rv32i_add_cg.cp_rd\n\
isacov.rv32i_add_cg.cp_rd_rs1_hazard\nisacov.rv32i_add_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F001_S000_I001
description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\
\ and ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
\ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_add_cg.cp_rs1_value\nisacov.rv32i_add_cg.cp_rs2_value\n\
isacov.rv32i_add_cg.cross_rs1_rs2_value\nisacov.rv32i_add_cg.cp_rs1_toggle\n\
isacov.rv32i_add_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F001_S000_I002
description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\
\ and ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_add_cg.cp_rd_value\nisacov.rv32i_add_cg.cp_rd_toggle"
comments: ''
- 001_SUB: !Subfeature
name: 001_SUB
tag: VP_IP001_P001
next_elt_id: 3
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F001_S001_I000
description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sub_cg.cp_rs1\nisacov.rv32i_sub_cg.cp_rs2\nisacov.rv32i_sub_cg.cp_rd\n\
isacov.rv32i_sub_cg.cp_rd_rs1_hazard\nisacov.rv32i_sub_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F001_S001_I001
description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
\ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sub_cg.cp_rs1_value\nisacov.rv32i_sub_cg.cp_rs2_value\n\
isacov.rv32i_sub_cg.cross_rs1_rs2_value\nisacov.rv32i_sub_cg.cp_rs1_toggle\n\
isacov.rv32i_sub_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F001_S001_I002
description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sub_cg.cp_rd_value\nisacov.rv32i_sub_cg.cp_rd_toggle"
comments: ''
- 002_AND: !Subfeature
name: 002_AND
tag: VP_IP001_P002
next_elt_id: 3
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F001_S002_I000
description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\
\ logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_and_cg.cp_rs1\nisacov.rv32i_and_cg.cp_rs2\nisacov.rv32i_and_cg.cp_rd\n\
isacov.rv32i_and_cg.cp_rd_rs1_hazard\nisacov.rv32i_and_cg.cp_rd_rs2_hazard\n\
isacov.rv32i_and_cg.cp_rs1\nisacov.rv32i_and_cg.cp_rs2\nisacov.rv32i_and_cg.cp_rd\n\
isacov.rv32i_and_cg.cp_rd_rs1_hazard\nisacov.rv32i_and_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F001_S002_I001
description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\
\ logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
\ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_and_cg.cp_rs1_value\nisacov.rv32i_and_cg.cp_rs2_value\n\
isacov.rv32i_and_cg.cross_rs1_rs2_value\nisacov.rv32i_and_cg.cp_rs1_toggle\n\
isacov.rv32i_and_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F001_S002_I002
description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\
\ logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_and_cg.cp_rd_value\nisacov.rv32i_and_cg.cp_rd_toggle"
comments: ''
- 003_OR: !Subfeature
name: 003_OR
tag: VP_IP001_P003
next_elt_id: 3
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F001_S003_I000
description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\
\ logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_or_cg.cp_rs1\nisacov.rv32i_or_cg.cp_rs2\nisacov.rv32i_or_cg.cp_rd\n\
isacov.rv32i_or_cg.cp_rd_rs1_hazard\nisacov.rv32i_or_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F001_S003_I001
description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\
\ logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
\ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_or_cg.cp_rs1_value\nisacov.rv32i_or_cg.cp_rs2_value\n\
isacov.rv32i_or_cg.cross_rs1_rs2_value\nisacov.rv32i_or_cg.cp_rs1_toggle\n\
isacov.rv32i_or_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F001_S003_I002
description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\
\ logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_or_cg.cp_rd_value\nisacov.rv32i_or_cg.cp_rd_toggle"
comments: ''
- 004_XOR: !Subfeature
name: 004_XOR
tag: VP_IP001_P004
next_elt_id: 3
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F001_S004_I000
description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\
\ logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_xor_cg.cp_rs1\nisacov.rv32i_xor_cg.cp_rs2\nisacov.rv32i_xor_cg.cp_rd\n\
isacov.rv32i_xor_cg.rd_rs1_hazard\nisacov.rv32i_xor_cg.rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F001_S004_I001
description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\
\ logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
\ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_xor_cg.cp_rs1_value\nisacov.rv32i_xor_cg.cp_rs2_value\n\
isacov.rv32i_xor_cg.cross_rs1_rs2_value\nisacov.rv32i_xor_cg.cp_rs1_toggle\n\
isacov.rv32i_xor_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F001_S004_I002
description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\
\ logical operation"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: -1
test_type: -1
cov_method: -1
cores: 56
coverage_loc: "isacov.rv32i_xor_cg.cp_rd_value\nisacov.rv32i_xor_cg.cp_rd_toggle"
comments: ''
- 005_SLT: !Subfeature
name: 005_SLT
tag: VP_IP001_P005
next_elt_id: 3
display_order: 5
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F001_S005_I000
description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\
\ treated as signed numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_slt_cg.cp_rs1\nisacov.rv32i_slt_cg.cp_rs2\nisacov.rv32i_slt_cg.cp_rd\n\
isacov.rv32i_slt_cg.cp_rd_rs1_hazard\nisacov.rv32i_slt_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F001_S005_I001
description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\
\ treated as signed numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
\ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_slt_cg.cp_rs1_value\nisacov.rv32i_slt_cg.cp_rs2_value\n\
isacov.rv32i_slt_cg.cross_rs1_rs2_value\nisacov.rv32i_slt_cg.cp_rs1_toggle\n\
isacov.rv32i_slt_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F001_S005_I002
description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\
\ treated as signed numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is [0,1]"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_slt_cg.cp_rd_value
comments: ''
- 006_SLTU: !Subfeature
name: 006_SLTU
tag: VP_IP001_P006
next_elt_id: 3
display_order: 6
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F001_S006_I000
description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\
\ and rs2 treated as unsigned numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sltu_cg.cp_rs1\nisacov.rv32i_sltu_cg.cp_rs2\n\
isacov.rv32i_sltu_cg.cp_rd\nisacov.rv32i_sltu_cg.cp_rd_rs1_hazard\nisacov.rv32i_sltu_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F001_S006_I001
description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\
\ and rs2 treated as unsigned numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\
\ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sltu_cg.cp_rs1_value\nisacov.rv32i_sltu_cg.cp_rs2_value\n\
isacov.rv32i_sltu_cg.cross_rs1_rs2_value\nisacov.rv32i_sltu_cg.cp_rs1_toggle\n\
isacov.rv32i_sltu_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F001_S006_I002
description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\
\ and rs2 treated as unsigned numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is [0,1]"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_sltu_cg.cp_rd_value
comments: ''
- 007_SLL: !Subfeature
name: 007_SLL
tag: VP_IP001_P007
next_elt_id: 3
display_order: 7
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F001_S007_I000
description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\
\ lower bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sll_cg.cp_rs1\nisacov.rv32i_sll_cg.cp_rs2\nisacov.rv32i_sll_cg.cp_rd\n\
isacov.rv32i_sll_cg.cp_rd_rs1_hazard\nisacov.rv32i_sll_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F001_S007_I001
description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\
\ lower bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\
\ is tested from [0,31]\nAll combinations of rs1 and rs2 non-zero and zero\
\ values with all shift values are used\nAll bits of rs1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sll_cg.cp_rs1_value\nisacov.rv32i_sll_cg.cp_rs2_value\n\
isacov.rv32i_sll_cg.cross_rs1_rs2_value\nisacov.rv32i_sll_cg.cp_rs1_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F001_S007_I002
description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\
\ lower bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is non-zero and zero.\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sll_cg.cp_rd_value\nisacov.rv32i_sll_cg.cp_rd_toggle\n\
isacov.rv32i_sll_cg.cp_rd_value\nisacov.rv32i_sll_cg.cp_rd_toggle"
comments: ''
- 008_SRL: !Subfeature
name: 008_SRL
tag: VP_IP001_P008
next_elt_id: 3
display_order: 8
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F001_S008_I000
description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\
\ upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_srl_cg.cp_rs1\nisacov.rv32i_srl_cg.cp_rs2\nisacov.rv32i_srl_cg.cp_rd\n\
isacov.rv32i_srl_cg.cp_rd_rs1_hazard\nisacov.rv32i_srl_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F001_S008_I001
description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\
\ upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\
\ is tested from [0,31]\nAll combinations of rs1 and rs2 non-zero and zero\
\ values with all shift values are used\nAll bits of rs1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_srl_cg.cp_rs1_value\nisacov.rv32i_srl_cg.cp_rs2_value\n\
isacov.rv32i_srl_cg.cross_rs1_rs2_value\nisacov.rv32i_srl_cg.cp_rs1_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F001_S008_I002
description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\
\ upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is non-zero and zero.\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_srl_cg.cp_rd_value\nisacov.rv32i_srl_cg.cp_rd_toggle"
comments: ''
- 009_SRA: !Subfeature
name: 009_SRA
tag: VP_IP001_P009
next_elt_id: 3
display_order: 9
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F001_S009_I000
description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\
\ is copied into the vacated upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sra_cg.cp_rs1\nisacov.rv32i_sra_cg.cp_rs2\nisacov.rv32i_sra_cg.cp_rd\n\
isacov.rv32i_sra_cg.cp_rd_rs1_hazard\nisacov.rv32i_sra_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F001_S009_I001
description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\
\ is copied into the vacated upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve, and zero\nrs2 value\
\ is tested from [0,31]\nAll combinations of rs1 and rs2 +ve, -ve and zero\
\ values with all shift values are used\nAll bits of rs1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sra_cg.cp_rs1_value\nisacov.rv32i_sra_cg.cp_rs2_value\n\
isacov.rv32i_sra_cg.cross_rs1_rs2_value\nisacov.rv32i_sra_cg.cp_rs1_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F001_S009_I002
description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\
\ upper bits"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve, and zero.\nAll bits\
\ of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sra_cg.cp_rd_value\nisacov.rv32i_sra_cg.cp_rd_toggle"
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

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cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck
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!Feature
next_elt_id: 8
name: RV32I Control Transfer Instructions
id: 2
display_order: 2
subfeatures: !!omap
- 000_JAL: !Subfeature
name: 000_JAL
tag: VP_IP002_P000
next_elt_id: 3
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F002_S000_I000
description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\
pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\
\ unconditional jump)\npc += Sext({imm[20:1], 1’b0})"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_jal_cg.cp_rd
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F002_S000_I001
description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\
pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\
\ unconditional jump)\npc += Sext({imm[20:1], 1’b0})"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmj value is +ve, -ve, and zero\nAll bits\
\ of immj are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_jal_cg.cp_immj_value\nisacov.rv32i_jal_cg.cp_immj_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F002_S000_I002
description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\
pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\
\ unconditional jump)\npc += Sext({imm[20:1], 1’b0})"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_jal_cg.cp_rd_toggle
comments: ''
- 001_JALR: !Subfeature
name: 001_JALR
tag: VP_IP002_P001
next_elt_id: 3
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F002_S001_I000
description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\
pc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_jalr_cg.cp_rs1\nisacov.rv32i_jalr_cg.cp_rd\nisacov.rv32i_jalr_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F002_S001_I001
description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\
pc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmi value is +ve, -ve, and zero\nAll bits\
\ of immi are toggled\nAll bits of rs1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_jalr_cg.cp_immi_value\nisacov.rv32i_jalr_cg.cp_immi_toggle\n\
isacov.rv32i_jalr_cg.cp_rs1_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F002_S001_I002
description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\
pc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_jalr_cg.cp_rd_toggle
comments: ''
- 002_BEQ: !Subfeature
name: 002_BEQ
tag: VP_IP002_P002
next_elt_id: 3
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F002_S002_I000
description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\
\ else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_beq_cg.cp_rs1\nisacov.rv32i_beq_cg.cp_rs2"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F002_S002_I001
description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\
\ else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\
\ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\
\ toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_beq_cg.cp_immb_value\nisacov.rv32i_beq_cg.cp_rs1_toggle\n\
isacov.rv32i_beq_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F002_S002_I002
description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\
\ else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nBranch taken or not-taken"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_beq_cg.cp_branch_taken
comments: ''
- 003_BNE: !Subfeature
name: 003_BNE
tag: VP_IP002_P003
next_elt_id: 3
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F002_S003_I000
description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\
\ else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_bne_cg.cp_rs1\nisacov.rv32i_bne_cg.cp_rs2"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F002_S003_I001
description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\
\ else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\
\ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\
\ toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_bne_cg.cp_immb_value\nisacov.rv32i_bne_cg.cp_rs1_toggle\n\
isacov.rv32i_bne_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F002_S003_I002
description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\
\ else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nBranch taken or not-taken"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_bne_cg.cp_branch_taken
comments: ''
- 004_BLT: !Subfeature
name: 004_BLT
tag: VP_IP002_P004
next_elt_id: 3
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F002_S004_I000
description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ < rs2) else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_blt_cg.cp_rs1\nisacov.rv32i_blt_cg.cp_rs2"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F002_S004_I001
description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ < rs2) else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\
\ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\
\ toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_blt_cg.cp_immb_value\nisacov.rv32i_blt_cg.cp_rs1_toggle\n\
isacov.rv32i_blt_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F002_S004_I002
description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ < rs2) else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nBranch taken or not-taken"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_blt_cg.cp_branch_taken
comments: ''
- 005_BGE: !Subfeature
name: 005_BGE
tag: VP_IP002_P005
next_elt_id: 6
display_order: 5
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F002_S005_I000
description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ >= rs2) else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_bge_cg.cp_rs1\nisacov.rv32i_bge_cg.cp_rs2"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F002_S005_I001
description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ >= rs2) else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\
\ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\
\ toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_bge_cg.cp_immb_value\nisacov.rv32i_bge_cg.cp_rs1_toggle\n\
isacov.rv32i_bge_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F002_S005_I002
description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ >= rs2) else pc += 4\npc is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nBranch taken or not-taken"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_bge_cg.cp_branch_taken
comments: ''
- 006_BLTU: !Subfeature
name: 006_BLTU
tag: VP_IP002_P006
next_elt_id: 3
display_order: 6
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F002_S006_I000
description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ < rs2) else pc += 4\npc is calculated using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_bltu_cg.cp_rs1\nisacov.rv32i_bltu_cg.cp_rs2"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F002_S006_I001
description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ < rs2) else pc += 4\npc is calculated using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\
\ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\
\ toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_bltu_cg.cp_immb_value\nisacov.rv32i_bltu_cg.cp_rs1_toggle\n\
isacov.rv32i_bltu_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F002_S006_I002
description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ < rs2) else pc += 4\npc is calculated using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nBranch taken or not-taken"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_bltu_cg.cp_branch_taken
comments: ''
- 007_BGEU: !Subfeature
name: 007_BGEU
tag: VP_IP002_P007
next_elt_id: 3
display_order: 7
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F002_S007_I000
description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_bgeu_cg.cp_rs1\nisacov.rv32i_bgeu_cg.cp_rs2"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F002_S007_I001
description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\
\ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\
\ toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_bgeu_cg.cp_immb_value\nisacov.rv32i_bgeu_cg.cp_rs1_toggle\n\
isacov.rv32i_bgeu_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F002_S007_I002
description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\
\ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nBranch taken or not-taken"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_bgeu_cg.cp_branch_taken
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

1333
cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck
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!Feature
next_elt_id: 8
name: RV32I Load and Store Instructions
id: 3
display_order: 3
subfeatures: !!omap
- 000_LB: !Subfeature
name: 000_LB
tag: VP_IP003_P000
next_elt_id: 3
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F003_S000_I000
description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\
\ using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lb_cg.cp_rs1\nisacov.rv32i_lb_cg.cp_rd\nisacov.rv32i_lb_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F003_S000_I001
description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\
\ using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\
\ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\
\ toggled\nAll bits of immi are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lb_cg.cp_immi_value\nisacov.rv32i_lb_cg.cp_rs1_toggle\n\
isacov.rv32i_lb_cg.cp_immi_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F003_S000_I002
description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\
\ using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lb_cg.cp_rd_value\nisacov.rv32i_lb_cg.cp_rd_toggle"
comments: ''
- 001_LH: !Subfeature
name: 001_LH
tag: VP_IP003_P001
next_elt_id: 3
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F003_S001_I000
description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\
\ using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lh_cg.cp_rs1\nisacov.rv32i_lh_cg.cp_rd\nisacov.rv32i_lh_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F003_S001_I001
description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\
\ using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\
\ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\
\ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\
\ from memory"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lh_cg.cp_immi_value\nisacov.rv32i_lh_cg.cp_rs1_toggle\n\
isacov.rv32i_lh_cg.cp_immi_toggle\nisacov.rv32i_lh_cg.cp_aligned"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F003_S001_I002
description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\
\ using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lh_cg.cp_rd_value\nisacov.rv32i_lh_cg.cp_rd_toggle"
comments: ''
- 002_LW: !Subfeature
name: 002_LW
tag: VP_IP003_P002
next_elt_id: 3
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F003_S002_I000
description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\
\ using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lw_cg.cp_rs1\nisacov.rv32i_lw_cg.cp_rd\nisacov.rv32i_lw_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F003_S002_I001
description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\
\ using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\
\ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\
\ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\
\ from memory"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lw_cg.cp_immi_value\nisacov.rv32i_lw_cg.cp_rs1_toggle\n\
isacov.rv32i_lw_cg.cp_immi_toggle\nisacov.rv32i_lw_cg.cp_aligned"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F003_S002_I002
description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\
\ using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lw_cg.cp_rd_value\nisacov.rv32i_lw_cg.cp_rd_toggle"
comments: ''
- 003_LBU: !Subfeature
name: 003_LBU
tag: VP_IP003_P003
next_elt_id: 3
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F003_S003_I000
description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\
\ using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lbu_cg.cp_rs1\nisacov.rv32i_lbu_cg.cp_rd\nisacov.rv32i_lbu_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F003_S003_I001
description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\
\ using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\
\ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\
\ toggled\nAll bits of immi are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lbu_cg.cp_immi_value\nisacov.rv32i_lbu_cg.cp_rs1_toggle\n\
isacov.rv32i_lbu_cg.cp_immi_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F003_S003_I002
description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\
\ using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd[7:0] are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lbu_cg.cp_rd_value\nisacov.rv32i_lbu_cg.cp_rd_toggle"
comments: ''
- 004_LHU: !Subfeature
name: 004_LHU
tag: VP_IP003_P004
next_elt_id: 3
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F003_S004_I000
description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\
\ using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lhu_cg.cp_rs1\nisacov.rv32i_lhu_cg.cp_rd\nisacov.rv32i_lhu_cg.cp_rd_rs1_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F003_S004_I001
description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\
\ using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\
\ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\
\ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\
\ from memory"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lhu_cg.cp_immi_value\nisacov.rv32i_lhu_cg.cp_rs1_toggle\n\
isacov.rv32i_lhu_cg.cp_immi_toggle\nisacov.rv32i_lhu_cg.cp_aligned"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F003_S004_I002
description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\
\ using unsigned arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd[15:0] are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_lhu_cg.cp_rd_value\nisacov.rv32i_lhu_cg.cp_rd_toggle"
comments: ''
- 005_SB: !Subfeature
name: 005_SB
tag: VP_IP003_P005
next_elt_id: 3
display_order: 5
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F003_S005_I000
description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sb_cg.cp_rs1\nisacov.rv32i_sb_cg.cp_rs2"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F003_S005_I001
description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\
\ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\
\ toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sb_cg.cp_imms_value\nisacov.rv32i_sb_cg.cp_rs1_toggle\n\
isacov.rv32i_sb_cg.cp_rs2_toggle\nisacov.rv32i_sb_cg.cp_imms_toggle"
comments: ''
- 006_SH: !Subfeature
name: 006_SH
tag: VP_IP003_P006
next_elt_id: 2
display_order: 6
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F003_S006_I000
description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sh_cg.cp_rs1\nisacov.rv32i_sh_cg.cp_rs2"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F003_S006_I001
description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\
\ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\
\ toggled\nUnaligned and aligned accesses to memory"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sh_cg.cp_imms_value\nisacov.rv32i_sh_cg.cp_rs1_toggle\n\
isacov.rv32i_sh_cg.cp_rs2_toggle\nisacov.rv32i_sh_cg.cp_imms_toggle\nisacov.rv32i_sh_cg.cp_aligned"
comments: ''
- 007_SW: !Subfeature
name: 007_SW
tag: VP_IP003_P007
next_elt_id: 2
display_order: 7
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F003_S007_I000
description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sw_cg.cp_rs1\nisacov.rv32i_sw_cg.cp_rs2"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F003_S007_I001
description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\
\ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\
\ toggled\nUnaligned and aligned accesses to memory"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32i_sw_cg.cp_imms_value\nisacov.rv32i_sw_cg.cp_rs1_toggle\n\
isacov.rv32i_sw_cg.cp_rs2_toggle\nisacov.rv32i_sw_cg.cp_imms_toggle\nisacov.rv32i_sw_cg.cp_aligned"
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

157
cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck
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@ -1,157 +0,0 @@
(VRV32I Memory Ordering Instructions
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I1
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I4
sVwid_order
p12
I4
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_FENCE
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I1
sg8
g17
sVtag
p23
VVP_IP004_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F004_S000_I000
p34
sVdescription
p35
VFence operation executed\u000aImplementation is microarchitecture specific
p36
sVpurpose
p37
VISA\u000aChapter 2.7
p38
sVverif_goals
p39
VInstruction executed
p40
sVcoverage_loc
p41
Visacov.rv32i_fence.cp_fixed
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
V
p48
sVstatus
p49
g48
sVsimu_target_list
p50
(lp51
sg15
(lp52
sVrfu_list_2
p53
(lp54
sg13
(dp55
Vlock_status
p56
I0
ssbtp57
asVrfu_list_1
p58
(lp59
sg53
(lp60
sg13
(dp61
sbtp62
asVrfu_list_0
p63
(lp64
sg58
(lp65
sVvptool_gitrev
p66
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p67
sVio_fmt_gitrev
p68
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p69
sVconfig_gitrev
p70
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p71
sVymlcfg_gitrev
p72
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p73
sbtp74
.

33
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!Feature
next_elt_id: 1
name: RV32I Memory Ordering Instructions
id: 4
display_order: 4
subfeatures: !!omap
- 000_FENCE: !Subfeature
name: 000_FENCE
tag: VP_IP004_P000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F004_S000_I000
description: "Fence operation executed\nImplementation is microarchitecture\
\ specific"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Instruction executed
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_fence.cp_fixed
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

284
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@ -1,284 +0,0 @@
(VRV32I Environment Call and Breakpoints
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I2
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I5
sVwid_order
p12
I5
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_ECALL
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I2
sg8
g17
sVtag
p23
VVP_IP005_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F005_S000_I000
p34
sVdescription
p35
VSoftware exception vector entered
p36
sVpurpose
p37
VISA\u000aChapter 2.8
p38
sVverif_goals
p39
VInstruction executed
p40
sVcoverage_loc
p41
Visacov.rv32i_ecall.cp_fixed
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
V
p48
sVstatus
p49
g48
sVsimu_target_list
p50
(lp51
sg15
(lp52
sVrfu_list_2
p53
(lp54
sg13
(dp55
Vlock_status
p56
I0
ssbtp57
a(V001
p58
g1
(g29
g3
Ntp59
Rp60
(dp61
g8
V001
p62
sg23
VVP_ISA_F005_S000_I001
p63
sg35
VReturn control to a debugger
p64
sg37
VISA\u000aChapter 2.8
p65
sg39
VInstruction executed
p66
sg41
Visacov.rv32i_ebreak.cp_fixed
p67
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp68
sg15
(lp69
sg53
(lp70
sg13
(dp71
g56
I0
ssbtp72
asVrfu_list_1
p73
(lp74
sg53
(lp75
sg13
(dp76
sbtp77
a(V001_EBREAK
p78
g1
(g18
g3
Ntp79
Rp80
(dp81
g22
I1
sg8
g78
sg23
VVP_IP005_P001
p82
sg25
(dp83
sg12
I1
sg15
(lp84
(V000
p85
g1
(g29
g3
Ntp86
Rp87
(dp88
g8
V000
p89
sg23
VVP_ISA_F005_S001_I000
p90
sg35
VReturn control to a debugger
p91
sg37
VISA\u000aChapter 2.8
p92
sg39
VInstruction executed
p93
sg41
Visacov.rv32i_ebreak.cp_fixed
p94
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp95
sg15
(lp96
sg53
(lp97
sg13
(dp98
Vlock_status
p99
I0
ssbtp100
asg73
(lp101
sg53
(lp102
sg13
(dp103
sbtp104
asVrfu_list_0
p105
(lp106
sg73
(lp107
sVvptool_gitrev
p108
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p109
sVio_fmt_gitrev
p110
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p111
sVconfig_gitrev
p112
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p113
sVymlcfg_gitrev
p114
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p115
sbtp116
.

70
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!Feature
next_elt_id: 2
name: RV32I Environment Call and Breakpoints
id: 5
display_order: 5
subfeatures: !!omap
- 000_ECALL: !Subfeature
name: 000_ECALL
tag: VP_IP005_P000
next_elt_id: 2
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F005_S000_I000
description: Software exception vector entered
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Instruction executed
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_ecall.cp_fixed
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F005_S000_I001
description: Return control to a debugger
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Instruction executed
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_ebreak.cp_fixed
comments: ''
- 001_EBREAK: !Subfeature
name: 001_EBREAK
tag: VP_IP005_P001
next_elt_id: 1
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F005_S001_I000
description: Return control to a debugger
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Instruction executed
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32i_ebreak.cp_fixed
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

780
cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck
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@ -1,780 +0,0 @@
(VRV32M Multiplication Operations
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I7
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I6
sVwid_order
p12
I6
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_MUL
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I3
sg8
g17
sVtag
p23
VVP_IP000_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F000_S000_I000
p34
sVdescription
p35
Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored.
p36
sVpurpose
p37
VUnprivileged ISA\u000aChapter 7.1
p38
sVverif_goals
p39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p40
sVcoverage_loc
p41
Visacov.rv32m_mul_cg.cp_rs1\u000aisacov.rv32m_mul_cg.cp_rs2\u000aisacov.rv32m_mul_cg.cp_rd\u000aisacov.rv32m_mul_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mul_cg.cp_rd_rs2_hazard
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
V
p48
sVstatus
p49
g48
sVsimu_target_list
p50
(lp51
sg15
(lp52
sVrfu_list_2
p53
(lp54
sg13
(dp55
Vlock_status
p56
I0
ssbtp57
a(V001
p58
g1
(g29
g3
Ntp59
Rp60
(dp61
g8
V001
p62
sg23
VVP_ISA_F000_S000_I001
p63
sg35
Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored.
p64
sg37
VUnprivileged ISA\u000aChapter 7.1
p65
sg39
VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p66
sg41
Visacov.rv32m_mul_cg.cp_rs1_value\u000aisacov.rv32m_mul_cg.cp_rs2_value\u000aisacov.rv32m_mul_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mul_cg.cp_rs1_toggle \u000aisacov.rv32m_mul_cg.cp_rs2_toggle
p67
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp68
sg15
(lp69
sg53
(lp70
sg13
(dp71
g56
I0
ssbtp72
a(V002
p73
g1
(g29
g3
Ntp74
Rp75
(dp76
g8
V002
p77
sg23
VVP_ISA_F000_S000_I002
p78
sg35
Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored.
p79
sg37
VUnprivileged ISA\u000aChapter 7.1
p80
sg39
VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled
p81
sg41
Visacov.rv32m_mul_cg.cp_rd_value\u000aisacov.rv32m_mul_cg.cp_rd_toggle
p82
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp83
sg15
(lp84
sg53
(lp85
sg13
(dp86
g56
I0
ssbtp87
asVrfu_list_1
p88
(lp89
sg53
(lp90
sg13
(dp91
sbtp92
a(V001_MULH
p93
g1
(g18
g3
Ntp94
Rp95
(dp96
g22
I3
sg8
g93
sg23
VVP_IP000_P001
p97
sg25
(dp98
sg12
I1
sg15
(lp99
(V000
p100
g1
(g29
g3
Ntp101
Rp102
(dp103
g8
V000
p104
sg23
VVP_ISA_F000_S001_I000
p105
sg35
Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers
p106
sg37
VUnprivileged ISA\u000aChapter 7.1
p107
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p108
sg41
Visacov.rv32m_mulh_cg.cp_rs1\u000aisacov.rv32m_mulh_cg.cp_rs2\u000aisacov.rv32m_mulh_cg.cp_rd\u000aisacov.rv32m_mulh_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulh_cg.cp_rd_rs2_hazard
p109
sg43
I3
sg44
I3
sg45
I1
sg46
I32
sg47
g48
sg49
g48
sg50
(lp110
sg15
(lp111
sg53
(lp112
sg13
(dp113
g56
I0
ssbtp114
a(V001
p115
g1
(g29
g3
Ntp116
Rp117
(dp118
g8
V001
p119
sg23
VVP_ISA_F000_S001_I001
p120
sg35
Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers
p121
sg37
VUnprivileged ISA\u000aChapter 7.1
p122
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p123
sg41
Visacov.rv32m_mulh_cg.cp_rs1_value\u000aisacov.rv32m_mulh_cg.cp_rs2_value\u000aisacov.rv32m_mulh_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulh_cg.cp_rs1_toggle \u000aisacov.rv32m_mulh_cg.cp_rs2_toggle
p124
sg43
I3
sg44
I3
sg45
I1
sg46
I32
sg47
g48
sg49
g48
sg50
(lp125
sg15
(lp126
sg53
(lp127
sg13
(dp128
g56
I0
ssbtp129
a(V002
p130
g1
(g29
g3
Ntp131
Rp132
(dp133
g8
V002
p134
sg23
VVP_ISA_F000_S001_I002
p135
sg35
Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers
p136
sg37
VUnprivileged ISA\u000aChapter 7.1
p137
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p138
sg41
Visacov.rv32m_mulh_cg.cp_rd_value\u000aisacov.rv32m_mulh_cg.cp_rd_toggle
p139
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp140
sg15
(lp141
sg53
(lp142
sg13
(dp143
g56
I0
ssbtp144
asg88
(lp145
sg53
(lp146
sg13
(dp147
sbtp148
a(V002_MULHU
p149
g1
(g18
g3
Ntp150
Rp151
(dp152
g22
I3
sg8
g149
sg23
VVP_IP000_P002
p153
sg25
(dp154
sg12
I2
sg15
(lp155
(V000
p156
g1
(g29
g3
Ntp157
Rp158
(dp159
g8
V000
p160
sg23
VVP_ISA_F000_S002_I000
p161
sg35
Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers
p162
sg37
VUnprivileged ISA\u000aChapter 7.1
p163
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p164
sg41
Visacov.rv32m_mulhu_cg.cp_rs1\u000aisacov.rv32m_mulhu_cg.cp_rs2\u000aisacov.rv32m_mulhu_cg.cp_rd\u000aisacov.rv32m_mulhu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulhu_cg.cp_rd_rs2_hazard
p165
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp166
sg15
(lp167
sg53
(lp168
sg13
(dp169
g56
I0
ssbtp170
a(V001
p171
g1
(g29
g3
Ntp172
Rp173
(dp174
g8
V001
p175
sg23
VVP_ISA_F000_S002_I001
p176
sg35
Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers
p177
sg37
VUnprivileged ISA\u000aChapter 7.1
p178
sg39
VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p179
sg41
Visacov.rv32m_mulhu_cg.cp_rs1_value\u000aisacov.rv32m_mulhu_cg.cp_rs2_value\u000aisacov.rv32m_mulhu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulhu_cg.cp_rs1_toggle \u000aisacov.rv32m_mulhu_cg.cp_rs2_toggle
p180
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp181
sg15
(lp182
sg53
(lp183
sg13
(dp184
g56
I0
ssbtp185
a(V002
p186
g1
(g29
g3
Ntp187
Rp188
(dp189
g8
V002
p190
sg23
VVP_ISA_F000_S002_I002
p191
sg35
Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers
p192
sg37
VUnprivileged ISA\u000aChapter 7.1
p193
sg39
VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled
p194
sg41
Visacov.rv32m_mulhu_cg.cp_rd_value\u000aisacov.rv32m_mulhu_cg.cp_rd_toggle
p195
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp196
sg15
(lp197
sg53
(lp198
sg13
(dp199
g56
I0
ssbtp200
asg88
(lp201
sg53
(lp202
sg13
(dp203
sbtp204
a(V003_MULHSU
p205
g1
(g18
g3
Ntp206
Rp207
(dp208
g22
I3
sg8
g205
sg23
VVP_IP000_P003
p209
sg25
(dp210
sg12
I3
sg15
(lp211
(V000
p212
g1
(g29
g3
Ntp213
Rp214
(dp215
g8
V000
p216
sg23
VVP_ISA_F000_S003_I000
p217
sg35
Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number
p218
sg37
VUnprivileged ISA\u000aChapter 7.1
p219
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p220
sg41
Visacov.rv32m_mulhsu_cg.cp_rs1\u000aisacov.rv32m_mulhsu_cg.cp_rs2\u000aisacov.rv32m_mulhsu_cg.cp_rd\u000aisacov.rv32m_mulhsu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulhsu_cg.cp_rd_rs2_hazard
p221
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp222
sg15
(lp223
sg53
(lp224
sg13
(dp225
g56
I0
ssbtp226
a(V001
p227
g1
(g29
g3
Ntp228
Rp229
(dp230
g8
V001
p231
sg23
VVP_ISA_F000_S003_I001
p232
sg35
Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number
p233
sg37
VUnprivileged ISA\u000aChapter 7.1
p234
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p235
sg41
Visacov.rv32m_mulhsu_cg.cp_rs1_value\u000aisacov.rv32m_mulhsu_cg.cp_rs2_value\u000aisacov.rv32m_mulhsu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulhsu_cg.cp_rs1_toggle \u000aisacov.rv32m_mulhsu_cg.cp_rs2_toggle
p236
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp237
sg15
(lp238
sg53
(lp239
sg13
(dp240
g56
I0
ssbtp241
a(V002
p242
g1
(g29
g3
Ntp243
Rp244
(dp245
g8
V002
p246
sg23
VVP_ISA_F000_S003_I002
p247
sg35
Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number
p248
sg37
VUnprivileged ISA\u000aChapter 7.1
p249
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p250
sg41
Visacov.rv32m_mulhsu_cg.cp_rd_value\u000aisacov.rv32m_mulhsu_cg.cp_rd_toggle
p251
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp252
sg15
(lp253
sg53
(lp254
sg13
(dp255
g56
I0
ssbtp256
asg88
(lp257
sg53
(lp258
sg13
(dp259
sbtp260
asVrfu_list_0
p261
(lp262
sg88
(lp263
sVvptool_gitrev
p264
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p265
sVio_fmt_gitrev
p266
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p267
sVconfig_gitrev
p268
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p269
sVymlcfg_gitrev
p270
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p271
sbtp272
.

275
cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml Normal file
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@ -0,0 +1,275 @@
!Feature
next_elt_id: 7
name: RV32M Multiplication Operations
id: 6
display_order: 6
subfeatures: !!omap
- 000_MUL: !Subfeature
name: 000_MUL
tag: VP_IP000_P000
next_elt_id: 3
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F006_S000_I000
description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\
\ is ignored."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_mul_cg.cp_rs1\nisacov.rv32m_mul_cg.cp_rs2\nisacov.rv32m_mul_cg.cp_rd\n\
isacov.rv32m_mul_cg.cp_rd_rs1_hazard\nisacov.rv32m_mul_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F006_S000_I001
description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\
\ is ignored."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\
\ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_mul_cg.cp_rs1_value\nisacov.rv32m_mul_cg.cp_rs2_value\n\
isacov.rv32m_mul_cg.cross_rs1_rs2_value\nisacov.rv32m_mul_cg.cp_rs1_toggle\
\ \nisacov.rv32m_mul_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F006_S000_I002
description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\
\ is ignored."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_mul_cg.cp_rd_value\nisacov.rv32m_mul_cg.cp_rd_toggle"
comments: ''
- 001_MULH: !Subfeature
name: 001_MULH
tag: VP_IP000_P001
next_elt_id: 3
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F006_S001_I000
description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\
\ rs1 and rs2 treated as signed numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 32
coverage_loc: "isacov.rv32m_mulh_cg.cp_rs1\nisacov.rv32m_mulh_cg.cp_rs2\n\
isacov.rv32m_mulh_cg.cp_rd\nisacov.rv32m_mulh_cg.cp_rd_rs1_hazard\nisacov.rv32m_mulh_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F006_S001_I001
description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\
\ rs1 and rs2 treated as signed numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
\ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 32
coverage_loc: "isacov.rv32m_mulh_cg.cp_rs1_value\nisacov.rv32m_mulh_cg.cp_rs2_value\n\
isacov.rv32m_mulh_cg.cross_rs1_rs2_value\nisacov.rv32m_mulh_cg.cp_rs1_toggle\
\ \nisacov.rv32m_mulh_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F006_S001_I002
description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\
\ rs1 and rs2 treated as signed numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_mulh_cg.cp_rd_value\nisacov.rv32m_mulh_cg.cp_rd_toggle"
comments: ''
- 002_MULHU: !Subfeature
name: 002_MULHU
tag: VP_IP000_P002
next_elt_id: 3
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F006_S002_I000
description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\
\ rs1 and rs2 treated as unsigned numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_mulhu_cg.cp_rs1\nisacov.rv32m_mulhu_cg.cp_rs2\n\
isacov.rv32m_mulhu_cg.cp_rd\nisacov.rv32m_mulhu_cg.cp_rd_rs1_hazard\nisacov.rv32m_mulhu_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F006_S002_I001
description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\
\ rs1 and rs2 treated as unsigned numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\
\ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_mulhu_cg.cp_rs1_value\nisacov.rv32m_mulhu_cg.cp_rs2_value\n\
isacov.rv32m_mulhu_cg.cross_rs1_rs2_value\nisacov.rv32m_mulhu_cg.cp_rs1_toggle\
\ \nisacov.rv32m_mulhu_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F006_S002_I002
description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\
\ rs1 and rs2 treated as unsigned numbers"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_mulhu_cg.cp_rd_value\nisacov.rv32m_mulhu_cg.cp_rd_toggle"
comments: ''
- 003_MULHSU: !Subfeature
name: 003_MULHSU
tag: VP_IP000_P003
next_elt_id: 3
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F006_S003_I000
description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\
\ treated as signed number, rs2 treated as unsigned number"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rs1\nisacov.rv32m_mulhsu_cg.cp_rs2\n\
isacov.rv32m_mulhsu_cg.cp_rd\nisacov.rv32m_mulhsu_cg.cp_rd_rs1_hazard\n\
isacov.rv32m_mulhsu_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F006_S003_I001
description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\
\ treated as signed number, rs2 treated as unsigned number"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
\ is non-zero and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rs1_value\nisacov.rv32m_mulhsu_cg.cp_rs2_value\n\
isacov.rv32m_mulhsu_cg.cross_rs1_rs2_value\nisacov.rv32m_mulhsu_cg.cp_rs1_toggle\
\ \nisacov.rv32m_mulhsu_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F006_S003_I002
description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\
\ treated as signed number, rs2 treated as unsigned number"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rd_value\nisacov.rv32m_mulhsu_cg.cp_rd_toggle"
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

976
cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck
View file

@ -1,976 +0,0 @@
(VRV32M Division Operations
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I4
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I7
sVwid_order
p12
I7
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_DIV
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I4
sg8
g17
sVtag
p23
VVP_IP007_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F007_S000_I000
p34
sVdescription
p35
Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero
p36
sVpurpose
p37
VUnprivileged ISA\u000aChapter 7.2
p38
sVverif_goals
p39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p40
sVcoverage_loc
p41
Visacov.rv32m_div_cg.cp_rs1\u000aisacov.rv32m_div_cg.cp_rs2\u000aisacov.rv32m_div_cg.cp_rd\u000aisacov.rv32m_div_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_div_cg.cp_rd_rs2_hazard
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
V
p48
sVstatus
p49
g48
sVsimu_target_list
p50
(lp51
sg15
(lp52
sVrfu_list_2
p53
(lp54
sg13
(dp55
Vlock_status
p56
I0
ssbtp57
a(V001
p58
g1
(g29
g3
Ntp59
Rp60
(dp61
g8
V001
p62
sg23
VVP_ISA_F007_S000_I001
p63
sg35
Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero
p64
sg37
VUnprivileged ISA\u000aChapter 7.2
p65
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p66
sg41
Visacov.rv32m_div_cg.cp_rs1_value\u000aisacov.rv32m_div_cg.cp_rs2_value\u000aisacov.rv32m_div_cg.cross_rs1_rs2_value\u000aisacov.rv32m_div_cg.cp_rs1_toggle \u000aisacov.rv32m_div_cg.cp_rs2_toggle
p67
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp68
sg15
(lp69
sg53
(lp70
sg13
(dp71
g56
I0
ssbtp72
a(V002
p73
g1
(g29
g3
Ntp74
Rp75
(dp76
g8
V002
p77
sg23
VVP_ISA_F007_S000_I002
p78
sg35
Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero
p79
sg37
VUnprivileged ISA\u000aChapter 7.2
p80
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p81
sg41
Visacov.rv32m_div_cg.cp_rs1_value\u000aisacov.rv32m_div_cg.cp_rs2_value\u000aisacov.rv32m_div_cg.cross_rs1_rs2_value\u000aisacov.rv32m_div_cg.cp_rs1_toggle \u000aisacov.rv32m_div_cg.cp_rs2_toggle
p82
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp83
sg15
(lp84
sg53
(lp85
sg13
(dp86
g56
I0
ssbtp87
a(V003
p88
g1
(g29
g3
Ntp89
Rp90
(dp91
g8
V003
p92
sg23
VVP_ISA_F007_S000_I003
p93
sg35
Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero
p94
sg37
VUnprivileged ISA\u000aChapter 7.2
p95
sg39
VExercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns rd = -2^31).\u000aExercise division by zero (returns -1 ; all bits set)
p96
sg41
Visacov.rv32m_div_results_cg.cp_div_special_results\u000aisacov.rv32m_div_results_cg.cp_div_arithmetic_overflow
p97
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp98
sg15
(lp99
sg53
(lp100
sg13
(dp101
g56
I0
ssbtp102
asVrfu_list_1
p103
(lp104
sg53
(lp105
sg13
(dp106
sbtp107
a(V001_REM
p108
g1
(g18
g3
Ntp109
Rp110
(dp111
g22
I4
sg8
g108
sg23
VVP_IP007_P001
p112
sg25
(dp113
sg12
I1
sg15
(lp114
(V000
p115
g1
(g29
g3
Ntp116
Rp117
(dp118
g8
V000
p119
sg23
VVP_ISA_F007_S001_I000
p120
sg35
Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1)
p121
sg37
VUnprivileged ISA\u000aChapter 7.2
p122
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p123
sg41
Visacov.rv32m_rem_cg.cp_rs1\u000aisacov.rv32m_rem_cg.cp_rs2\u000aisacov.rv32m_rem_cg.cp_rd\u000aisacov.rv32m_rem_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_rem_cg.cp_rd_rs2_hazard
p124
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp125
sg15
(lp126
sg53
(lp127
sg13
(dp128
g56
I0
ssbtp129
a(V001
p130
g1
(g29
g3
Ntp131
Rp132
(dp133
g8
V001
p134
sg23
VVP_ISA_F007_S001_I001
p135
sg35
Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1)
p136
sg37
VUnprivileged ISA\u000aChapter 7.2
p137
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p138
sg41
Visacov.rv32m_rem_cg.cp_rs1_value\u000aisacov.rv32m_rem_cg.cp_rs2_value\u000aisacov.rv32m_rem_cg.cross_rs1_rs2_value\u000aisacov.rv32m_rem_cg.cp_rs1_toggle \u000aisacov.rv32m_rem_cg.cp_rs2_toggle
p139
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp140
sg15
(lp141
sg53
(lp142
sg13
(dp143
g56
I0
ssbtp144
a(V002
p145
g1
(g29
g3
Ntp146
Rp147
(dp148
g8
V002
p149
sg23
VVP_ISA_F007_S001_I002
p150
sg35
Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1)
p151
sg37
VUnprivileged ISA\u000aChapter 7.2
p152
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p153
sg41
Visacov.rv32m_rem_cg.cp_rd_value\u000aisacov.rv32m_rem_cg.cp_rd_toggle
p154
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp155
sg15
(lp156
sg53
(lp157
sg13
(dp158
g56
I0
ssbtp159
a(V003
p160
g1
(g29
g3
Ntp161
Rp162
(dp163
g8
V003
p164
sg23
VVP_ISA_F007_S001_I003
p165
sg35
Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1)
p166
sg37
VUnprivileged ISA\u000aChapter 7.2
p167
sg39
VExercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns rd = 0).\u000aExercise division by zero (returns rs1)
p168
sg41
Visacov.rv32m_rem_results_cg.cp_div_zero\u000aisacov.rv32m_rem_results_cg.cp_div_arithmetic_overflow
p169
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp170
sg15
(lp171
sg53
(lp172
sg13
(dp173
g56
I0
ssbtp174
asg103
(lp175
sg53
(lp176
sg13
(dp177
sbtp178
a(V002_DIVU
p179
g1
(g18
g3
Ntp180
Rp181
(dp182
g22
I4
sg8
g179
sg23
VVP_IP007_P002
p183
sg25
(dp184
sg12
I2
sg15
(lp185
(V000
p186
g1
(g29
g3
Ntp187
Rp188
(dp189
g8
V000
p190
sg23
VVP_ISA_F007_S002_I000
p191
sg35
Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero
p192
sg37
VUnprivileged ISA\u000aChapter 7.2
p193
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p194
sg41
Visacov.rv32m_divu_cg.cp_rs1\u000aisacov.rv32m_divu_cg.cp_rs2\u000aisacov.rv32m_divu_cg.cp_rd\u000aisacov.rv32m_divu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_divu_cg.cp_rd_rs2_hazard
p195
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp196
sg15
(lp197
sg53
(lp198
sg13
(dp199
g56
I0
ssbtp200
a(V001
p201
g1
(g29
g3
Ntp202
Rp203
(dp204
g8
V001
p205
sg23
VVP_ISA_F007_S002_I001
p206
sg35
Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero
p207
sg37
VUnprivileged ISA\u000aChapter 7.2
p208
sg39
VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p209
sg41
Visacov.rv32m_divu_cg.cp_rs1_value\u000aisacov.rv32m_divu_cg.cp_rs2_value\u000aisacov.rv32m_divu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_divu_cg.cp_rs1_toggle \u000aisacov.rv32m_divu_cg.cp_rs2_toggle
p210
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp211
sg15
(lp212
sg53
(lp213
sg13
(dp214
g56
I0
ssbtp215
a(V002
p216
g1
(g29
g3
Ntp217
Rp218
(dp219
g8
V002
p220
sg23
VVP_ISA_F007_S002_I002
p221
sg35
Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero
p222
sg37
VUnprivileged ISA\u000aChapter 7.2
p223
sg39
VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled
p224
sg41
Visacov.rv32m_divu_cg.cp_rd_value\u000aisacov.rv32m_divu_cg.cp_rd_toggle
p225
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp226
sg15
(lp227
sg53
(lp228
sg13
(dp229
g56
I0
ssbtp230
a(V003
p231
g1
(g29
g3
Ntp232
Rp233
(dp234
g8
V003
p235
sg23
VVP_ISA_F007_S002_I003
p236
sg35
Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero
p237
sg37
VUnprivileged ISA\u000aChapter 7.2
p238
sg39
VExercise division by zero (returns 2^32-1 ; all bits set)
p239
sg41
Visacov.rv32m_divu_results_cg.cp_div_zero
p240
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp241
sg15
(lp242
sg53
(lp243
sg13
(dp244
g56
I0
ssbtp245
asg103
(lp246
sg53
(lp247
sg13
(dp248
sbtp249
a(V003_REMU
p250
g1
(g18
g3
Ntp251
Rp252
(dp253
g22
I4
sg8
g250
sg23
VVP_IP007_P003
p254
sg25
(dp255
sg12
I3
sg15
(lp256
(V000
p257
g1
(g29
g3
Ntp258
Rp259
(dp260
g8
V000
p261
sg23
VVP_ISA_F007_S003_I000
p262
sg35
Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU
p263
sg37
VUnprivileged ISA\u000aChapter 7.2
p264
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p265
sg41
Visacov.rv32m_remu_cg.cp_rs1\u000aisacov.rv32m_remu_cg.cp_rs2\u000aisacov.rv32m_remu_cg.cp_rd\u000aisacov.rv32m_remu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_remu_cg.cp_rd_rs2_hazard
p266
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp267
sg15
(lp268
sg53
(lp269
sg13
(dp270
g56
I0
ssbtp271
a(V001
p272
g1
(g29
g3
Ntp273
Rp274
(dp275
g8
V001
p276
sg23
VVP_ISA_F007_S003_I001
p277
sg35
Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU
p278
sg37
VUnprivileged ISA\u000aChapter 7.2
p279
sg39
VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p280
sg41
Visacov.rv32m_remu_cg.cp_rs1_value\u000aisacov.rv32m_remu_cg.cp_rs2_value\u000aisacov.rv32m_remu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_remu_cg.cp_rs1_toggle \u000aisacov.rv32m_remu_cg.cp_rs2_toggle
p281
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp282
sg15
(lp283
sg53
(lp284
sg13
(dp285
g56
I0
ssbtp286
a(V002
p287
g1
(g29
g3
Ntp288
Rp289
(dp290
g8
V002
p291
sg23
VVP_ISA_F007_S003_I002
p292
sg35
Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU
p293
sg37
VUnprivileged ISA\u000aChapter 7.2
p294
sg39
VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled
p295
sg41
Visacov.rv32m_remu_cg.cp_rd_value\u000aisacov.rv32m_remu_cg.cp_rd_toggle
p296
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp297
sg15
(lp298
sg53
(lp299
sg13
(dp300
g56
I0
ssbtp301
a(V003
p302
g1
(g29
g3
Ntp303
Rp304
(dp305
g8
V003
p306
sg23
VVP_ISA_F007_S003_I003
p307
sg35
Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU
p308
sg37
VUnprivileged ISA\u000aChapter 7.2
p309
sg39
VExercise division by zero (returns rs1)
p310
sg41
Visacov.rv32m_remu_results_cg.cp_div_zero
p311
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp312
sg15
(lp313
sg53
(lp314
sg13
(dp315
g56
I0
ssbtp316
asg103
(lp317
sg53
(lp318
sg13
(dp319
sbtp320
asVrfu_list_0
p321
(lp322
sg103
(lp323
sVvptool_gitrev
p324
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p325
sVio_fmt_gitrev
p326
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p327
sVconfig_gitrev
p328
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p329
sVymlcfg_gitrev
p330
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p331
sbtp332
.

350
cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml Normal file
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@ -0,0 +1,350 @@
!Feature
next_elt_id: 4
name: RV32M Division Operations
id: 7
display_order: 7
subfeatures: !!omap
- 000_DIV: !Subfeature
name: 000_DIV
tag: VP_IP007_P000
next_elt_id: 4
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F007_S000_I000
description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\
\ using signed arithmetic; rounding towards zero"
reqt_doc: "Unprivileged ISA\nChapter 7.2"
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_div_cg.cp_rs1\nisacov.rv32m_div_cg.cp_rs2\nisacov.rv32m_div_cg.cp_rd\n\
isacov.rv32m_div_cg.cp_rd_rs1_hazard\nisacov.rv32m_div_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F007_S000_I001
description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\
\ using signed arithmetic; rounding towards zero"
reqt_doc: "Unprivileged ISA\nChapter 7.2"
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
\ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\
isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\
\ \nisacov.rv32m_div_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F007_S000_I002
description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\
\ using signed arithmetic; rounding towards zero"
reqt_doc: "Unprivileged ISA\nChapter 7.2"
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\
isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\
\ \nisacov.rv32m_div_cg.cp_rs2_toggle"
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F007_S000_I003
description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\
\ using signed arithmetic; rounding towards zero"
reqt_doc: "Unprivileged ISA\nChapter 7.2"
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\
\ rd = -2^31).\nExercise division by zero (returns -1 ; all bits set)"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_div_results_cg.cp_div_special_results\nisacov.rv32m_div_results_cg.cp_div_arithmetic_overflow"
comments: ''
- 001_REM: !Subfeature
name: 001_REM
tag: VP_IP007_P001
next_elt_id: 4
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F007_S001_I000
description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
\ using signed arithmetic; remainder from the same division than DIV (the\
\ sign of rd equals the sign of rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_rem_cg.cp_rs1\nisacov.rv32m_rem_cg.cp_rs2\nisacov.rv32m_rem_cg.cp_rd\n\
isacov.rv32m_rem_cg.cp_rd_rs1_hazard\nisacov.rv32m_rem_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F007_S001_I001
description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
\ using signed arithmetic; remainder from the same division than DIV (the\
\ sign of rd equals the sign of rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
\ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_rem_cg.cp_rs1_value\nisacov.rv32m_rem_cg.cp_rs2_value\n\
isacov.rv32m_rem_cg.cross_rs1_rs2_value\nisacov.rv32m_rem_cg.cp_rs1_toggle\
\ \nisacov.rv32m_rem_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F007_S001_I002
description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
\ using signed arithmetic; remainder from the same division than DIV (the\
\ sign of rd equals the sign of rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_rem_cg.cp_rd_value\nisacov.rv32m_rem_cg.cp_rd_toggle"
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F007_S001_I003
description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
\ using signed arithmetic; remainder from the same division than DIV (the\
\ sign of rd equals the sign of rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\
\ rd = 0).\nExercise division by zero (returns rs1)"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_rem_results_cg.cp_div_zero\nisacov.rv32m_rem_results_cg.cp_div_arithmetic_overflow"
comments: ''
- 002_DIVU: !Subfeature
name: 002_DIVU
tag: VP_IP007_P002
next_elt_id: 4
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F007_S002_I000
description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\
\ using unsigned arithmetic; rounding towards zero"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_divu_cg.cp_rs1\nisacov.rv32m_divu_cg.cp_rs2\n\
isacov.rv32m_divu_cg.cp_rd\nisacov.rv32m_divu_cg.cp_rd_rs1_hazard\nisacov.rv32m_divu_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F007_S002_I001
description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\
\ using unsigned arithmetic; rounding towards zero"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\
\ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_divu_cg.cp_rs1_value\nisacov.rv32m_divu_cg.cp_rs2_value\n\
isacov.rv32m_divu_cg.cross_rs1_rs2_value\nisacov.rv32m_divu_cg.cp_rs1_toggle\
\ \nisacov.rv32m_divu_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F007_S002_I002
description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\
\ using unsigned arithmetic; rounding towards zero"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_divu_cg.cp_rd_value\nisacov.rv32m_divu_cg.cp_rd_toggle"
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F007_S002_I003
description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\
\ using unsigned arithmetic; rounding towards zero"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Exercise division by zero (returns 2^32-1 ; all bits set)
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32m_divu_results_cg.cp_div_zero
comments: ''
- 003_REMU: !Subfeature
name: 003_REMU
tag: VP_IP007_P003
next_elt_id: 4
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F007_S003_I000
description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
\ using unsigned arithmetic; remainder from the same division than DIVU"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_remu_cg.cp_rs1\nisacov.rv32m_remu_cg.cp_rs2\n\
isacov.rv32m_remu_cg.cp_rd\nisacov.rv32m_remu_cg.cp_rd_rs1_hazard\nisacov.rv32m_remu_cg.cp_rd_rs2_hazard"
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F007_S003_I001
description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
\ using unsigned arithmetic; remainder from the same division than DIVU"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\
\ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\
\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_remu_cg.cp_rs1_value\nisacov.rv32m_remu_cg.cp_rs2_value\n\
isacov.rv32m_remu_cg.cross_rs1_rs2_value\nisacov.rv32m_remu_cg.cp_rs1_toggle\
\ \nisacov.rv32m_remu_cg.cp_rs2_toggle"
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F007_S003_I002
description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
\ using unsigned arithmetic; remainder from the same division than DIVU"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: "isacov.rv32m_remu_cg.cp_rd_value\nisacov.rv32m_remu_cg.cp_rd_toggle"
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F007_S003_I003
description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
\ using unsigned arithmetic; remainder from the same division than DIVU"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Exercise division by zero (returns rs1)
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32m_remu_results_cg.cp_div_zero
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

520
cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck
View file

@ -1,520 +0,0 @@
(VRV32A Load-Reserved/Store-Conditional Instructions
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I2
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I8
sVwid_order
p12
I8
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_LR.W
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I4
sg8
g17
sVtag
p23
VVP_IP008_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F008_S000_I000
p34
sVdescription
p35
Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception
p36
sVpurpose
p37
VUnprivileged ISA\u000aChapter 8.2
p38
sVverif_goals
p39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
a(V001
p57
g1
(g29
g3
Ntp58
Rp59
(dp60
g8
V001
p61
sg23
VVP_ISA_F008_S000_I001
p62
sg35
Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception
p63
sg37
VUnprivileged ISA\u000aChapter 8.2
p64
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled
p65
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp66
sg15
(lp67
sg52
(lp68
sg13
(dp69
g55
I0
ssbtp70
a(V002
p71
g1
(g29
g3
Ntp72
Rp73
(dp74
g8
V002
p75
sg23
VVP_ISA_F008_S000_I002
p76
sg35
Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception
p77
sg37
VUnprivileged ISA\u000aChapter 8.2
p78
sg39
VOutput result:\u000a\u000aAll bits of rd are toggled
p79
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp80
sg15
(lp81
sg52
(lp82
sg13
(dp83
g55
I0
ssbtp84
a(V003
p85
g1
(g29
g3
Ntp86
Rp87
(dp88
g8
V003
p89
sg23
VVP_ISA_F008_S000_I003
p90
sg35
Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception
p91
sg37
VUnprivileged ISA\u000aChapter 8.2
p92
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exceptio
p93
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp94
sg15
(lp95
sg52
(lp96
sg13
(dp97
g55
I0
ssbtp98
asVrfu_list_1
p99
(lp100
sg52
(lp101
sg13
(dp102
sbtp103
a(V001_SC.W
p104
g1
(g18
g3
Ntp105
Rp106
(dp107
g22
I4
sg8
g104
sg23
VVP_IP008_P001
p108
sg25
(dp109
sg12
I1
sg15
(lp110
(V000
p111
g1
(g29
g3
Ntp112
Rp113
(dp114
g8
V000
p115
sg23
VVP_ISA_F008_S001_I000
p116
sg35
Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds.
p117
sg37
VUnprivileged ISA\u000aChapter 8.2
p118
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p119
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp120
sg15
(lp121
sg52
(lp122
sg13
(dp123
g55
I0
ssbtp124
a(V001
p125
g1
(g29
g3
Ntp126
Rp127
(dp128
g8
V001
p129
sg23
VVP_ISA_F008_S001_I001
p130
sg35
Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds.
p131
sg37
VUnprivileged ISA\u000aChapter 8.2
p132
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p133
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp134
sg15
(lp135
sg52
(lp136
sg13
(dp137
g55
I0
ssbtp138
a(V002
p139
g1
(g29
g3
Ntp140
Rp141
(dp142
g8
V002
p143
sg23
VVP_ISA_F008_S001_I002
p144
sg35
Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds.
p145
sg37
VUnprivileged ISA\u000aChapter 8.2
p146
sg39
VOutput result:\u000a\u000ard is either zero or non-zero to indicate success or failure, respectively
p147
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp148
sg15
(lp149
sg52
(lp150
sg13
(dp151
g55
I0
ssbtp152
a(V003
p153
g1
(g29
g3
Ntp154
Rp155
(dp156
g8
V003
p157
sg23
VVP_ISA_F008_S001_I003
p158
sg35
Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds.
p159
sg37
VUnprivileged ISA\u000aChapter 8.2
p160
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception
p161
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp162
sg15
(lp163
sg52
(lp164
sg13
(dp165
g55
I0
ssbtp166
asg99
(lp167
sg52
(lp168
sg13
(dp169
sbtp170
asVrfu_list_0
p171
(lp172
sg99
(lp173
sVvptool_gitrev
p174
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p175
sVio_fmt_gitrev
p176
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p177
sVconfig_gitrev
p178
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p179
sVymlcfg_gitrev
p180
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p181
sbtp182
.

179
cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml Normal file
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@ -0,0 +1,179 @@
!Feature
next_elt_id: 2
name: RV32A Load-Reserved/Store-Conditional Instructions
id: 8
display_order: 8
subfeatures: !!omap
- 000_LR.W: !Subfeature
name: 000_LR.W
tag: VP_IP008_P000
next_elt_id: 4
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F008_S000_I000
description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\
\ with the results loaded to rd.\nMisaligned address should cause an exception"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F008_S000_I001
description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\
\ with the results loaded to rd.\nMisaligned address should cause an exception"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F008_S000_I002
description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\
\ with the results loaded to rd.\nMisaligned address should cause an exception"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F008_S000_I003
description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\
\ with the results loaded to rd.\nMisaligned address should cause an exception"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\
\ cause exceptio"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 001_SC.W: !Subfeature
name: 001_SC.W
tag: VP_IP008_P001
next_elt_id: 4
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F008_S001_I000
description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\
\ occurs to address at rs1 with data from rs2.\nIf the reservation set\
\ from a previous LR.W fails, then rd is set to a non-zero value and the\
\ store does not occur.\nIf the reservation set passes, then rd is set to\
\ a zero-value and the store succeeds."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
All possible rd registers are used.\nAll possible register combinations\
\ where rs1 == rd are used\nAll possible register combinations where rs2\
\ == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F008_S001_I001
description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\
\ occurs to address at rs1 with data from rs2.\nIf the reservation set\
\ from a previous LR.W fails, then rd is set to a non-zero value and the\
\ store does not occur.\nIf the reservation set passes, then rd is set to\
\ a zero-value and the store succeeds."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\
\ rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F008_S001_I002
description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\
\ occurs to address at rs1 with data from rs2.\nIf the reservation set\
\ from a previous LR.W fails, then rd is set to a non-zero value and the\
\ store does not occur.\nIf the reservation set passes, then rd is set to\
\ a zero-value and the store succeeds."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd is either zero or non-zero to indicate\
\ success or failure, respectively"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F008_S001_I003
description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\
\ occurs to address at rs1 with data from rs2.\nIf the reservation set\
\ from a previous LR.W fails, then rd is set to a non-zero value and the\
\ store does not occur.\nIf the reservation set passes, then rd is set to\
\ a zero-value and the store succeeds."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\
\ cause exception"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

2059
cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck
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!Feature
next_elt_id: 9
name: RV32A Atomic Memory Operations
id: 9
display_order: 9
subfeatures: !!omap
- 000_AMOSWAP.W: !Subfeature
name: 000_AMOSWAP.W
tag: VP_IP009_P000
next_elt_id: 4
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F009_S000_I000
description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\
\ from the address at rs1 into rd.\nThe value at rs2 is then written back\
\ to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\
\ possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F009_S000_I001
description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\
\ from the address at rs1 into rd.\nThe value at rs2 is then written back\
\ to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\
\ rs2 are toggled\nZero and non-zero values of rs2 are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F009_S000_I002
description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\
\ from the address at rs1 into rd.\nThe value at rs2 is then written back\
\ to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: ''
verif_goals: "Output result: \n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F009_S000_I003
description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\
\ from the address at rs1 into rd.\nThe value at rs2 is then written back\
\ to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\
\ cause exception"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 001_AMOADD.W: !Subfeature
name: 001_AMOADD.W
tag: VP_IP009_P001
next_elt_id: 4
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F009_S001_I000
description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and added using signed arithmetic and the result iis then written back\
\ to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\
\ possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F009_S001_I001
description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and added using signed arithmetic and the result iis then written back\
\ to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\
\ rs2 are toggled\n+ve, -ve and zero values of rs2 are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F009_S001_I002
description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and added using signed arithmetic and the result iis then written back\
\ to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\
All bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F009_S001_I003
description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and added using signed arithmetic and the result iis then written back\
\ to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\
\ cause exception"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 002_AMOAND.W: !Subfeature
name: 002_AMOAND.W
tag: VP_IP009_P002
next_elt_id: 4
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F009_S002_I000
description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and bit-wise ANDed and the result iis then written back to the address\
\ at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\
\ possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F009_S002_I001
description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and bit-wise ANDed and the result iis then written back to the address\
\ at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\
\ rs2 are toggled\nZero and non-zero values of rs2 are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F009_S002_I002
description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and bit-wise ANDed and the result iis then written back to the address\
\ at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result: \n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F009_S002_I003
description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and bit-wise ANDed and the result iis then written back to the address\
\ at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\
\ cause exception"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 003_AMOOR.W: !Subfeature
name: 003_AMOOR.W
tag: VP_IP009_P003
next_elt_id: 4
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F009_S003_I000
description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\
\ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\
\ bit-wise ORed and the result iis then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\
\ possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F009_S003_I001
description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\
\ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\
\ bit-wise ORed and the result iis then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\
\ rs2 are toggled\nZero and non-zero values of rs2 are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F009_S003_I002
description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\
\ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\
\ bit-wise ORed and the result iis then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result: \n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F009_S003_I003
description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\
\ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\
\ bit-wise ORed and the result iis then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\
\ cause exception"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 004_AMOXOR.W: !Subfeature
name: 004_AMOXOR.W
tag: VP_IP009_P004
next_elt_id: 4
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F009_S004_I000
description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and bit-wise XORRed and the result iis then written back to the address\
\ at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\
\ possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F009_S004_I001
description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and bit-wise XORRed and the result iis then written back to the address\
\ at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\
\ rs2 are toggled\nZero and non-zero values of rs2 are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F009_S004_I002
description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and bit-wise XORRed and the result iis then written back to the address\
\ at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result: \n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F009_S004_I003
description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\
\ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\
\ and bit-wise XORRed and the result iis then written back to the address\
\ at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\
\ cause exception"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 005_AMOMAX.W: !Subfeature
name: 005_AMOMAX.W
tag: VP_IP009_P005
next_elt_id: 4
display_order: 5
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F009_S005_I000
description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming signed numbers and the largest value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\
\ possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F009_S005_I001
description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming signed numbers and the largest value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\
\ rs2 are toggled\n+ve, -ve and zero values of rs2 are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F009_S005_I002
description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming signed numbers and the largest value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\
All bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F009_S005_I003
description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming signed numbers and the largest value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\
\ cause exception"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 006_AMOMAXU.W: !Subfeature
name: 006_AMOMAXU.W
tag: VP_IP009_P006
next_elt_id: 4
display_order: 6
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F009_S006_I000
description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming unsigned numbers and the largest value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\
\ possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F009_S006_I001
description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming unsigned numbers and the largest value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\
\ rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F009_S006_I002
description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming unsigned numbers and the largest value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result: \n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F009_S006_I003
description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming unsigned numbers and the largest value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\
\ cause exception"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 007_AMOMIN.W: !Subfeature
name: 007_AMOMIN.W
tag: VP_IP009_P007
next_elt_id: 4
display_order: 7
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F009_S007_I000
description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming signed numbers and the smaller value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\
\ possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F009_S007_I001
description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming signed numbers and the smaller value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\
\ rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F009_S007_I002
description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming signed numbers and the smaller value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\
All bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F009_S007_I003
description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming signed numbers and the smaller value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\
\ cause exception"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 008_AMOMINU.W: !Subfeature
name: 008_AMOMINU.W
tag: VP_IP009_P008
next_elt_id: 4
display_order: 8
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F009_S008_I000
description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming unsigned numbers and the smaller value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\
\ possible rs2 registers are used.\nAll possible rd registers are used.\n\
All possible register combinations where rs1 == rd are used\nAll possible\
\ register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F009_S008_I001
description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming unsigned numbers and the smaller value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\
\ rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F009_S008_I002
description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming unsigned numbers and the smaller value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result: \n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '003': !VerifItem
name: '003'
tag: VP_ISA_RV32_F009_S008_I003
description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\
\ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\
\ rd and rs2 and compared assuming unsigned numbers and the smaller value\
\ is then written back to the address at (rs1)"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\
\ cause exception"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

2592
cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck
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!Feature
next_elt_id: 16
name: RV32C Integer Computational Instructions
id: 10
display_order: 10
subfeatures: !!omap
- 000_C.LI: !Subfeature
name: 000_C.LI
tag: VP_IP008_P000
next_elt_id: 2
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S000_I000
description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\
\ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of imm[5:0] are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S000_I001
description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\
\ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 001_C.LUI: !Subfeature
name: 001_C.LUI
tag: VP_IP008_P001
next_elt_id: 2
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S001_I000
description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\
\ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\
\ calculated using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of imm[17:12] are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S001_I001
description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\
\ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\
\ calculated using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd[31:12] are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 002_C.ADDI: !Subfeature
name: 002_C.ADDI
tag: VP_IP008_P002
next_elt_id: 3
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S002_I000
description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\
\ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\
\ overflow is lost and ignored.\nrd is calculated using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S002_I001
description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\
\ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\
\ overflow is lost and ignored.\nrd is calculated using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll inputs bits of rd before instruction\
\ execution are toggled\nAll bits of nzimm are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S002_I002
description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\
\ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\
\ overflow is lost and ignored.\nrd is calculated using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 003_C.ADDI16SP: !Subfeature
name: 003_C.ADDI16SP
tag: VP_IP008_P003
next_elt_id: 3
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S003_I000
description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\
\ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\
\ signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\n+ve and -ve values of nzimm are used\nAll\
\ bits of nzimm[9:4] are toggled\nAll bits of x2 before instruction execution\
\ are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S003_I001
description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\
\ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\
\ signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of x2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 004_C.ADDI4SPN: !Subfeature
name: 004_C.ADDI4SPN
tag: VP_IP008_P004
next_elt_id: 3
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S004_I000
description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\
Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\
\ using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd` registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S004_I001
description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\
Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\
\ using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of nzuimm[9:2] are toggled\nAll\
\ bits of x2 before instruction execution are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S004_I002
description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\
Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\
\ using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd` are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 005_C.SLLI: !Subfeature
name: 005_C.SLLI
tag: VP_IP008_P005
next_elt_id: 3
display_order: 5
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S005_I000
description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\
\ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S005_I001
description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\
\ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\
All bits of rd before instruction execution are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S005_I002
description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\
\ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 006_C.SRLI: !Subfeature
name: 006_C.SRLI
tag: VP_IP008_P006
next_elt_id: 3
display_order: 6
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S006_I000
description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\
\ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0,"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd` registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S006_I001
description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\
\ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0,"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\
All bits of rd before instruction execution are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S006_I002
description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\
\ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0,"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 007_C.SRAI: !Subfeature
name: 007_C.SRAI
tag: VP_IP008_P007
next_elt_id: 3
display_order: 7
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S007_I000
description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\
\ to srai rd', rd', uimm[5:0]."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd` registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S007_I001
description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\
\ to srai rd', rd', uimm[5:0]."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\
+ve, -ve and zero values of rd` are used\nAll bits of rd` before instruction\
\ execution are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S007_I002
description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\
\ to srai rd', rd', uimm[5:0]."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd` are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 008_C.ANDI: !Subfeature
name: 008_C.ANDI
tag: VP_IP008_P008
next_elt_id: 3
display_order: 8
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S008_I000
description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\
Expands to andi rd', rd', imm[5:0].\nimm treated as signed number"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd` registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S008_I001
description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\
Expands to andi rd', rd', imm[5:0].\nimm treated as signed number"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\
+ve, -ve and zero values of imm are used\nAll bits of rd` before instruction\
\ execution are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S008_I002
description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\
Expands to andi rd', rd', imm[5:0].\nimm treated as signed number"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd` are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 009_C.MV: !Subfeature
name: 009_C.MV
tag: VP_IP008_P009
next_elt_id: 3
display_order: 9
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S009_I000
description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\
\ when rs2=x0 or rd=x0."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd registers are used.\n\
All possible register combinations where rs2 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S009_I001
description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\
\ when rs2=x0 or rd=x0."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs2 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S009_I002
description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\
\ when rs2=x0 or rd=x0."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 010_C.ADD: !Subfeature
name: 010_C.ADD
tag: VP_IP008_P010
next_elt_id: 3
display_order: 10
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S010_I000
description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\
\ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S010_I001
description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\
\ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\n+ve,-ve and zero values of rs2 are used\n\
+ve,-ve, and zero values of rdrs1 are used\nAll bits of rs2 are toggled\n\
All bits of rd before instruction execution are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S010_I002
description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\
\ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd are toggled\n+ve,-ve and zero\
\ values of rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 011_C.AND: !Subfeature
name: 011_C.AND
tag: VP_IP008_P011
next_elt_id: 3
display_order: 11
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S011_I000
description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\
\ and rd', rd', rs2'."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd` registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S011_I001
description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\
\ and rd', rd', rs2'."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\
Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\
All bits of rd` before instruction execution are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S011_I002
description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\
\ and rd', rd', rs2'."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd` are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 012_C.OR: !Subfeature
name: 012_C.OR
tag: VP_IP008_P012
next_elt_id: 3
display_order: 12
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S012_I000
description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\
\ or rd', rd', rs2'."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd` registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S012_I001
description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\
\ or rd', rd', rs2'."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\
Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\
All bits of rd` before instruction execution are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S012_I002
description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\
\ or rd', rd', rs2'."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd` are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 013_C.XOR: !Subfeature
name: 013_C.XOR
tag: VP_IP008_P013
next_elt_id: 3
display_order: 13
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S013_I000
description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\
\ xor rd', rd', rs2'."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd` registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S013_I001
description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\
\ xor rd', rd', rs2'."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\
Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\
All bits of rd` before instruction execution are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S013_I002
description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\
\ xor rd', rd', rs2'."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd` are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 014_C.SUB: !Subfeature
name: 014_C.SUB
tag: VP_IP008_P014
next_elt_id: 3
display_order: 14
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S014_I000
description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\
\ sub rd', rd', rs2'. Arithmetic underflow is ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd` registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F010_S014_I001
description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\
\ sub rd', rd', rs2'. Arithmetic underflow is ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\n+ve,-ve and zero values of rs2` are used\n\
+ve, -ve, and zero values of rd` are used\nAll bits of rs2` are toggled\n\
All bits of rd` before instruction execution are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F010_S014_I002
description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\
\ sub rd', rd', rs2'. Arithmetic underflow is ignored"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of rd` are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 015_C.EBREAK: !Subfeature
name: 015_C.EBREAK
tag: VP_IP008_P015
next_elt_id: 1
display_order: 15
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F010_S015_I000
description: "c.ebreak\nRaiseException(Breakpoint)\nExpands to ebreak."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Instruction executed
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

920
cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck
View file

@ -1,920 +0,0 @@
(VRV32C Control Transfer Instructions
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I6
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I11
sVwid_order
p12
I11
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_C.J
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I1
sg8
g17
sVtag
p23
VVP_IP010_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F010_S000_I000
p34
sVdescription
p35
Vc.j imm[11:1]\u000apc += sext(imm)\u000apc is calculated using signed arithmetic\u000aExpands to jal x0, imm[11:1].
p36
sVpurpose
p37
VUnprivileged ISA\u000aChapter 16.4
p38
sVverif_goals
p39
VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
asVrfu_list_1
p57
(lp58
sg52
(lp59
sg13
(dp60
sbtp61
a(V001_C.JAL
p62
g1
(g18
g3
Ntp63
Rp64
(dp65
g22
I2
sg8
g62
sg23
VVP_IP010_P001
p66
sg25
(dp67
sg12
I1
sg15
(lp68
(V000
p69
g1
(g29
g3
Ntp70
Rp71
(dp72
g8
V000
p73
sg23
VVP_ISA_F010_S001_I000
p74
sg35
Vc.jal imm[11:1]\u000ax[1] = pc+2; pc += sext(imm)\u000apc is calculated using signed arithmetic.
p75
sg37
VUnprivileged ISA\u000aChapter 16.4
p76
sg39
VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled
p77
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp78
sg15
(lp79
sg52
(lp80
sg13
(dp81
g55
I0
ssbtp82
a(V001
p83
g1
(g29
g3
Ntp84
Rp85
(dp86
g8
V001
p87
sg23
VVP_ISA_F010_S001_I001
p88
sg35
Vc.jal imm[11:1]\u000ax[1] = pc+2; pc += sext(imm)\u000apc is calculated using signed arithmetic.
p89
sg37
VUnprivileged ISA\u000aChapter 16.4
p90
sg39
VOutput result:\u000a\u000aAll bits of x1 are toggled
p91
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp92
sg15
(lp93
sg52
(lp94
sg13
(dp95
g55
I0
ssbtp96
asg57
(lp97
sg52
(lp98
sg13
(dp99
sbtp100
a(V002_C.JR
p101
g1
(g18
g3
Ntp102
Rp103
(dp104
g22
I2
sg8
g101
sg23
VVP_IP010_P002
p105
sg25
(dp106
sg12
I2
sg15
(lp107
(V000
p108
g1
(g29
g3
Ntp109
Rp110
(dp111
g8
V000
p112
sg23
VVP_ISA_F010_S002_I000
p113
sg35
Vc.jr rs1\u000apc = x[rs1]\u000aExpands to jalr x0, 0(rs1). \u000aInvalid when rs1=x0.
p114
sg37
VUnprivileged ISA\u000aChapter 16.4
p115
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.
p116
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp117
sg15
(lp118
sg52
(lp119
sg13
(dp120
g55
I0
ssbtp121
a(V001
p122
g1
(g29
g3
Ntp123
Rp124
(dp125
g8
V001
p126
sg23
VVP_ISA_F010_S002_I001
p127
sg35
Vc.jr rs1\u000apc = x[rs1]\u000aExpands to jalr x0, 0(rs1). \u000aInvalid when rs1=x0.
p128
sg37
VUnprivileged ISA\u000aChapter 16.4
p129
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled
p130
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp131
sg15
(lp132
sg52
(lp133
sg13
(dp134
g55
I0
ssbtp135
asg57
(lp136
sg52
(lp137
sg13
(dp138
sbtp139
a(V003_C.JALR
p140
g1
(g18
g3
Ntp141
Rp142
(dp143
g22
I3
sg8
g140
sg23
VVP_IP010_P003
p144
sg25
(dp145
sg12
I3
sg15
(lp146
(V000
p147
g1
(g29
g3
Ntp148
Rp149
(dp150
g8
V000
p151
sg23
VVP_ISA_F010_S003_I000
p152
sg35
Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0.
p153
sg37
VUnprivileged ISA\u000aChapter 16.4
p154
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.
p155
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp156
sg15
(lp157
sg52
(lp158
sg13
(dp159
g55
I0
ssbtp160
a(V001
p161
g1
(g29
g3
Ntp162
Rp163
(dp164
g8
V001
p165
sg23
VVP_ISA_F010_S003_I001
p166
sg35
Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0.
p167
sg37
VUnprivileged ISA\u000aChapter 16.4
p168
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled
p169
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp170
sg15
(lp171
sg52
(lp172
sg13
(dp173
g55
I0
ssbtp174
a(V002
p175
g1
(g29
g3
Ntp176
Rp177
(dp178
g8
V002
p179
sg23
VVP_ISA_F010_S003_I002
p180
sg35
Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0.
p181
sg37
VUnprivileged ISA\u000aChapter 16.4
p182
sg39
VOutput result:\u000a\u000aAll bits of x1 are toggled
p183
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp184
sg15
(lp185
sg52
(lp186
sg13
(dp187
g55
I0
ssbtp188
asg57
(lp189
sg52
(lp190
sg13
(dp191
sbtp192
a(V004_C.BEQZ
p193
g1
(g18
g3
Ntp194
Rp195
(dp196
g22
I3
sg8
g193
sg23
VVP_IP010_P004
p197
sg25
(dp198
sg12
I4
sg15
(lp199
(V000
p200
g1
(g29
g3
Ntp201
Rp202
(dp203
g8
V000
p204
sg23
VVP_ISA_F010_S004_I000
p205
sg35
Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic.
p206
sg37
VUnprivileged ISA\u000aChapter 16.4
p207
sg39
VRegister operands:\u000a\u000aAll possible rs1` registers are used.
p208
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp209
sg15
(lp210
sg52
(lp211
sg13
(dp212
g55
I0
ssbtp213
a(V001
p214
g1
(g29
g3
Ntp215
Rp216
(dp217
g8
V001
p218
sg23
VVP_ISA_F010_S004_I001
p219
sg35
Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic.
p220
sg37
VUnprivileged ISA\u000aChapter 16.4
p221
sg39
VInput operands:\u000a\u000aAll bits of rs1` are toggled
p222
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp223
sg15
(lp224
sg52
(lp225
sg13
(dp226
g55
I0
ssbtp227
a(V002
p228
g1
(g29
g3
Ntp229
Rp230
(dp231
g8
V002
p232
sg23
VVP_ISA_F010_S004_I002
p233
sg35
Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic.
p234
sg37
VUnprivileged ISA\u000aChapter 16.4
p235
sg39
VOutput result:\u000a\u000aBranch taken or not-taken
p236
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp237
sg15
(lp238
sg52
(lp239
sg13
(dp240
g55
I0
ssbtp241
asg57
(lp242
sg52
(lp243
sg13
(dp244
sbtp245
a(V005_C.BNEZ
p246
g1
(g18
g3
Ntp247
Rp248
(dp249
g22
I3
sg8
g246
sg23
VVP_IP010_P005
p250
sg25
(dp251
sg12
I5
sg15
(lp252
(V000
p253
g1
(g29
g3
Ntp254
Rp255
(dp256
g8
V000
p257
sg23
VVP_ISA_F010_S005_I000
p258
sg35
Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic.
p259
sg37
VUnprivileged ISA\u000aChapter 16.4
p260
sg39
VRegister operands:\u000a\u000aAll possible rs1` registers are used.
p261
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp262
sg15
(lp263
sg52
(lp264
sg13
(dp265
g55
I0
ssbtp266
a(V001
p267
g1
(g29
g3
Ntp268
Rp269
(dp270
g8
V001
p271
sg23
VVP_ISA_F010_S005_I001
p272
sg35
Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic.
p273
sg37
VUnprivileged ISA\u000aChapter 16.4
p274
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled
p275
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp276
sg15
(lp277
sg52
(lp278
sg13
(dp279
g55
I0
ssbtp280
a(V002
p281
g1
(g29
g3
Ntp282
Rp283
(dp284
g8
V002
p285
sg23
VVP_ISA_F010_S005_I002
p286
sg35
Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic.
p287
sg37
VUnprivileged ISA\u000aChapter 16.4
p288
sg39
VOutput result:\u000a\u000aBranch taken or not-taken
p289
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp290
sg15
(lp291
sg52
(lp292
sg13
(dp293
g55
I0
ssbtp294
asg57
(lp295
sg52
(lp296
sg13
(dp297
sbtp298
asVrfu_list_0
p299
(lp300
sg57
(lp301
sVvptool_gitrev
p302
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p303
sVio_fmt_gitrev
p304
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p305
sVconfig_gitrev
p306
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p307
sVymlcfg_gitrev
p308
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p309
sbtp310
.

286
cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml Normal file
View file

@ -0,0 +1,286 @@
!Feature
next_elt_id: 6
name: RV32C Control Transfer Instructions
id: 11
display_order: 11
subfeatures: !!omap
- 000_C.J: !Subfeature
name: 000_C.J
tag: VP_IP010_P000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F011_S000_I000
description: "c.j imm[11:1]\npc += sext(imm)\npc is calculated using signed\
\ arithmetic\nExpands to jal x0, imm[11:1]."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\
\ of uimm are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 001_C.JAL: !Subfeature
name: 001_C.JAL
tag: VP_IP010_P001
next_elt_id: 2
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F011_S001_I000
description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\
\ using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\
\ of uimm are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F011_S001_I001
description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\
\ using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of x1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 002_C.JR: !Subfeature
name: 002_C.JR
tag: VP_IP010_P002
next_elt_id: 2
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F011_S002_I000
description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\
\ when rs1=x0."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F011_S002_I001
description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\
\ when rs1=x0."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 003_C.JALR: !Subfeature
name: 003_C.JALR
tag: VP_IP010_P003
next_elt_id: 3
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F011_S003_I000
description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\
\ x1, 0(rs1). \nInvalid when rs1=x0."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F011_S003_I001
description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\
\ x1, 0(rs1). \nInvalid when rs1=x0."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F011_S003_I002
description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\
\ x1, 0(rs1). \nInvalid when rs1=x0."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nAll bits of x1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 004_C.BEQZ: !Subfeature
name: 004_C.BEQZ
tag: VP_IP010_P004
next_elt_id: 3
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F011_S004_I000
description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\
Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1` registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F011_S004_I001
description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\
Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1` are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F011_S004_I002
description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\
Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nBranch taken or not-taken"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 005_C.BNEZ: !Subfeature
name: 005_C.BNEZ
tag: VP_IP010_P005
next_elt_id: 3
display_order: 5
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F011_S005_I000
description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\
Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1` registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F011_S005_I001
description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\
Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nAll bits of rs1 are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F011_S005_I002
description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\
Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nBranch taken or not-taken"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

672
cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck
View file

@ -1,672 +0,0 @@
(VRV32C Load and Store Instructions
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I4
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I12
sVwid_order
p12
I12
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_C.LWSP
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I3
sg8
g17
sVtag
p23
VVP_IP009_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F009_S000_I000
p34
sVdescription
p35
Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number
p36
sVpurpose
p37
VUnprivileged ISA\u000aChapter 16.3
p38
sVverif_goals
p39
VRegister operands:\u000a\u000aAll possible rd registers are used.
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
a(V001
p57
g1
(g29
g3
Ntp58
Rp59
(dp60
g8
V001
p61
sg23
VVP_ISA_F009_S000_I001
p62
sg35
Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number
p63
sg37
VUnprivileged ISA\u000aChapter 16.3
p64
sg39
VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled
p65
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp66
sg15
(lp67
sg52
(lp68
sg13
(dp69
g55
I0
ssbtp70
a(V002
p71
g1
(g29
g3
Ntp72
Rp73
(dp74
g8
V002
p75
sg23
VVP_ISA_F009_S000_I002
p76
sg35
Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number
p77
sg37
VUnprivileged ISA\u000aChapter 16.3
p78
sg39
VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled
p79
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp80
sg15
(lp81
sg52
(lp82
sg13
(dp83
g55
I0
ssbtp84
asVrfu_list_1
p85
(lp86
sg52
(lp87
sg13
(dp88
sbtp89
a(V001_C.SWSP
p90
g1
(g18
g3
Ntp91
Rp92
(dp93
g22
I2
sg8
g90
sg23
VVP_IP009_P001
p94
sg25
(dp95
sg12
I1
sg15
(lp96
(V000
p97
g1
(g29
g3
Ntp98
Rp99
(dp100
g8
V000
p101
sg23
VVP_ISA_F009_S001_I000
p102
sg35
Vc.swsp rs2, uimm(x2)\u000aM[x[2] + uimm][0:31] = x[rs2]\u000aExpands to sw rs2, uimm[7:2](x2).\u000auimm treated as unsigned number
p103
sg37
VUnprivileged ISA\u000aChapter 16.3
p104
sg39
VRegister operands:\u000a\u000aAll possible rs2 registers are used.
p105
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp106
sg15
(lp107
sg52
(lp108
sg13
(dp109
g55
I0
ssbtp110
a(V001
p111
g1
(g29
g3
Ntp112
Rp113
(dp114
g8
V001
p115
sg23
VVP_ISA_F009_S001_I001
p116
sg35
Vc.swsp rs2, uimm(x2)\u000aM[x[2] + uimm][0:31] = x[rs2]\u000aExpands to sw rs2, uimm[7:2](x2).\u000auimm treated as unsigned number
p117
sg37
VUnprivileged ISA\u000aChapter 16.3
p118
sg39
VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled
p119
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp120
sg15
(lp121
sg52
(lp122
sg13
(dp123
g55
I0
ssbtp124
asg85
(lp125
sg52
(lp126
sg13
(dp127
sbtp128
a(V002_C.LW
p129
g1
(g18
g3
Ntp130
Rp131
(dp132
g22
I3
sg8
g129
sg23
VVP_IP009_P002
p133
sg25
(dp134
sg12
I2
sg15
(lp135
(V000
p136
g1
(g29
g3
Ntp137
Rp138
(dp139
g8
V000
p140
sg23
VVP_ISA_F009_S002_I000
p141
sg35
Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1')
p142
sg37
VUnprivileged ISA\u000aChapter 16.3
p143
sg39
VRegister operands:\u000a\u000aAll possible rs1` registers are used.\u000aAll possible rd` registers are used.\u000aAll possible register combinations where rs1` == rd` are used
p144
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp145
sg15
(lp146
sg52
(lp147
sg13
(dp148
g55
I0
ssbtp149
a(V001
p150
g1
(g29
g3
Ntp151
Rp152
(dp153
g8
V001
p154
sg23
VVP_ISA_F009_S002_I001
p155
sg35
Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1')
p156
sg37
VUnprivileged ISA\u000aChapter 16.3
p157
sg39
VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled\u000aAll bits of rs1` are toggled
p158
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp159
sg15
(lp160
sg52
(lp161
sg13
(dp162
g55
I0
ssbtp163
a(V002
p164
g1
(g29
g3
Ntp165
Rp166
(dp167
g8
V002
p168
sg23
VVP_ISA_F009_S002_I002
p169
sg35
Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1')
p170
sg37
VUnprivileged ISA\u000aChapter 16.3
p171
sg39
VOutput result:\u000a\u000ard` value is non-zero and zero\u000aAll bits of rd are toggled
p172
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp173
sg15
(lp174
sg52
(lp175
sg13
(dp176
g55
I0
ssbtp177
asg85
(lp178
sg52
(lp179
sg13
(dp180
sbtp181
a(V003_C.SW
p182
g1
(g18
g3
Ntp183
Rp184
(dp185
g22
I2
sg8
g182
sg23
VVP_IP009_P003
p186
sg25
(dp187
sg12
I3
sg15
(lp188
(V000
p189
g1
(g29
g3
Ntp190
Rp191
(dp192
g8
V000
p193
sg23
VVP_ISA_F009_S003_I000
p194
sg35
Vc.sw rs2', uimm(rs1')\u000aM[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1'\u000aExpands to sw rs2', uimm[6:2](rs1').
p195
sg37
VUnprivileged ISA\u000aChapter 16.3
p196
sg39
VRegister operands:\u000a\u000aAll possible rs1` registers are used.\u000aAll possible rd` registers are used.\u000aAll possible register combinations where rs1` == rd` are used
p197
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp198
sg15
(lp199
sg52
(lp200
sg13
(dp201
g55
I0
ssbtp202
a(V001
p203
g1
(g29
g3
Ntp204
Rp205
(dp206
g8
V001
p207
sg23
VVP_ISA_F009_S003_I001
p208
sg35
Vc.sw rs2', uimm(rs1')\u000aM[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1'\u000aExpands to sw rs2', uimm[6:2](rs1').
p209
sg37
VUnprivileged ISA\u000aChapter 16.3
p210
sg39
VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled\u000aAll bits of rs1` are toggled\u000aAll bits of rs2` are toggled
p211
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp212
sg15
(lp213
sg52
(lp214
sg13
(dp215
g55
I0
ssbtp216
asg85
(lp217
sg52
(lp218
sg13
(dp219
sbtp220
asVrfu_list_0
p221
(lp222
sg85
(lp223
sVvptool_gitrev
p224
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p225
sVio_fmt_gitrev
p226
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p227
sVconfig_gitrev
p228
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p229
sVymlcfg_gitrev
p230
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p231
sbtp232
.

218
cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml Normal file
View file

@ -0,0 +1,218 @@
!Feature
next_elt_id: 4
name: RV32C Load and Store Instructions
id: 12
display_order: 12
subfeatures: !!omap
- 000_C.LWSP: !Subfeature
name: 000_C.LWSP
tag: VP_IP009_P000
next_elt_id: 3
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F012_S000_I000
description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\
\ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\
\ number"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F012_S000_I001
description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\
\ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\
\ number"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\
\ of uimm are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F012_S000_I002
description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\
\ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\
\ number"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 001_C.SWSP: !Subfeature
name: 001_C.SWSP
tag: VP_IP009_P001
next_elt_id: 2
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F012_S001_I000
description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\
\ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs2 registers are used."
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F012_S001_I001
description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\
\ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\
\ of uimm are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 002_C.LW: !Subfeature
name: 002_C.LW
tag: VP_IP009_P002
next_elt_id: 3
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F012_S002_I000
description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\
\ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1` registers are used.\n\
All possible rd` registers are used.\nAll possible register combinations\
\ where rs1` == rd` are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F012_S002_I001
description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\
\ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\
\ of uimm are toggled\nAll bits of rs1` are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_ISA_RV32_F012_S002_I002
description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\
\ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Output result:\n\nrd` value is non-zero and zero\nAll bits of\
\ rd are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 003_C.SW: !Subfeature
name: 003_C.SW
tag: VP_IP009_P003
next_elt_id: 2
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F012_S003_I000
description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\
\ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1` registers are used.\n\
All possible rd` registers are used.\nAll possible register combinations\
\ where rs1` == rd` are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F012_S003_I001
description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\
\ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\
\ of uimm are toggled\nAll bits of rs1` are toggled\nAll bits of rs2` are\
\ toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

824
cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck
View file

@ -1,824 +0,0 @@
(VRV32Zicsr Control and Status Register (CSR) Instructions
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I6
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I13
sVwid_order
p12
I13
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_CSRRW
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I2
sg8
g17
sVtag
p23
VVP_IP007_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F007_S000_I000
p34
sVdescription
p35
Vcsrrw rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1]
p36
sVpurpose
p37
VISA Chapter 9
p38
sVverif_goals
p39
VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
a(V001
p57
g1
(g29
g3
Ntp58
Rp59
(dp60
g8
V001
p61
sg23
VVP_ISA_F007_S000_I001
p62
sg35
Vcsrrw rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1]
p63
sg37
VISA Chapter 9
p64
sg39
VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0)
p65
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp66
sg15
(lp67
sg52
(lp68
sg13
(dp69
g55
I0
ssbtp70
asVrfu_list_1
p71
(lp72
sg52
(lp73
sg13
(dp74
sbtp75
a(V001_CSRRS
p76
g1
(g18
g3
Ntp77
Rp78
(dp79
g22
I2
sg8
g76
sg23
VVP_IP007_P001
p80
sg25
(dp81
sg12
I1
sg15
(lp82
(V000
p83
g1
(g29
g3
Ntp84
Rp85
(dp86
g8
V000
p87
sg23
VVP_ISA_F007_S001_I000
p88
sg35
Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] | csr\u000aNote that not all bits of csr will be writable.
p89
sg37
VISA Chapter 9
p90
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used
p91
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp92
sg15
(lp93
sg52
(lp94
sg13
(dp95
g55
I0
ssbtp96
a(V001
p97
g1
(g29
g3
Ntp98
Rp99
(dp100
g8
V001
p101
sg23
VVP_ISA_F007_S001_I001
p102
sg35
Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] | csr\u000aNote that not all bits of csr will be writable.
p103
sg37
VISA Chapter 9
p104
sg39
VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0)
p105
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp106
sg15
(lp107
sg52
(lp108
sg13
(dp109
g55
I0
ssbtp110
asg71
(lp111
sg52
(lp112
sg13
(dp113
sbtp114
a(V002_CSRRC
p115
g1
(g18
g3
Ntp116
Rp117
(dp118
g22
I2
sg8
g115
sg23
VVP_IP007_P002
p119
sg25
(dp120
sg12
I2
sg15
(lp121
(V000
p122
g1
(g29
g3
Ntp123
Rp124
(dp125
g8
V000
p126
sg23
VVP_ISA_F007_S002_I000
p127
sg35
Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = ~[rs1] | csr\u000aNote that not all bits of csr will be writable.
p128
sg37
VISA Chapter 9
p129
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used
p130
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp131
sg15
(lp132
sg52
(lp133
sg13
(dp134
g55
I0
ssbtp135
a(V001
p136
g1
(g29
g3
Ntp137
Rp138
(dp139
g8
V001
p140
sg23
VVP_ISA_F007_S002_I001
p141
sg35
Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = ~[rs1] | csr\u000aNote that not all bits of csr will be writable.
p142
sg37
VISA Chapter 9
p143
sg39
VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0)
p144
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp145
sg15
(lp146
sg52
(lp147
sg13
(dp148
g55
I0
ssbtp149
asg71
(lp150
sg52
(lp151
sg13
(dp152
sbtp153
a(V003_CSRRWI
p154
g1
(g18
g3
Ntp155
Rp156
(dp157
g22
I2
sg8
g154
sg23
VVP_IP007_P003
p158
sg25
(dp159
sg12
I3
sg15
(lp160
(V000
p161
g1
(g29
g3
Ntp162
Rp163
(dp164
g8
V000
p165
sg23
VVP_ISA_F007_S003_I000
p166
sg35
Vcsrrwi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0])\u000aIf rd == x0 then CSR is not read.
p167
sg37
VISA Chapter 9
p168
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used
p169
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp170
sg15
(lp171
sg52
(lp172
sg13
(dp173
g55
I0
ssbtp174
a(V001
p175
g1
(g29
g3
Ntp176
Rp177
(dp178
g8
V001
p179
sg23
VVP_ISA_F007_S003_I001
p180
sg35
Vcsrrwi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0])\u000aIf rd == x0 then CSR is not read.
p181
sg37
VISA Chapter 9
p182
sg39
VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled
p183
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp184
sg15
(lp185
sg52
(lp186
sg13
(dp187
g55
I0
ssbtp188
asg71
(lp189
sg52
(lp190
sg13
(dp191
sbtp192
a(V004_CSRRSI
p193
g1
(g18
g3
Ntp194
Rp195
(dp196
g22
I2
sg8
g193
sg23
VVP_IP007_P004
p197
sg25
(dp198
sg12
I4
sg15
(lp199
(V000
p200
g1
(g29
g3
Ntp201
Rp202
(dp203
g8
V000
p204
sg23
VVP_ISA_F007_S004_I000
p205
sg35
Vcsrrsi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0]) | csr\u000aNote that not all bits of csr will be writable.
p206
sg37
VISA Chapter 9
p207
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used
p208
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp209
sg15
(lp210
sg52
(lp211
sg13
(dp212
g55
I0
ssbtp213
a(V001
p214
g1
(g29
g3
Ntp215
Rp216
(dp217
g8
V001
p218
sg23
VVP_ISA_F007_S004_I001
p219
sg35
Vcsrrsi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0]) | csr\u000aNote that not all bits of csr will be writable.
p220
sg37
VISA Chapter 9
p221
sg39
VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled
p222
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp223
sg15
(lp224
sg52
(lp225
sg13
(dp226
g55
I0
ssbtp227
asg71
(lp228
sg52
(lp229
sg13
(dp230
sbtp231
a(V005_CSRRCI
p232
g1
(g18
g3
Ntp233
Rp234
(dp235
g22
I2
sg8
g232
sg23
VVP_IP007_P005
p236
sg25
(dp237
sg12
I5
sg15
(lp238
(V000
p239
g1
(g29
g3
Ntp240
Rp241
(dp242
g8
V000
p243
sg23
VVP_ISA_F007_S005_I000
p244
sg35
Vcsrrs rd, imm[4:0], csr\u000ard = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr\u000aNote that not all bits of csr will be writable.
p245
sg37
VISA Chapter 9
p246
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used
p247
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp248
sg15
(lp249
sg52
(lp250
sg13
(dp251
g55
I0
ssbtp252
a(V001
p253
g1
(g29
g3
Ntp254
Rp255
(dp256
g8
V001
p257
sg23
VVP_ISA_F007_S005_I001
p258
sg35
Vcsrrs rd, imm[4:0], csr\u000ard = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr\u000aNote that not all bits of csr will be writable.
p259
sg37
VISA Chapter 9
p260
sg39
VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled
p261
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp262
sg15
(lp263
sg52
(lp264
sg13
(dp265
g55
I0
ssbtp266
asg71
(lp267
sg52
(lp268
sg13
(dp269
sbtp270
asVrfu_list_0
p271
(lp272
sg71
(lp273
sVvptool_gitrev
p274
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p275
sVio_fmt_gitrev
p276
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p277
sVconfig_gitrev
p278
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p279
sVymlcfg_gitrev
p280
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p281
sbtp282
.

263
cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml Normal file
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@ -0,0 +1,263 @@
!Feature
next_elt_id: 6
name: RV32Zicsr Control and Status Register (CSR) Instructions
id: 13
display_order: 13
subfeatures: !!omap
- 000_CSRRW: !Subfeature
name: 000_CSRRW
tag: VP_IP007_P000
next_elt_id: 2
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F013_S000_I000
description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\
All possible rd registers are used\nAll supported CSRs are used\nAll possible\
\ register combinations where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F013_S000_I001
description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\
\ rs1 != x0)"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 001_CSRRS: !Subfeature
name: 001_CSRRS
tag: VP_IP007_P001
next_elt_id: 2
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F013_S001_I000
description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\
\ that not all bits of csr will be writable."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\
All possible rd registers are used\nAll supported CSRs are used\nAll possible\
\ register combinations where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F013_S001_I001
description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\
\ that not all bits of csr will be writable."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\
\ rs1 != x0)"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 002_CSRRC: !Subfeature
name: 002_CSRRC
tag: VP_IP007_P002
next_elt_id: 2
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F013_S002_I000
description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\
\ that not all bits of csr will be writable."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\
All possible rd registers are used\nAll supported CSRs are used\nAll possible\
\ register combinations where rs1 == rd are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F013_S002_I001
description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\
\ that not all bits of csr will be writable."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\
\ rs1 != x0)"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 003_CSRRWI: !Subfeature
name: 003_CSRRWI
tag: VP_IP007_P003
next_elt_id: 2
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F013_S003_I000
description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\
If rd == x0 then CSR is not read."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\
\ supported CSRs are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F013_S003_I001
description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\
If rd == x0 then CSR is not read."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\
All bits of imm[4:0] are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 004_CSRRSI: !Subfeature
name: 004_CSRRSI
tag: VP_IP007_P004
next_elt_id: 2
display_order: 4
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F013_S004_I000
description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\
\ | csr\nNote that not all bits of csr will be writable."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\
\ supported CSRs are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F013_S004_I001
description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\
\ | csr\nNote that not all bits of csr will be writable."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\
All bits of imm[4:0] are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 005_CSRRCI: !Subfeature
name: 005_CSRRCI
tag: VP_IP007_P005
next_elt_id: 2
display_order: 5
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F013_S005_I000
description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\
\ | csr\nNote that not all bits of csr will be writable."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\
\ supported CSRs are used"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F013_S005_I001
description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\
\ | csr\nNote that not all bits of csr will be writable."
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\
All bits of imm[4:0] are toggled"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

157
cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck
View file

@ -1,157 +0,0 @@
(VRV32Zifencei Instruction-Fetch Fence
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I1
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I14
sVwid_order
p12
I14
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_FENCE.I
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I1
sg8
g17
sVtag
p23
VVP_IP006_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F006_S000_I000
p34
sVdescription
p35
VFence.I instruction executed\u000aImplementation is core-specific
p36
sVpurpose
p37
VUnprivileged ISA\u000aChapter 3
p38
sVverif_goals
p39
VFence.I instruction is executed
p40
sVcoverage_loc
p41
Visacov.rv32zifencei_fence_i_cg
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
V
p48
sVstatus
p49
g48
sVsimu_target_list
p50
(lp51
sg15
(lp52
sVrfu_list_2
p53
(lp54
sg13
(dp55
Vlock_status
p56
I0
ssbtp57
asVrfu_list_1
p58
(lp59
sg53
(lp60
sg13
(dp61
sbtp62
asVrfu_list_0
p63
(lp64
sg58
(lp65
sVvptool_gitrev
p66
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p67
sVio_fmt_gitrev
p68
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p69
sVconfig_gitrev
p70
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p71
sVymlcfg_gitrev
p72
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p73
sbtp74
.

32
cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml Normal file
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@ -0,0 +1,32 @@
!Feature
next_elt_id: 1
name: RV32Zifencei Instruction-Fetch Fence
id: 14
display_order: 14
subfeatures: !!omap
- 000_FENCE.I: !Subfeature
name: 000_FENCE.I
tag: VP_IP006_P000
next_elt_id: 1
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F014_S000_I000
description: "Fence.I instruction executed\nImplementation is core-specific"
reqt_doc: ./RISCV_Instructions.rst
ref_mode: ''
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Fence.I instruction is executed
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: isacov.rv32zifencei_fence_i_cg
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

154
cva6/docs/VerifPlans/ISA_RV32/VP_IP015.yml Normal file
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!Feature
next_elt_id: 4
name: Instruction execution sequences
id: 15
display_order: 15
subfeatures: !!omap
- 000_Instruction Execution: !Subfeature
name: 000_Instruction Execution
tag: VP_ISA_RV32_F015_S000
next_elt_id: 3
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F015_S000_I000
description: All suported instructions for the core are executed
reqt_doc: ./RISCV_Instructions.rst
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Instruction is executed
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F015_S000_I001
description: All suported instructions for the core are executed
reqt_doc: ./RISCV_Instructions.rst
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: All back-to-back supported instruction sequences are executed
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 001_Instruction Group Execution: !Subfeature
name: 001_Instruction Group Execution
tag: VP_ISA_RV32_F015_S001
next_elt_id: 2
display_order: 1
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F015_S001_I000
description: All defined instruction groups for a core are executed
reqt_doc: ./RISCV_Instructions.rst
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: For the core under test, all instruction groups are executed
in the core
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F015_S001_I001
description: All defined instruction groups are executed in sequence
reqt_doc: ./RISCV_Instructions.rst
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Depending on the length of the pipeline in the processor, sequence
chains of 2,3,or 4 instruction groups are checked for execution
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 002_GPR Hazard: !Subfeature
name: 002_GPR Hazard
tag: VP_ISA_RV32_F015_S002
next_elt_id: 1
display_order: 2
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F015_S002_I000
description: An instruction reads from register that was written to in the
previous instruction
reqt_doc: ./RISCV_Instructions.rst
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: All instruction groups are tested across GPR hazards
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- 003_CSR Hazard: !Subfeature
name: 003_CSR Hazard
tag: VP_ISA_RV32_F015_S003
next_elt_id: 2
display_order: 3
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_ISA_RV32_F015_S003_I000
description: CSR writes from the program are executed in conjunction with
all instruction groups
reqt_doc: ./RISCV_Instructions.rst
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: "CSR write instruction attempts to write to a supported CSR\n\
This does not include csr set or clear instructions where rs1 is x0 (bypassing\
\ the write)"
pfc: 3
test_type: 3
cov_method: 1
cores: 56
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_ISA_RV32_F015_S003_I001
description: CSR writes from the program are executed in conjunction with
all instruction groups
reqt_doc: ./RISCV_Instructions.rst
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: Each instruction group is executed after each supported CSR is
written with a Zicsri write instructio
pfc: -1
test_type: -1
cov_method: -1
cores: 56
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

6
cva6/docs/VerifPlans/ISA_RV32/runme.sh
View file

@ -17,11 +17,11 @@ export PLATFORM_TOP_DIR="$ROOTDIR"
# Set the printable name for the project that will be used
# in the human-readable documentation.
export PROJECT_NAME="ISA"
export PROJECT_NAME="ISA RISC-V 32b"
# Set the alphanumerical identifier of the project that
# will be used to construct file names etc.
export PROJECT_IDENT="ISA"
export PROJECT_IDENT="ISA_RV32"
# Set the destination directory of Markdown files for this project.
# Since it will be used by VPTOOL, it shall NOT be a relative path.
@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"`
# FIXME: Introduce a suitably named shell variable that points to the root
# directory of the tool set (TOOL_TOP etc.)
# FORNOW use a hardcoded relative path.
python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py -t winxpblue
sh $ROOTDIR/../../../../tools/vptool/vptool.sh $*

71
cva6/docs/VerifPlans/csr_access/VP_IP000.yml Normal file
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@ -0,0 +1,71 @@
!Feature
next_elt_id: 1
name: machineScratch(MSCRATCH)
id: 0
display_order: 0
subfeatures: !!omap
- 000_MSCRATCH: !Subfeature
name: 000_MSCRATCH
tag: VP_csr-test-ident_F000_S000
next_elt_id: 3
display_order: 0
items: !!omap
- '000': !VerifItem
name: '000'
tag: VP_csr-test-ident_F000_S000_I000
description: "To verify the Power-on Reset value for MSCRATCH CSR.\n \nAddress\
\ Offset : 0x340\nWidth (bits) : 32\nAccess Type : RW\nReset Value : 0x00000000\n\
priviliged mode : Machine"
reqt_doc: riscv-privileged-20211203
ref_mode: section
ref_page: ''
ref_section: 3.1.13
ref_viewer: firefox
verif_goals: Read MSCRATCH CSR to check default POR value that should be equal
to 0x00000000.
pfc: 3
test_type: 1
cov_method: 10
cores: 8
coverage_loc: ''
comments: ''
- '001': !VerifItem
name: '001'
tag: VP_csr-test-ident_F000_S000_I001
description: Verifying R/W access of a MSCRATCH CSR by writing random valid
data like 0xFFFFFFFF, 0XA5A5A5A5, 0X5A5A5A5A ... and Read back CSR values
to check correctness.
reqt_doc: riscv-privileged-20211203
ref_mode: section
ref_page: ''
ref_section: 3.1.13
ref_viewer: firefox
verif_goals: The read values of MSCRATCH CSR should matches with written random
data values.
pfc: -1
test_type: -1
cov_method: -1
cores: 8
coverage_loc: ''
comments: ''
- '002': !VerifItem
name: '002'
tag: VP_csr-test-ident_F000_S000_I002
description: Verifying MSCRATCH CSR in other privilige modes(supervisor, user)
reqt_doc: ''
ref_mode: page
ref_page: ''
ref_section: ''
ref_viewer: firefox
verif_goals: It is expected that accessing Machine Mode CSRs in lower privilige
modes will raise an exception.
pfc: 3
test_type: 1
cov_method: 10
cores: 8
coverage_loc: ''
comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'

2653
cva6/docs/VerifPlans/csr_access/cva6_csr.rst Normal file
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File diff suppressed because it is too large Load diff

34
cva6/docs/VerifPlans/csr_access/runme.sh Normal file
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@ -0,0 +1,34 @@
#############################################################################
# Copyright (C) 2022 Thales DIS France SAS
#
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0.
#
# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com)
#############################################################################
#!/bin/sh
# Location of project-specific directories
ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")`
# Set up platform location. It can be anywhere but should contain
# a valid `vp_config.py` file in `vptool` directory.
# Here we use the verification tree from the example directory.
export PLATFORM_TOP_DIR="$ROOTDIR"
# Set the printable name for the project that will be used
# in the human-readable documentation.
export PROJECT_NAME="CSR ACCESS VERIFICATION"
# Set the alphanumerical identifier of the project that
# will be used to construct file names etc.
export PROJECT_IDENT="csr-access"
# Set the destination directory of Markdown files for this project.
# Since it will be used by VPTOOL, it shall NOT be a relative path.
export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"`
# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'.
# FIXME: Introduce a suitably named shell variable that points to the root
# directory of the tool set (TOOL_TOP etc.)
# FORNOW use a hardcoded relative path.
sh $ROOTDIR/../../../../tools/vptool/vptool.sh $*

18
cva6/docs/VerifPlans/install-prerequisites.sh
View file

@ -9,19 +9,29 @@
#############################################################################
# Make sure all necessary components are installed/available.
#
# Install Python dependencies.
for REQT in `cat requirements.txt` ; do
python3 -m pip install $REQT
done
# Install Python dependencies. We can extract the full path of the script only
# when invoked using '$SHELL <script>' syntax. With "source" and "dot" invocation
# methods (basename of $0 equal to $SHELL), the script must be run from the
# directory containing 'requirements.txt'.
[ $(basename $SHELL) = $0 ] && { \
echo "Please run this script from the directory in which it is located,"
echo "or use the syntax '"$0 path-to-script"'"
return 1
}
python3 -m pip install -q -r $(dirname $(readlink -f $0))/requirements.txt
# Check for a LaTeX installation.
which latex > /dev/null || { \
echo "*** LaTeX ecosystem missing on you machine!"
echo "*** Please install a LaTeX distribution if you intend to produce DV plans in PDF and/or ePub formats."
return 1
}
# Check for latexmk which is required for printable output.
which latexmk > /dev/null || { \
echo "*** LaTeX wrapper 'latexmk' missing!"
echo "*** Please install it if you intend to produce DV plans in PDF and/or ePub formats."
return 1
}
echo "All dependencies for human-readable Verification Plan generation are OK."

461
cva6/docs/VerifPlans/source/dvplan_AXI.md Normal file
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@ -0,0 +1,461 @@
# Module: AXI
## Feature: Burst
### Sub-feature: 000_Control_Signals
#### Item: 000
* **Requirement location:** AXI Design doc - Address structure
* **Feature Description**
All transaction performed by CVA6 are of type INCR. AxBURST = 0b01
* **Verification Goals**
Ensure that AxBURST == 0b01 is always true while AX_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F005_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 001
* **Requirement location:** AXI Design doc - Address structure
* **Feature Description**
All Read transaction performed by CVA6 are of burst lenght less or equal to 2. ARLEN = 0b01
* **Verification Goals**
Ensure that ARLEN == 0b01 is always true while AR_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F005_S000_I001
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 002
* **Requirement location:** AXI Design doc - Address structure
* **Feature Description**
All write transaction performed by CVA6 are of burst lenght equal to 1. AWLEN = 0b00
* **Verification Goals**
Ensure that AWLEN == 0b00 is always true while AW_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F005_S000_I002
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 003
* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.4.1)
* **Feature Description**
The size of a read transfer does not exceed the width of the data interface. The maximum value can be taking by AxSIZE is 3.
* **Verification Goals**
Ensure that AxSIZE <= log2(AXI_DATA_WIDTH/8) is always true while AR_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F005_S000_I003
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 007
* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A7.2.4)
* **Feature Description**
Exclusive access transactions cannot have a length greater than 16 beats
* **Verification Goals**
Ensure that AxLOCK && AxLEN <= 15 is always true while AX_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F005_S000_I007
* **Link to Coverage:**
* **Comments**
*(none)*
## Feature: Signals
### Sub-feature: 000_ID
#### Item: 000
* **Requirement location:** AXI Design doc - Transaction Identifiers
* **Feature Description**
The CVA6 identify read transaction with an ID equal to 0 or 1
* **Verification Goals**
Ensure that ARID == 0b01 || ARID == 0b00 is always true while AR_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F006_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 001
* **Requirement location:** AXI Design doc - Transaction Identifiers
* **Feature Description**
The CVA6 identify write transaction with an ID equal to 1
* **Verification Goals**
Ensure that AWID == 0b01 is always true while AW_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F006_S000_I001
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 001_User
#### Item: 000
* **Requirement location:** AXI Design doc - (table 2.2 and 2.5)
* **Feature Description**
User-defined extension for the write and read address channel is not supported. AxUSER = 0b00
* **Verification Goals**
Ensure that AxUSER = 0b00 is always true while AX_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F006_S001_I000
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 001
* **Requirement location:** AXI Design doc - (table 2.4)
* **Feature Description**
User-defined extension for the write response channel is not supported.
* **Verification Goals**
Ensure that BUSER = 0b00 is always true while B_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F006_S001_I001
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 002_Quality_of_Service
#### Item: 000
* **Requirement location:** AXI Design doc - (table 2.2 and 2.5)
* **Feature Description**
Quality of Service identifier is not supported. AxQOS = 0b0000
* **Verification Goals**
Ensure that AxQOS = 0b0000 is always true while AX_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F006_S002_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 003_Cache
#### Item: 000
* **Requirement location:** AXI Design Doc - Transaction Attributes: Memory types
* **Feature Description**
AxCACHE always take 0b0000.
* **Verification Goals**
Ensure that AxCACHE = 0b0000 is always true while AX_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F006_S003_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 004_Protection
#### Item: 000
* **Requirement location:** AXI Design Doc - (Table 2.2 and 2.5)
* **Feature Description**
Protection attributes always take the 0b000
* **Verification Goals**
Ensure that AxPROT = 0b000 is always true while AX_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F006_S004_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 008_Region
#### Item: 000
* **Requirement location:** AXI Design doc - (table 2.2 and 2.5)
* **Feature Description**
Region indicator is not supported. AxREGION = 0b0000
* **Verification Goals**
Ensure that AxREGION = 0b0000 is always true while AX_VALID is asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F006_S008_I000
* **Link to Coverage:**
* **Comments**
*(none)*
## Feature: Clock and Reset
### Sub-feature: 000_Signals_Value
#### Item: 000
* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2)
* **Feature Description**
A value of X on [Ax | x]VALID is not permitted when not in reset
* **Verification Goals**
Ensure that reset && [Ax | x]VALID != X is always true
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F007_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 001
* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2)
* **Feature Description**
A value of X on [Ax | x]READY is not permitted when not in reset
* **Verification Goals**
Ensure that reset && [Ax | x]READY != X is always true
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F007_S000_I001
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 002
* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Figure A3-1)
* **Feature Description**
[Ax | x]VALID is LOW for the first cycle after RESET goes HIGH
* **Verification Goals**
Ensure that [Ax | x]VALID is low the first cycle after RESET
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F007_S000_I002
* **Link to Coverage:**
* **Comments**
*(none)*
## Feature: Handshake_Process
### Sub-feature: 000_Stability
#### Item: 000
* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.2)
* **Feature Description**
All signals must remain stable when [Ax | x]VALID is asserted and [Ax | x]READY is LOW
* **Verification Goals**
Ensure that all the signals does not change while [Ax | x]VALID is asserted and [Ax | x]READY not yet asserted.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F008_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 001
* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.1)
* **Feature Description**
[Ax | x]VALID must remain asserted until [Ax | x]READY is HIGH
* **Verification Goals**
Ensure that [Ax | x]VALID does not change while [Ax | x]READY is low.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F008_S000_I001
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 001_Timing
#### Item: 000
* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1)
* **Feature Description**
The Manager must not wait for the Subordinate to assert ARREADY before asserting ARVALID
* **Verification Goals**
Ensure that no errors are encountered as the testbench injects random Ready-to-Valid delays. There are two cases to consider:
ARREADY is asserted on or after same cycle as ARVALID
ARREADY is asserted and deasserted during an interval when ARVALID is de-asserted
* **Pass/Fail Criteria:** Any/All
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F008_S001_I000
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 002
* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1)
* **Feature Description**
The Manager must not wait for the Subordinate to assert AWREADY before asserting AWVALID or WVALID.
* **Verification Goals**
Ensure that no errors are encountered as the testbench injects random Ready-to-Valid delays. There are four cases to consider:
AWREADY is asserted on or after same cycle as AWVALID and WVALID is de-asserted
AWREADY is asserted on or after same cycle as WVALID and AWVALID is de-asserted
AWREADY is asserted on or after same cycle as AWVALID and WVALID
AWREADY is asserted and deasserted during an interval when AWVALID and WVALID is de-asserted
* **Pass/Fail Criteria:** Any/All
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F008_S001_I002
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 003
* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1)
* **Feature Description**
The Manager must not wait for the Subordinate to assert WREADY before asserting AWVALID or WVALID.
* **Verification Goals**
Ensure that no errors are encountered as the testbench injects random Ready-to-Valid delays. There are four cases to consider:
WREADY is asserted on or after same cycle as AWVALID and WVALID is de-asserted
WREADY is asserted on or after same cycle as WVALID and AWVALID is de-asserted
WREADY is asserted on or after same cycle as AWVALID and WVALID
WREADY is asserted and deasserted during an interval when AWVALID and WVALID is de-asserted
* **Pass/Fail Criteria:** Any/All
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F008_S001_I003
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 005
* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1)
* **Feature Description**
The Subordinate must not wait for the Manager to assert [B | R]READY before asserting [B | R]VALID
* **Verification Goals**
No specific “observable checks” to be made in simulation. Testbench will always provide response data independently of [B | R]READY.
* **Pass/Fail Criteria:** Any/All
* **Test Type:** Other
* **Coverage Method:** N/A
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_1_F008_S001_I005
* **Link to Coverage:**
* **Comments**
*(none)*

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@ -0,0 +1,556 @@
# Module: CVXIF
## Feature: Issue Interface
### Sub-feature: 000_issue_req signals stable
#### Item: 000
* **Requirement location:**
* **Feature Description**
The “instr” and “mode” signals remain stable during an Issue request transaction.
* **Verification Goals**
Check that “mode” and “instr” are stable during an issue transaction (cannot be modified by an instruction when transaction issue is in process)
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 001_mode signal value
#### Item: 000
* **Requirement location:**
* **Feature Description**
When issue transaction starts, instruction and current CPU mode are provided
* **Verification Goals**
Check that a mode modification coming from execution of a first instruction is well provided to the following offloaded instruction
* **Pass/Fail Criteria:** Check RM
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S001_I000
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 001
* **Requirement location:**
* **Feature Description**
Check “mode” signal values.
* **Verification Goals**
Check that mode take a value that the CPU supports : Privilege level (2’b00 = User, 2’b01 = Supervisor, 2’b10 = Reserved,
2’b11 = Machine).
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
* **Test Type:** NDY (Not Defined Yet)
* **Coverage Method:** NDY (Not Defined Yet)
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S001_I001
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 002_rs_valid signal transition order
#### Item: 000
* **Requirement location:**
* **Feature Description**
During a transaction, each bit of “rs_valid” can transition from 0 to 1 but are not allowed to transition back to 0.
* **Verification Goals**
For issue transaction which lasts more than one cycle, check that asserted “rs_valid” signals do not transition back to 0.(for i in [0;2] if rs_valid[i] = 1 then rs_valid[i] → 0 cannot happen)
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S002_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 003_rs signal value
#### Item: 000
* **Requirement location:**
* **Feature Description**
If XLEN = X_RFR_WIDTH, then rs[X_NUM_RS-1:0] correspond to rs1 and rs2 CPU registers (and rs3 if X_NUM_RS = 3).
* **Verification Goals**
For every issue transaction check that rs signal correspond to rs1,rs2(rs3) value in CPU register file.
* **Pass/Fail Criteria:** Check RM
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S003_I000
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 001
* **Requirement location:**
* **Feature Description**
rs signals are only required to be stable during the part of a transaction in which these signals are considered to be valid.
* **Verification Goals**
Check that rs signals are stable when issue_valid==1 && the corresponding bit in rs_valid is 1.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** NDY (Not Defined Yet)
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S003_I001
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 002
* **Requirement location:**
* **Feature Description**
If XLEN != X_RFR_WIDTH , then rs[X_NUM_RS-1:0] correspond to even/odd register pair with rs1, rs2, (rs3) are even register and even register is provided in the 32 lower bits of rs signal.
* **Verification Goals**
For every issue transaction check that rs signal correspond to the concatenation of rs1/rs1+1,rs2/rs2+1, (rs3/rs3+1) value in CPU register file and even register is in the 32 lower bits of rs.
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
* **Test Type:** NDY (Not Defined Yet)
* **Coverage Method:** NDY (Not Defined Yet)
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S003_I002
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 004_Default value for unaccepted instruction
#### Item: 000
* **Requirement location:**
* **Feature Description**
If accept == 0 :
Writeback == 0; dualwrite == 0; dualread == 0; loadstore == 0; exc = 0.
* **Verification Goals**
Check that for writeback; dualwrite; dualread; loadstore; exc signals if accept == 0 then all those signals are 0.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S004_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 005_Illegal Instruction causes
#### Item: 000
* **Requirement location:**
* **Feature Description**
The CPU shall cause an illegal instruction if:
- an instruction is considered to be valid by the CPU and accepted by the coprocessor (accept = 1)
- neither to be valid by the CPU nor accepted by the coprocessor (accept = 0)
* **Verification Goals**
- CPU causes illegal instruction for instruction accepted by the core and the coprocessor.
- CPU causes illegal instruction exception for instruction that are not valid for coprocessor and CPU
* **Pass/Fail Criteria:** Check RM
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S005_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 006_issue uniquness
#### Item: 000
* **Requirement location:**
* **Feature Description**
Check for issue id validity.
* **Verification Goals**
Check that the issue interface doesn't issue an "id" that isn't legal to be used (has not fully completed).
* **Pass/Fail Criteria:** Other
* **Test Type:** Constrained Random
* **Coverage Method:** N/A
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S006_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 007_coprocessor decoding
#### Item: 000
* **Requirement location:**
* **Feature Description**
Accept = 1 if:
- coprocessor can handle the instruction based on decoding “instr”and "mode".
- “issue_valid” == 1 and required bit(s) of “rs_valid” are 1.
* **Verification Goals**
To be checked in coprocessor.
* **Pass/Fail Criteria:** Check RM
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S007_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 008_Transaction definition
#### Item: 000
* **Requirement location:**
* **Feature Description**
“issue_resp” signals and “issue_req” signals are accepted when “issue_valid” == “issue_ready” == 1
“issue_resp” is valid when "valid==ready==1".
“issue_req” is valid when "valid==1"
* **Verification Goals**
The definition of a transaction.
Not to be verified.
* **Pass/Fail Criteria:** Other
* **Test Type:** Other
* **Coverage Method:** N/A
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F000_S008_I000
* **Link to Coverage:**
* **Comments**
*(none)*
## Feature: Commit Interface
### Sub-feature: 000_commit_valid pulse
#### Item: 000
* **Requirement location:**
* **Feature Description**
The “commit_valid” == 1 exactly one clk cycle for every offloaded Instruction by the coprocessor (whether accepted or not).
* **Verification Goals**
For every offloaded instruction, check that commit_valid is asserted exactly one clk cycle ( is a pulse ).
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F001_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 001_commit transaction uniquness
#### Item: 000
* **Requirement location:**
* **Feature Description**
There is a unique commit transaction for every issue transaction (unique until an instruction has "fully completed" = its result has been submitted).
* **Verification Goals**
Check that the commit interface doesn't commit an "id" that isn't legal to be used (hasn't been seen in earlier stages, or has not fully completed).
* **Pass/Fail Criteria:** Self-Check
* **Test Type:** Other
* **Coverage Method:** N/A
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F001_S001_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 002_commit transaction for every issue transaction
#### Item: 000
* **Requirement location:**
* **Feature Description**
- The CPU shall perform a commit transaction for every issue transaction, independent of the accept value of the issue transaction.
- For each offloaded and accepted instruction the core is guaranteed to (eventually) signal that such an instruction is either no longer speculative and can be committed (commit_valid is 1 and commit_kill is 0) or that the instruction must be killed (commit_valid is 1 and commit_kill is 1).
* **Verification Goals**
Check that for each issue transaction, the commit transaction is sent at the same clock cycle than the issue transaction, or at any clock cycle after the issue transaction.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F001_S002_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 003_Transaction definition
#### Item: 000
* **Requirement location:**
* **Feature Description**
The signals in commit are valid when commit_valid is 1.
* **Verification Goals**
The definition of a transaction.
Not to be verified.
* **Pass/Fail Criteria:** Other
* **Test Type:** NDY (Not Defined Yet)
* **Coverage Method:** N/A
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F001_S003_I000
* **Link to Coverage:**
* **Comments**
*(none)*
## Feature: Result Interface
### Sub-feature: 000_no speculative result transaction
#### Item: 000
* **Requirement location:**
* **Feature Description**
A coprocessor is not allowed to perform speculative result transactions.
* **Verification Goals**
There is no result transaction for instructions that haven't been committed. Check that Result valid is only asserted for instructions that were committed (commit_valid == 1 && commit_kill == 0).
* **Pass/Fail Criteria:** Other
* **Test Type:** Other
* **Coverage Method:** N/A
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F002_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 001_out of order result transaction
#### Item: 000
* **Requirement location:**
* **Feature Description**
A coprocessor is allowed to provide results to the core in an out of order fashion.
* **Verification Goals**
Check that the CPU is able to receive the result in an out of order fashion.
* **Pass/Fail Criteria:** Check RM
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F002_S001_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 002_result transaction uniquness
#### Item: 000
* **Requirement location:**
* **Feature Description**
Each accepted offloaded (committed and not killed) instruction shall have exactly one result group transaction (even if no data needs to be written back to the CPU’s register file).
* **Verification Goals**
There is an unique result transaction for every accepted and commit instruction.
* **Pass/Fail Criteria:** Other
* **Test Type:** Other
* **Coverage Method:** N/A
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F002_S002_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 003_result packet stability
#### Item: 000
* **Requirement location:**
* **Feature Description**
The signals in result shall remain stable during a result transaction (except data ...)
* **Verification Goals**
Check that result signals (except data) are stable during result transaction (result_valid==1 jusqu'à valid==ready ==1)
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F002_S003_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 004_data stability
#### Item: 000
* **Requirement location:**
* **Feature Description**
Data is only required to remain stable during result transactions in which "we" is not 0.
* **Verification Goals**
Check that "data" remains stable when we==1.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F002_S004_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 005_synchronous exception
#### Item: 000
* **Requirement location:**
* **Feature Description**
The exc is used to signal synchronous exceptions. A synchronous exception will lead to a trap in CPU unless the corresponding instruction is killed.
* **Verification Goals**
Check that synchronous exception (exc ==1) leads to a trap in the CPU if the instruction is committed.
* **Pass/Fail Criteria:** Check RM
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F002_S005_I000
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 001
* **Requirement location:**
* **Feature Description**
exccode provides the least significant bits of the exception code bitfield of the mcause CSR.
* **Verification Goals**
Check that exccode signal is the value of the mcause CSR when exc == 1.
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
* **Test Type:** NDY (Not Defined Yet)
* **Coverage Method:** NDY (Not Defined Yet)
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F002_S005_I001
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 002
* **Requirement location:**
* **Feature Description**
 "we" shall be driven to 0 by the coprocessor for synchronous exceptions.
* **Verification Goals**
Check that "we" signal == 0 when exc == 1.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** NDY (Not Defined Yet)
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F002_S005_I002
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 006_"we" value when dualwrite
#### Item: 000
* **Requirement location:**
* **Feature Description**
we is 2 bits wide when XLEN` = 32 and X_RFW_WIDTH = 64, and 1 bit wide otherwise. If "we" is 2 bits wide, then we[1] is only allowed to be 1 if we[0] is 1 as well (i.e. for dual writeback).
* **Verification Goals**
For dualwrite instruction, check that we[1]==1 is only allowed if we[0] == 1.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F002_S006_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 007_proper result transaction
#### Item: 000
* **Requirement location:**
* **Feature Description**
Result transaction starts in the cycle that result_valid = 1 and ends in the cycle that both result_valid == result_ready == 1.
* **Verification Goals**
Check that result transaction ends properly.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_CVXIF_F002_S007_I000
* **Link to Coverage:**
* **Comments**
*(none)*

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# Module: FENCEI
## Feature: Fetching
### Sub-feature: 000_Fetching
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
* **Feature Description**
Instruction data for the next PC must be fetched after the fence.i instruction has executed (because only then can data-side stores have completed and caches have been updated).
* **Verification Goals**
Check that after a fence.i instruction retires then instr-side obi fetches the next instruction to be executed.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F000_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
## Feature: StoresVisible
### Sub-feature: 000_StoresVisible
#### Item: 000
* **Requirement location:** The RISC-V Instruction Set Manual
Volume I: Unprivileged ISA
Document Version 20191213
https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf
* **Feature Description**
After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction.
* **Verification Goals**
Do a fencei, but right before the fencei do a store to the instruction following the fencei, then see that the newly stored value is executed instead of the old instruction (e.g. change addi to use a different immediate).
* **Pass/Fail Criteria:** Check RM
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F001_S000_I000
* **Link to Coverage:**
* **Comments**
TODO must be added to regression lists!
#### Item: 001
* **Requirement location:** The RISC-V Instruction Set Manual
Volume I: Unprivileged ISA
Document Version 20191213
https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf
* **Feature Description**
After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction.
* **Verification Goals**
Do a fencei followed by any instruction, but let the environment detect when the fencei is being executed and change the memory holding the next instruction, then see that the old instruction is not executed.
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
* **Test Type:** Directed Non-SelfChk
* **Coverage Method:** NDY (Not Defined Yet)
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F001_S000_I001
* **Link to Coverage:**
* **Comments**
TODO missing cover!
#### Item: 002
* **Requirement location:** The RISC-V Instruction Set Manual
Volume I: Unprivileged ISA
Document Version 20191213
https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf
* **Feature Description**
After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction.
* **Verification Goals**
Let the instruction right before a fence.i write a different instruction to the address following the fence.i, then observe that the written instruction is executed instead of the original one and that no side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit instructions to force a noticable difference).
* **Pass/Fail Criteria:** Self-Check
* **Test Type:** Directed SelfChk
* **Coverage Method:** Testcase
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F001_S000_I002
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 003
* **Requirement location:** The RISC-V Instruction Set Manual
Volume I: Unprivileged ISA
Document Version 20191213
https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf
* **Feature Description**
After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction.
* **Verification Goals**
Check that after having read one value from an address, then after storing a value to that same address, if executing that address then the value shall always be that which was written (should work well in both sim/formal).
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F001_S000_I003
* **Link to Coverage:**
* **Comments**
TODO missing assert. (Note was ignored because of the difficulty of writing this as an assert for fv.)!
## Feature: ExternalHandshake
### Sub-feature: 000_ReqHigh
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
* **Feature Description**
When executing a fence.i instruction, fencei_flush_req_o shall rise sometime before executing the next instruction.
* **Verification Goals**
Check that when executing a fence.i instruction there will be a rising req before has retired.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F002_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 001_ReqWaitLsu
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph.
* **Feature Description**
When executing a fence.i instruction, if there is an ongoing store instruction (not limited to rv32i) that has not completed (data_rvalid_i clocked in as 1), then fencei_flush_req_o shall be low.
* **Verification Goals**
Make sure a store instruction is run right before a fence.i, and (possibly using obi stalls) ensure that the fence.i is pending retirement but holds off until the store's data_rvalid_i is clocked in and that fencei_flush_req_o was low until this point where it now goes high.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F002_S001_I000
* **Link to Coverage:**
* **Comments**
TODO missing cover!
### Sub-feature: 002_ReqWaitWritebuffer
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
* **Feature Description**
When executing a fence.i instruction, if the write buffer is not empty, then fencei_flush_req_o shall be low until the write buffer has been emptied and the corresponding data_rvalid_i have been clocked in as 1.
* **Verification Goals**
Fill up the write buffer prior to executing a fence.i and ensure that fencei_flush_req_o holds off going high until the write buffer to has been emptied.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F002_S002_I000
* **Link to Coverage:**
* **Comments**
TODO missing cover!
### Sub-feature: 003_ReqWaitXinterface
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
* **Feature Description**
When executing a fence.i instruction, if the X interface is busy with any store operations, then fencei_flush_req_o shall be low until all the store operations are done
* **Verification Goals**
Issue one or more store instructions that uses the X interface and ensure that fencei_flush_req_o waits until the stores have all completed before going high.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F002_S003_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 004_ReqWaitObi
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph.
* **Feature Description**
fencei_flush_req_o shall not go high while there are outstanding stores on the obi bus.
* **Verification Goals**
Check vs the OBI monitors that there are no outstanding stores at the time fencei_flush_req_o goes high.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F002_S004_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 005_ReqLow
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph.
* **Feature Description**
When fencei_flush_req_o is high, it shall stay high until fencei_flush_req_o and fencei_flush_ack_i has been sampled high simultaneously, and then then it shall go low.
* **Verification Goals**
Check that when fencei_flush_req_o is high, then it behaves correctly with regards to fencei_flush_ack_i.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F002_S005_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 006_AckChange
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph.
* **Feature Description**
fencei_flush_ack_i is allowed to change freely on any clock cycle: It can be permanently high, go high without fence.i and retract, go high at the same cycle as the req, it can delay arbitrarily after req and then go high, etc
* **Verification Goals**
Drive ack to test all permutations of rising/falling before/after/on req, acking without req, retracting an early ack, delaying ack after req, etc.
* **Pass/Fail Criteria:** Any/All
* **Test Type:** ENV Capability
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F002_S006_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 007_AckWithold
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
* **Feature Description**
If req is high, but ack never comes, then the core keeps on stalling and the fence.i is blocked from completing.
* **Verification Goals**
Upon a req, try witholding ack for a long time and see that the fence.i can be stalled arbitrarily long (should have covers for ack delays of at least {[0:5]}).
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F002_S007_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 008_BranchInitiated
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph.
* **Feature Description**
After req and ack has been sampled simultaneously high and when req is low again, then the core takes a branch to the instruction after the fence.i instruction.
* **Verification Goals**
Check that the branch is taken at the point after req and ack has been simultaneously high.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F002_S008_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 009_ShadowingBranch
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
* **Feature Description**
If the fence.i ends up not retiring because it was preceeded by a taken branch or a jump, then the fencei_flush_req_o shall not go high
* **Verification Goals**
Take a branch or do a jump to skip a fence.i, and ensure that fencei_flush_req_o doesn't go high.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F002_S009_I000
* **Link to Coverage:**
* **Comments**
*(none)*
## Feature: MultiCycle
### Sub-feature: 000_MultiCycle
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
* **Feature Description**
Given zero stalls on neither instr-side and data-side obi nor on fencei_flush_ack_i, then the execution of fence.i takes a fixed number of cycles.
* **Verification Goals**
Check that, given ideal conditions, the cycle count of fence.i is as expected.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F003_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
## Feature: StoresComplete
### Sub-feature: 000_StoresComplete
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph.
* **Feature Description**
Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about syncronization with instruction fetch, but rather seeing that the stores are not aborted).
* **Verification Goals**
Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged).
* **Pass/Fail Criteria:** Self-Check
* **Test Type:** Directed SelfChk
* **Coverage Method:** Testcase
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F004_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
### Sub-feature: 001_StoresComplete
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
* **Feature Description**
Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about syncronization with instruction fetch, but rather seeing that the stores are not aborted).
* **Verification Goals**
Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged).
* **Pass/Fail Criteria:** Check RM
* **Test Type:** Constrained Random
* **Coverage Method:** Testcase
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F004_S001_I000
* **Link to Coverage:**
* **Comments**
*(none)*
## Feature: Flush
### Sub-feature: 000_Flush
#### Item: 000
* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence
* **Feature Description**
When fence.i is executed, then any prefetched instructions shall be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, write buffer is flushed, and data_req_o is eventually supressed.
* **Verification Goals**
Check that a fence.i will cause flushing of the pipeline, prefetcher, write buffer, and data_req_o.
* **Pass/Fail Criteria:** Assertion
* **Test Type:** ENV Capability
* **Coverage Method:** Assertion Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F005_S000_I000
* **Link to Coverage:**
* **Comments**
TODO missing assert. (Have not checked/covered that the pipeline/writebuffer content is actually purged. Or that any memory change WILL be the next instr word.)!
## Feature: UnusedFields
### Sub-feature: 000_UnusedFields
#### Item: 000
* **Requirement location:** The RISC-V Instruction Set Manual
Volume I: Unprivileged ISA
Document Version 20191213
https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf
* **Feature Description**
imm[11:0], rs1, rd are reserved for future extensions, and implementations shall ignore them
* **Verification Goals**
Try giving random values in those fields and see that all else works as expected
* **Pass/Fail Criteria:** Check RM
* **Test Type:** Constrained Random
* **Coverage Method:** Functional Coverage
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
* **Unique verification tag:** VP_FENCEI_F006_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*

1432
cva6/docs/VerifPlans/source/dvplan_ISA.md → cva6/docs/VerifPlans/source/dvplan_ISA_RV32.md
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69
cva6/docs/VerifPlans/source/dvplan_csr-access.md Normal file
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@ -0,0 +1,69 @@
# Module: CSR ACCESS VERIFICATION
## Feature: machineScratch(MSCRATCH)
### Sub-feature: 000_MSCRATCH
#### Item: 000
* **Requirement location:** riscv-privileged-20211203
* **Feature Description**
To verify the Power-on Reset value for MSCRATCH CSR.
Address Offset : 0x340
Width (bits) : 32
Access Type : RW
Reset Value : 0x00000000
priviliged mode : Machine
* **Verification Goals**
Read MSCRATCH CSR to check default POR value that should be equal to 0x00000000.
* **Pass/Fail Criteria:** Check RM
* **Test Type:** Directed SelfChk
* **Coverage Method:** N/A
* **Applicable Cores:** CV32A6_v0.1.0
* **Unique verification tag:** VP_csr-test-ident_F000_S000_I000
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 001
* **Requirement location:** riscv-privileged-20211203
* **Feature Description**
Verifying R/W access of a MSCRATCH CSR by writing random valid data like 0xFFFFFFFF, 0XA5A5A5A5, 0X5A5A5A5A ... and Read back CSR values to check correctness.
* **Verification Goals**
The read values of MSCRATCH CSR should matches with written random data values.
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
* **Test Type:** NDY (Not Defined Yet)
* **Coverage Method:** NDY (Not Defined Yet)
* **Applicable Cores:** CV32A6_v0.1.0
* **Unique verification tag:** VP_csr-test-ident_F000_S000_I001
* **Link to Coverage:**
* **Comments**
*(none)*
#### Item: 002
* **Requirement location:**
* **Feature Description**
Verifying MSCRATCH CSR in other privilige modes(supervisor, user)
* **Verification Goals**
It is expected that accessing Machine Mode CSRs in lower privilige modes will raise an exception.
* **Pass/Fail Criteria:** Check RM
* **Test Type:** Directed SelfChk
* **Coverage Method:** N/A
* **Applicable Cores:** CV32A6_v0.1.0
* **Unique verification tag:** VP_csr-test-ident_F000_S000_I002
* **Link to Coverage:**
* **Comments**
*(none)*

5
cva6/docs/VerifPlans/source/dvplan_intro.rst
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@ -6,7 +6,7 @@
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
Original Author: Jean-Roch COULON - Thales
.. _DVPLAN_INTRO:
@ -71,8 +71,7 @@ Description of the framework:
Contributors
------------
| Jean-Roch Coulon
(`jean-roch.coulon@thalesgroup.com <mailto:jean-roch.coulon@thalesgroup.com>`__)
| Jean-Roch Coulon - Thales
[TO BE COMPLETED]

6
cva6/docs/VerifPlans/source/index.rst
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@ -24,5 +24,9 @@ CV32A6-step1 Design Verification Plan
dvplan_intro
dvplan_FRONTEND
dvplan_ISA
dvplan_ISA_RV32
dvplan_CVXIF
dvplan_AXI
dvplan_FENCEI
dvplan_csr-access

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77
cva6/docs/verif-approvals.md Normal file
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# Approvals of CVA6 verification tasks
For each verification task on CVA6 v5.0.0, the artefacts have to be checked.
It means dedicated approvals for each artifact produced by engineers.
## Approval
To approve an artefact, the approving person has to update this document.
## User manual chapter/section
For some the topics, the user manual chapter may only describe differences
and precisions with existing specifications
like RISC-V Instruction Set Manual, AXI Protocol, or CV-X-IF.
For other ones (when no specification already exists), it shall be a brand new chapter.
Each chapter/section has to be formally approved.
## DV plan (VP tool)
Based on the user manual, DV plan is written using the VP tool which
provides a way to have text files allowing easier differences than binary format.
Each DV plan has to be formally approved.
## Test bench
To implement the DV plan, the test bench has to be enriched.
When needed a UVM agent has to be developed or to be reused from core-v-verif.
Such UVM agents have to be generic as much as possible to be reusable.
Specific CVA6 behaviours have to be part of the CVA6 UVM environment.
To exercise the DUT, tests have to be added. Two types of tests are possible:
- Generated ones: produced by riscv-dv
- Directed ones: hand crafted to address specific cases difficult to exercise with generated tests
The implementation of the different components (tests, code coverage, assertions, agents,...) have to be formally approved.
## Coverage
- Functional coverage: if not 100%, missing points explained and approved
- Code coverage: provide delta results after new tests
- Results available in CI dashboard
The results of coverage and the missing points have to be formally approved.
## GitHub issues
Once running tests, discrepancies with the expected behaviour can be observed.
For each of them, a GitHub issue has to be created with the relevant
information (e.g. a detailed explanation how to reproduce the problem).
Each issue has to be assigned.
## ISACOV
| Task | Date | Owner | Approved by | Commit hash | link to extra information (GitHub issue, doc,..) |
| --------------- | ---------- | --------------------- | --------------------- | ------------ | ------------------------------------------------ |
| User Manual | 2023-05-26 | Ayoub Jalali | André Sintzoff | [be58d57d](https://github.com/openhwgroup/cva6/commit/be58d57d)| [User Manual chapter](https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/RISCV_Instructions.html) |
| DV plan | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
| Test bench | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
| Coverage | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
| Assigned Issues | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
## CV-X-IF
| Task | Date | Owner | Approved by | Commit hash | link to extra information (GitHub issue, doc,..) |
| --------------- | ---------- | --------------------- | --------------------- | ------------ | ------------------------------------------------ |
| User Manual | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
| DV plan | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
| Test bench | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
| Coverage | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
| Assigned Issues | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
## AXI
| Task | Date | Owner | Approved by | Commit hash | link to extra information (GitHub issue, doc,..) |
| --------------- | ---------- | --------------------- | --------------------- | ------------ | ------------------------------------------------ |
| User Manual | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
| DV plan | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
| Test bench | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
| Coverage | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |
| Assigned Issues | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters |

18
cva6/env/corev-dv/cva6_asm_program_gen.sv vendored
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@ -25,7 +25,7 @@
//-----------------------------------------------------------------------------------------
// CVA6 assembly program generator - extension of the RISC-V assembly program generator.
//
// Overrides gen_program_header()
// Overrides gen_program_header() and gen_test_done()
//-----------------------------------------------------------------------------------------
class cva6_asm_program_gen_c extends riscv_asm_program_gen;
@ -38,7 +38,12 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen;
virtual function void gen_program_header();
string str[$];
instr_stream.push_back(".include \"user_define.include\"");
cva6_instr_gen_config_c cfg_cva6;
`DV_CHECK_FATAL($cast(cfg_cva6, cfg), "Could not cast cfg into cfg_cva6")
if (cfg_cva6.enable_x_extension) begin //used for cvxif custom test
instr_stream.push_back(".include \"x_extn_user_define.h\"");
end
instr_stream.push_back(".include \"user_define.h\"");
instr_stream.push_back(".globl _start");
instr_stream.push_back(".section .text");
if (cfg.disable_compressed_instr) begin
@ -55,6 +60,15 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen;
end
endfunction
virtual function void gen_test_done();
string str = format_string("test_done:", LABEL_STR_LEN);
instr_stream.push_back(str);
instr_stream.push_back({indent, "li gp, 1"});
instr_stream.push_back({indent, "sw gp, tohost, t5"});
instr_stream.push_back({indent, "wfi"});
endfunction
endclass : cva6_asm_program_gen_c
`endif // __CVA6_ASM_PROGRAM_GEN_SV__

54
cva6/env/corev-dv/cva6_instr_base_test.sv vendored Normal file
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@ -0,0 +1,54 @@
/*
* Copyright 2018 Google LLC
* Copyright 2020 OpenHW Group
* Copyright 2023 Thales
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//------------------------------------------------------------------------------
// CORE-V instruction generator base test:
// - extension of the RISC-V instruction generator base test.
//
//------------------------------------------------------------------------------
class cva6_instr_base_test_c extends riscv_instr_base_test;
`uvm_component_utils(cva6_instr_base_test_c)
function new(string name="", uvm_component parent=null);
super.new(name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
override_asm_program_gen();
override_gen_config();
super.build_phase(phase);
endfunction
virtual function void override_asm_program_gen();
`uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW)
uvm_factory::get().set_type_override_by_type(riscv_asm_program_gen::get_type(),
cva6_asm_program_gen_c::get_type());
`uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW)
endfunction
virtual function void override_gen_config();
`uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW)
uvm_factory::get().set_type_override_by_type(riscv_instr_gen_config::get_type(),
cva6_instr_gen_config_c::get_type());
`uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW)
endfunction
endclass : cva6_instr_base_test_c

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