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Update the specification following the last commits (RVF, SUPERSCALAR,...) (#2155)

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JeanRochCoulon 2024-05-27 18:02:40 +02:00 • committed by GitHub
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commit f0adb7680b
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6 changed files with 77 additions and 35 deletions
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54
docs/04_cv32a65x_design/source/parameters_cv32a65x.rst
View file

@ -52,7 +52,11 @@
- Zicond RISC-V extension
- False
* - FpuEn
* - RVF
- Floating Point
- False
* - RVD
- Floating Point
- False
@ -72,6 +76,14 @@
- Non standard Vector Floating Point extension
- False
* - PerfCounterEn
- Perf counters
- False
* - MmuPresent
- MMU
- False
* - RVS
- Supervisor mode
- False
@ -182,7 +194,7 @@
* - MemTidWidth
- TODO
- 2
- 4
* - IcacheByteSize
- Instruction cache size (in bytes)
@ -196,6 +208,14 @@
- Instruction cache line width
- 128
* - DCacheType
- Cache Type
- config_pkg::HPDCACHE
* - DcacheIdWidth
- Data cache ID
- 1
* - DcacheByteSize
- Data cache size (in bytes)
- 32768
@ -212,6 +232,10 @@
- User field on data bus enable
- 0
* - WtDcacheWbufDepth
- Write-through data cache write buffer depth
- 2
* - FetchUserEn
- User field on fetch bus enable
- 0
@ -228,13 +252,21 @@
- Number of commit ports
- 1
* - NrLoadPipeRegs
- Load cycle latency number
- 0
* - NrStorePipeRegs
- Store cycle latency number
- 0
* - NrScoreboardEntries
- Scoreboard length
- 4
* - NrLoadBufEntries
- Load buffer entry buffer
- 1
- 2
* - MaxOutstandingStores
- Maximum number of outstanding stores
@ -251,3 +283,19 @@
* - BHTEntries
- Branch history entries
- 32
* - InstrTlbEntries
- MMU instruction TLB entries
- 2
* - DataTlbEntries
- MMU data TLB entries
- 2
* - UseSharedTlb
- MMU option to use shared TLB
- True
* - SharedTlbDepth
- MMU depth of shared TLB
- 64

6
docs/04_cv32a65x_design/source/port_frontend.rst
View file

@ -106,19 +106,19 @@
- out
- Handshake's data between fetch and decode
- ID_STAGE
- fetch_entry_t
- fetch_entry_t[ariane_pkg::SUPERSCALAR:0]
* - ``fetch_entry_valid_o``
- out
- Handshake's valid between fetch and decode
- ID_STAGE
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
* - ``fetch_entry_ready_i``
- in
- Handshake's ready between fetch and decode
- ID_STAGE
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below

16
docs/04_cv32a65x_design/source/port_id_stage.rst
View file

@ -40,49 +40,49 @@
- in
- Handshake's data between fetch and decode
- FRONTEND
- fetch_entry_t
- fetch_entry_t[ariane_pkg::SUPERSCALAR:0]
* - ``fetch_entry_valid_i``
- in
- Handshake's valid between fetch and decode
- FRONTEND
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
* - ``fetch_entry_ready_o``
- out
- Handshake's ready between fetch and decode
- FRONTEND
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
* - ``issue_entry_o``
- out
- Handshake's data between decode and issue
- ISSUE
- scoreboard_entry_t
- scoreboard_entry_t[ariane_pkg::SUPERSCALAR:0]
* - ``orig_instr_o``
- out
- Instruction value
- ISSUE
- logic[31:0]
- logic[ariane_pkg::SUPERSCALAR:0][31:0]
* - ``issue_entry_valid_o``
- out
- Handshake's valid between decode and issue
- ISSUE
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
* - ``is_ctrl_flow_o``
- out
- Report if instruction is a control flow instruction
- ISSUE
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
* - ``issue_instr_ack_i``
- in
- Handshake's acknowlege between decode and issue
- ISSUE
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
* - ``irq_i``
- in

6
docs/04_cv32a65x_design/source/port_instr_queue.rst
View file

@ -106,19 +106,19 @@
- out
- Handshake’s data with ID_STAGE
- ID_STAGE
- fetch_entry_t
- fetch_entry_t[ariane_pkg::SUPERSCALAR:0]
* - ``fetch_entry_valid_o``
- out
- Handshake’s valid with ID_STAGE
- ID_STAGE
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
* - ``fetch_entry_ready_i``
- in
- Handshake’s ready with ID_STAGE
- ID_STAGE
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below

10
docs/04_cv32a65x_design/source/port_issue_stage.rst
View file

@ -46,31 +46,31 @@
- in
- Handshake's data with decode stage
- ID_STAGE
- scoreboard_entry_t
- scoreboard_entry_t[SUPERSCALAR:0]
* - ``orig_instr_i``
- in
- instruction value
- ID_STAGE
- logic[31:0]
- logic[SUPERSCALAR:0][31:0]
* - ``decoded_instr_valid_i``
- in
- Handshake's valid with decode stage
- ID_STAGE
- logic
- logic[SUPERSCALAR:0]
* - ``is_ctrl_flow_i``
- in
- Is instruction a control flow instruction
- ID_STAGE
- logic
- logic[SUPERSCALAR:0]
* - ``decoded_instr_ack_o``
- out
- Handshake's acknowlege with decode stage
- ID_STAGE
- logic
- logic[SUPERSCALAR:0]
* - ``rs1_forwarding_o``
- out

20
docs/04_cv32a65x_design/source/port_scoreboard.rst
View file

@ -48,12 +48,6 @@
- TO_BE_COMPLETED
- logic
* - ``unresolved_branch_i``
- in
- We have an unresolved branch
- TO_BE_COMPLETED
- logic
* - ``rd_clobber_gpr_o``
- out
- TO_BE_COMPLETED
@ -136,43 +130,43 @@
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- scoreboard_entry_t
- scoreboard_entry_t[ariane_pkg::SUPERSCALAR:0]
* - ``orig_instr_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic[31:0]
- logic[ariane_pkg::SUPERSCALAR:0][31:0]
* - ``decoded_instr_valid_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
* - ``decoded_instr_ack_o``
- out
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
* - ``orig_instr_o``
- out
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic[31:0]
- logic[ariane_pkg::SUPERSCALAR:0][31:0]
* - ``issue_instr_valid_o``
- out
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
* - ``issue_ack_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
- logic[ariane_pkg::SUPERSCALAR:0]
* - ``resolved_branch_i``
- in