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21 commits

Author SHA1 Message Date
André Sintzoff
cbb08e8d19
docs: clarify WLRL CSR fields on CVA6 (fix #1053) (#2733)
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as priv-csrs.adoc was not yet tailored for CVA6, the file is copied
and tailored

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2025-01-23 16:48:13 +01:00
André Sintzoff
02092dbcf0
riscv-isa-manual: ignore mm-formal.adoc (#2723)
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as this appendix requires Java and as it is not relevant for CV32A65X

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-01-21 17:42:39 +01:00
André Sintzoff
b6b259914a
fix 8e5872c03 (add missing smctr.adoc file) (#2720)
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2025-01-21 16:25:18 +01:00
André Sintzoff
8e5872c03b
update riscv-isa-manual to riscv-isa-release-4f277ff-2025-01-17 (#2717)
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Since last riscv-isa-manual update (CVA6 commit 67a6ae966):
	- minor documentation changes
	- new unsupported Zsmctr extension
	- add missing asciidoctor-lists gem in dependencies/Gemfile

Gemfile update is needed for ReadTheDocs

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-01-21 09:56:51 +01:00
André Sintzoff
1c6b89df5b
doc: RVZicntr extension can be not supported (#2699)
counters.adoc: condition around Zicntr text
2025-01-09 14:38:49 +01:00
Zbigniew Chamski
ed89c717f7
[CV32A65X] Update PMPADDRn spec to make bit 0 ROCST 0. Update config files. (#2651)
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Update CV32A65X-annotated privileged ISA specification to reflect the fact that with PMP granularity 8 and only supported PMP address matching modes being OFF and TOR, bit 0 of the pmpaddr0..pmpaddr7 registers can be safely made read-only zero. Update riscv-config specifications and its generated files accordingly.
2024-12-09 13:22:38 +01:00
André Sintzoff
7aad781b74
doc: pmp granularity equals to 8-byte (#2572) 2024-11-04 09:27:23 +01:00
slgth
ab2283c075
doc: keep documentation in sync with the code (#2558)
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Both the ISA and design documentations use some parameters generated from the RTL (ports, parameters).
As of now, they are committed to the repository and can be out of sync with the code.

This PR removes them from the repository and freshly generates them from the code when building HTML files.

This PR also removes prebuilt HTML files (design & ISA docs) and generates them when building the top-level Read the Docs documentation (make -C docs).
2024-10-25 12:27:09 +02:00
André Sintzoff
67a6ae966c
update riscv-isa-manual to riscv-isa-release-2c07aa2-2024-10-18 (#2560)
Since last riscv-isa-manual update (CVA6 commit 3059b1cb2):
        - Privileged Architecture 1.13 ratified
        - minor documentation changes
        - wavedrom file renamed to .edn
2024-10-22 14:44:02 +02:00
André Sintzoff
5131fb030c
doc PMP: rephrase PMP configuration description (#2540) 2024-10-11 09:12:22 +02:00
André Sintzoff
3059b1cb25
update riscv-isa-manual to riscv-isa-release-5ddbdd678-2024-08-01 (#2434)
since last riscv-isa-manual update (CVA6 commit 0bd8b8693)
2024-08-07 11:52:07 +02:00
slgth
e9648eaf8c
Design documentation: AsciiDoc conversion (#2399) 2024-07-25 17:18:27 +02:00
JeanRochCoulon
8d413b7c54
doc PMA: cv32a65x is always idempotent and without caches (#2377) 2024-07-22 11:15:06 +00:00
André Sintzoff
8c70976759
docs: use correct commit for riscv-isa-manual submodule (#2368)
fix after 8fa590b5c
2024-07-15 12:42:07 +00:00
Guillaume Chauvon
8fa590b5c3
CVXIF 1.0.0 (#2340) 2024-07-12 10:53:18 +02:00
JeanRochCoulon
58d490b461
Update PMP entry number from 16 to 64 (#2343) 2024-07-10 09:54:16 +00:00
André Sintzoff
51114ee0a1
machine.adoc: add missing table (#2331)
For CVA6, add table:
Encoding of A field in PMP configuration registers
2024-07-05 23:49:20 +02:00
André Sintzoff
0bd8b8693a
update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03 (#2323)
since last riscv-isa-manual update (CVA6 commit 105d3601b):
- minor documentation changes
- use of docs-resources submodule inside riscv-isa-manual
- requires asciidoctor-lists
2024-07-05 12:06:16 +02:00
LQUA
66caecdfe6
Add RISCV documentation for cv64a6_mmu (#2315) 2024-07-03 17:24:07 +02:00
André Sintzoff
89568b0c10
doc: clarify mtval register description when not enabled (#2271) 2024-06-19 13:00:33 +02:00
slgth
802066bfd3
docs: move riscv-isa-manual outside of cv32a65x documentation (#2264) 2024-06-16 23:20:41 +02:00