19 commits

Author	SHA1	Message	Date
Florian Zaruba	3c40965e8a	Merge remote-tracking branch 'origin/ariane_next' into fpga_dev	2018-11-17 22:38:54 +01:00
Florian Zaruba	c907270502	First instructions passing on Spike	2018-11-03 22:44:45 +01:00
Florian Zaruba	95519e4a2a	Clean-up fpga folder	2018-10-29 11:53:21 +01:00
Florian Zaruba	25a0470df6	Fix Issue #127 (#128) ... * Switch to AXI structs * Fix problems with ID width mismatches * 📝 Update CHANGELOG	2018-10-17 16:30:58 +02:00
Florian Zaruba	9d1f6b1b76	Fix multi-hart debug issues	2018-09-14 10:57:48 +02:00
Florian Zaruba	3ec61a67cc	Change build dir, adapt README	2018-07-24 18:24:45 -07:00
Florian Zaruba	527e944577	🚧 Verilator debug integration	2018-07-10 09:20:07 -07:00
Florian Zaruba	62fffe6a9a	Add correct dependencies	2018-03-06 17:20:47 +01:00
Florian Zaruba	98b924a76f	📝 Update doc add .travis.yml	2018-02-05 13:22:52 +01:00
Florian Zaruba	30b1e5f464	Add option parsing to verilator environment	2018-02-01 18:52:03 +01:00
Florian Zaruba	491ea33be4	Update riscv-torture test framework	2018-01-23 17:12:27 +01:00
Florian Zaruba	aa9d4e6642	Add CI scripts	2018-01-23 11:57:19 +01:00
Florian Zaruba	008af68b58	Start implementing Verilator wrapper	2018-01-17 19:23:05 +01:00
Florian Zaruba	492ad51c7c	Add support for device tree ... - compiling - loading	2017-07-13 18:05:29 +02:00
Florian Zaruba	5625728f01	Add ability to dump torture signature	2017-06-27 10:40:18 +02:00
Florian Zaruba	34976972b8	Update .gitignore	2017-06-25 18:16:11 +02:00
Florian Zaruba	aa50f69434	Adapt dcache arbiter testbench using new dcache if	2017-05-29 15:51:31 +02:00
Florian Zaruba	c1d00a43e7	💚 Fixing Scoreboard testbench after #7	2017-04-28 11:57:11 +02:00
Florian Zaruba	1f526a8c78	Doc: Reorganized documentation, generating pages	2017-04-08 12:31:59 +02:00