11 commits

Author	SHA1	Message	Date
JeanRochCoulon	58d490b461	Update PMP entry number from 16 to 64 (#2343)	2024-07-10 09:54:16 +00:00
André Sintzoff	51114ee0a1	machine.adoc: add missing table (#2331) ... For CVA6, add table: Encoding of A field in PMP configuration registers	2024-07-05 23:49:20 +02:00
André Sintzoff	0bd8b8693a	update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03 (#2323) ... since last riscv-isa-manual update (CVA6 commit 105d3601b): - minor documentation changes - use of docs-resources submodule inside riscv-isa-manual - requires asciidoctor-lists	2024-07-05 12:06:16 +02:00
LQUA	66caecdfe6	Add RISCV documentation for cv64a6_mmu (#2315)	2024-07-03 17:24:07 +02:00
André Sintzoff	89568b0c10	doc: clarify mtval register description when not enabled (#2271)	2024-06-19 13:00:33 +02:00
slgth	802066bfd3	docs: move riscv-isa-manual outside of cv32a65x documentation (#2264)	2024-06-16 23:20:41 +02:00
JeanRochCoulon	7e8e2c931f	Fix CSR chapter insertion and rename Design Doc names (remove "for cv32a65x") (#2262)	2024-06-14 15:39:22 +02:00
André Sintzoff	105d3601b6	update riscv-isa-manual to riscv-isa-release-c8c8075-2024-06-12 (#2253)	2024-06-13 16:45:04 +02:00
André Sintzoff	361b17e7b0	cv32a65x doc: fix RISC-V unpriv pdf generation ... issue introduced in 718c4e23 Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>	2024-06-12 11:32:36 +02:00
André Sintzoff	d5b7cc77ff	cv32a65x doc: split unpriv and priv HTML pages ... Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>	2024-06-12 11:18:31 +02:00
slgth	f57a6c0106	Move CV32A65X documentation into its own chapter (#2236)	2024-06-11 18:01:25 +02:00