github-mirrors/cva6 - Blizzard Finnegan's Codeforge

7360 commits 16 branches 13 tags 288 MiB

Author	SHA1	Message	Date
André Sintzoff	21506e4c66	docs: add CV32A60X configuration in RISC-V ISA manual (#2838 ) Some checks are pending bender-up-to-date / bender-up-to-date (push) Waiting to run Details ci / build-riscv-tests (push) Waiting to run Details ci / execute-riscv64-tests (push) Blocked by required conditions Details ci / execute-riscv32-tests (push) Blocked by required conditions Details * docs: spec_builder.py: add missing extensions * docs: fix unpriv manual (opcode map, Zcmop) * in opcode map, write not used when corresponding extension is disabled * use correct condition for Zcmop extension * docs: remove PMP chapter when no PMP * docs: add tailored RISC-V ISA manual for CV32A60X configuration Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>	2025-03-19 00:03:00 +01:00
slgth	e9648eaf8c	Design documentation: AsciiDoc conversion (#2399 )	2024-07-25 17:18:27 +02:00

Renamed from docs/riscv-isa/src/config_define.adoc (Browse further)