This fixes the paths for the CV32A60X-specific documentation (from the cv32a60x branch). Whenever the cv32a60x branch is updated, the documentation will be regenerated by RTD.
This macro is not required and makes the file harder to parse.
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Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Following what was done in branch_unit, I set up a default value for hypervisor exception fields in cvxif_fu.
Should fix issue #2831
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Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
* wait for dashboard generation before commenting PRs with pipeline report link.
* change dashboard link and badge
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
* docs: spec_builder.py: add missing extensions
* docs: fix unpriv manual (opcode map, Zcmop)
* in opcode map, write not used when corresponding extension is disabled
* use correct condition for Zcmop extension
* docs: remove PMP chapter when no PMP
* docs: add tailored RISC-V ISA manual for CV32A60X configuration
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
This PR assigns 0 to tinst by default.
Even though tinst is only used when CVA6Cfg.RVH is enabled, I chose to assign it a default value in all configurations, since the signal is defined for all configurations.
Fixes#2803
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Bring the tests added by #2648 in Gitlab CI:
* Rename PMP tests with generic names
* Add a CV32A60X PMP testlist
* Adapt PMP test script to run the testlist
* Add a CI job running said test script
Verification Plan provided in VP_TOOL for the PMP. The verification plan should be complete, however only a partial set of the tests is available. This is not included in the CI but a bash script is available to run the test.
Changing the type of Kgates from int to float in order to add more granularity on the report (usefull when the difference is under 1k Gates)
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
This code hits verilator/verilator#5829 due to the use of partial assignments to dcache_rtrn_o in this always block, while reading other bits of the same packed struct elsewhere in the block.
The actual effect of this is that with a Verilator simulation, invalidation requests incoming from the coherence network are sometimes ignored breaking AMOs.
Moving the assignments to the bits read in the always block into the same always block avoids this issue.
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
This PR adds a new two-level BHT predictor with private history. The new BPType parameters allow choosing between the original BHT and the new one.
Co-authored-by: Gianmarco Ottavi <ottavig91@gmail.com>
Adds to #2798. Sorry for noticing this only now. Together with #2798, this reverts a bug that was introduced in #2528.
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
A new configuration file and core v target is added to start working on a 64 bit CVA6 core.
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
The load and store units sample the MMU exception one cycle after
`dtlb_hit` is asserted. However, misaligned exceptions are currently fed
through the MMU, potentially attributing a misaligned exception to the
*preceding* instruction. Fix this by latching the misaligned exception.
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Update Altera APU design to support linux in both 32 and 64 bits
* Move JTAG UART inside peripherals to properly connect the interruput request to PLIC
* Reduce the frequency of operation to 100MHz to avoid timing issues in 64bit version
* Update UART read and write operation in bootrom to allow keyboard interrupt
Use separate parametrization for RVF and RVD support. In the cv32a6_imafc_sv32 configuration RVD is currently enabled, leading to compilation errors.
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
As discussed in #2775 (comment) , this pr enables gdb back on the toolchain build scripts. It also updates the README to use the current toolchain name for the gdb section.
Currently, the instruction trace update logic is triggered on both clock
edges, leading to double entries in the instruction trace and a wrong
cycle count. Fix this by updating the trace only on positive clock edges.
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
`src/bootrom/bootrom_$(XLEN).sv` does not exist relative to the Makefile
and is not built by the recipe. Like all other FPGA source files, prefix
the full path to `bootrom_$(XLEN).sv`.
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Hi! Some tools like morty struggle with this expression. I suggest this very simple rewrite. No need for fancy constructs here.
Thanks @flaviens for this contribution
Add parameter CoproType to select which coprocessor to instantiate when CvxifEn == 1
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
let CI fail if verible catches mismatches to prevent them from being accidentally merged
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Follow-up to the discussion on extending Linux support to the Ara vector processor.
* Main changes:
Add:
Add external MMU interface to share the MMU with the external accelerator.
Add avoid_neg() function used to clip negative numbers to zero. Useful for parametric array sizes and vector multipliers.
Modifications:
2 commit ports by default in cv64a6_imafdcv_config_pkg.
Change exception_t from localparam to param in cva6.sv.
Add parameters accelerator_req_t, accelerator_resp_t, acc_mmu_req_t, and acc_mmu_resp_t to cva6.sv.
Replace the fall-through register with a spill register in acc_dispatcher to decouple timing with the accelerator.
Decrease cache sizes in cv64a6_imafdcv_sv39_config_pkg.
Modify Bender.yml package name from ariane to cva6.
Add harmless code to prevent synthesizer tool from crashing when compiling csr_regfile.
* Collateral changes:
Fixes:
Guard some X-IF code lines with correct parameter in cva6.sv.
Parametrize the tracer interface with NrCommitPorts.
Add missing local dependencies to Bender.yml.
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Add support for Superscalar with ZCMP, ZCMT and CVXIF.
ZCMP decoder, ZCMT decoder and CVXIF interface driver are using port 0.
Standard RVC and 32 bits instruction can take port 0 or 1.
* RVFI Tracer : Update tracer to support interrupts
* Randomize sv_seed by default
* Change pc64 to pc
* Fixes
* cva6.py : add the capability to create a log for sv_seed
* Tracer : keep pc64 64 targets failed
* Fix UVM seed for performance tests
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Co-authored-by: André Sintzoff <61976467+ASintzoff@users.noreply.github.com>
Use CVA6Cfg.DebugEn in an outer test instead of in inner tests
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
is_rvc is redundant with riscv::OpcodeC1, riscv::OpcodeC2
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
