bht2lvl containts a coding pattern that is not supported in Verilator, despite being legal
Unsupported: Delayed assignment to array inside for loops (non-delayed is ok - see docs)
This issue is not always triggered, as it popped up for cv64 but not for cv32.
Fix TLB bug in the MMU when H-Mode is active:
TLB: correct a race condition in lsu_gpaddr_o in which only the highest PPN were checked for match, which may result in invalid translation
Also:
improve coding style / comments of cva6_tlb.sv
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Break-down of #2933 : PTW changes only:
walks on intermediate nodes during G-translation do no generate faults if R/D/X bits is not set and request is a store (fixes [BUG] Wrong permission check walking HGATP #2910)
walks on intermediate nodes during G-translation do no generate faults if X bits is not set and request is an execute
Code style:
gather requests to the TLB in a single process instead of scattered signals
add more comments
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
In commit 92b2d0b ("fix fpga bootrom makefile") we should
have tested $(CC) to be not cc if we where not to set the
standard CC and OBJCOPY files.
This should fix building the bootrom and allow overriding
the CC/OBJCOPY when wanted.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
This follows PRs from @ibooga generated by Claude Code that spam the reviewers.
We need to find a technical solution to instruct language modes or AI coding assistants not to submit PRs.
In the meantime, the rule is written in CONTRIBUTING.md.
The prints after the command invocation makes it easier to work
out what went wrong if you get errors in the command, which end
up being done silently.
For testing, it is useful to be able to control where the CC and
OBJCOPY commands are coming from.
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Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
A couple simple changes which adds a caveat to the README about #2535 and removes some unnecessary hard coded paths which makes development easier on platforms such as Nix
Prior to this change, the MMU only captured LSU misalignment faults when
Hypervisor extensions (RVH) were enabled. If RVH was disabled, misaligned
loads/stores would silently bypass exception handling, violating the
RISC-V privilege spec. This patch moves the [misaligned_ex_q] update
outside the (RVH) guard so that misaligned exceptions are always registered
and prioritized over translation.
Fixes rv32mi-ma_addr & rv32i-I-MISALIGN_LDST_01 tests.
Fix fence.i synchronization issue with HPDCache write-back Data
Add [halt_frontend_o] signal to stall instruction fetch during fence.i
Introduce [fence_i_active] state to track ICache+DCache flush progress
Gate ICache requests and NPC updates when fence.i is active
Resolves stale instruction fetch in self-modifying code scenarios (riscv-tests/rv32ui/fence_i)
Enables Linux boot with HPDCache write-back data by ensuring ICache/DCache coherency
Note: This was not seen with [std_dcache] in standard [fence_i] tests, since it normally finishes write‑back before the ICache flush completes. However, for large self‑modifying code regions, the write‑back can lag behind the ICache flush, leading to stale instruction fetches even with [std_dcache].
Problem:
When executing self-modifying code or booting Linux with a write-back D$, fence.i flushes the ICache but allows the frontend to fetch new instructions before the DCache flush completes. This causes the core to execute stale instructions from the ICache that were modified in the DCache (Dirty data may not be written back because the DCache is still flushing).
Root Cause:
The frontend resumes fetching immediately after ICache flush, even if the DCache is still flushing.
NPC (Next PC) continues advancing after ICache flush, leading to incorrect instruction fetch.
Solution:
Introduce halt_frontend_o signal to freeze frontend during fence.i.
Add fence_i_active state in controller to track combined ICache+DCache flush.
Gate ICache requests (icache_dreq_o.req) and NPC updates (if_ready) during fence_i_active.
This commit makes two changes to the commit stage:
- It fixes incorrect parenthesis, causing dirty_fp_state_o not to be set
on floating point instructions such as fld.
- It adds a condition for dirty_fp_state_o that only asserts the flag
for floating point instructions that change any FPU registers.
Co-authored-by: Guillaume Chauvon <94678394+Gchauvon@users.noreply.github.com>
Fix port connection width mismatch warning in the instruction tracer when using 32-bit version of the core. As the tracer is hardcoded to 64 bit operands and it could be useful to have the same trace format for both 64 and 32 bit cores, the most convenient solution is to pad the data when needed.
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Use define to constraint function declaration from DPI-C. This was already done in ariane_tb.sv and rvfi_tracer.sv
This prevent an error with xcelium reporting that functions such as read_elf have multiple definitions
* Introduction
This PR adds support for Zbkx, Zkne, Zknd and Zknh extensions in the CVA6 core. It also adds the documentation and tests for these extensions. These changes have been tested with self-written single instruction tests and with the riscv-arch-tests. This PR will complete the Zkn - NIST Algorithm Suite extension.
* Implementation
Zbkx Extension:
Added support for the Zbkx instruction set. It essentially expands the Bitmanip extension with additional instructions useful in cryptography. These instructions are xperm8, xperm4.
Zkne Extension:
Added support for the Zkne instruction set. It essentially adds AES encryption support for scalar cryptography. These instructions are aes32esi, aes32esmi, aes64es, aes64esm, aes64ks1i, aes64ks2.
Zknd Extension:
Added support for the Zknd instruction set. It adds AES decryption support for scalar cryptography. These instructions are aes32dsi, aes32dsmi, aes64ds, aes64dsm, aes64im, aes64ks1i, aes64ks2.
Note:
The aes64ks1i and aes64ks2 instructions are present in both the Zknd and Zkne extensions.
Zknh Extension:
Added support for the Zknh instruction set. It adds the hash function instructions support for scalar cryptography. These instructions are sha256sig0, sha256sig1, sha256sum0, sha256sum1, sha512sig0h, sha512sig0l, sha512sig1h, sha512sig1l, sha512sum0r, sha512sum1r, sha512sig0, sha512sig1, sha512sum0, sha512sum1.
* Modifications
Updated the ALU and decoder to recognize and handle Zbkx instructions. For Zkne, Zknd & Zknh, the decoder will now select the AES unit as functional unit instead of the ALU.
The complete Zkn extension is added under the ZKN bit for ease of use. This configuration will also require the RVB (bitmanip) bit to be set.
Note:
The Zkn extension does not require the use of vectorial fpu.
* AES Functional Unit
A new functional unit was created inside the execute stage that will handle all AES and Hashing instructions (Zkne, Zknd, Zknh).
A new package "aes_pkg" handles all AES functions such as sbox substitution, mix columns, etc.
aes_unit
* Documentation and Reference
The official RISC-V Cryptography Extensions Volume I was followed to ensure alignment with ratification. The relevant documentation for Zbkx, Zkne, Zknd and Zknh instructions was also added.
* Verification
Assembly Tests:
The instructions were tested and verified with the K module of both 32 bit and 64 bit versions of the riscv-arch-tests to ensure proper functionality. These tests check for ISA compliance, edge cases and use assertions to ensure expected behavior.
Currently, cvxif_off_instr_n is assigned to orig_instr[i], with i being
0 or 1 depending on the issue port.
This assigns the original instruction value (which will be propagated,
e.g., into tval in an exception) to the last bit of the instruction on
issue port 0.
This commit assigns it to the full instruction on the corresponding
issue port instead.
Adds support for Trace Interface or Trace Ingress Port (TIP) on CVA6
TIP is Interface between a RISC-V hart and the trace encoder
It generates information about the instruction retired.
The implementation is compliant with the Efficient Trace for RISC-V standard Version 2.0.2(https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0.2/riscv-trace-spec-asciidoc.pdf), specifically:
Chapter 4.1: Instruction Trace Interface Requirements
Chapter 4.2: Instruction Trace Interface
The current implementation supports the following TIP signals: iretire, itype, cause, tval, priv, iaddr, and time. For Instruction Type (itype) encoding, it supports the following: Exception, Interrupt, Exception or interrupt return, Nontaken branch, Taken branch, Uninferable jump.
What I have been able to test so far:
Simulation: Executed C binaries and observed the waveform of TIP.
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Co-authored-by: root <darshak.sheladiya@sysgo.com>
Co-authored-by: CHAUVON Guillaume <guillaume.chauvon@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
This PR introduces a new RAW hazard detection mechanism to eliminate WAW hazards in CVA6 issue stage.
It first checks for hazards in all scoreboard entries in parallel.
Then it filters found hazards before vs after the current issue pointer.
It then finds the index of the last hazard before (resp. after) the issue pointer.
Finally, it gives precedence to a hazard before the issue pointer over the one after the issue pointer.
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Co-authored-by: Junheng Zheng <junheng.zheng@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
This fixes the paths for the CV32A60X-specific documentation (from the cv32a60x branch). Whenever the cv32a60x branch is updated, the documentation will be regenerated by RTD.
This macro is not required and makes the file harder to parse.
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Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Following what was done in branch_unit, I set up a default value for hypervisor exception fields in cvxif_fu.
Should fix issue #2831
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Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
* wait for dashboard generation before commenting PRs with pipeline report link.
* change dashboard link and badge
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
* docs: spec_builder.py: add missing extensions
* docs: fix unpriv manual (opcode map, Zcmop)
* in opcode map, write not used when corresponding extension is disabled
* use correct condition for Zcmop extension
* docs: remove PMP chapter when no PMP
* docs: add tailored RISC-V ISA manual for CV32A60X configuration
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
This PR assigns 0 to tinst by default.
Even though tinst is only used when CVA6Cfg.RVH is enabled, I chose to assign it a default value in all configurations, since the signal is defined for all configurations.
Fixes#2803
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Bring the tests added by #2648 in Gitlab CI:
* Rename PMP tests with generic names
* Add a CV32A60X PMP testlist
* Adapt PMP test script to run the testlist
* Add a CI job running said test script
Verification Plan provided in VP_TOOL for the PMP. The verification plan should be complete, however only a partial set of the tests is available. This is not included in the CI but a bash script is available to run the test.
Changing the type of Kgates from int to float in order to add more granularity on the report (usefull when the difference is under 1k Gates)
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
