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82 lines
1.9 KiB
ReStructuredText
82 lines
1.9 KiB
ReStructuredText
..
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Copyright (c) 2023 OpenHW Group
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Copyright (c) 2023 Thales
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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.. Level 1
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=======
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Level 2
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-------
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Level 3
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~~~~~~~
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Level 4
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^^^^^^^
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.. _cva6_interfaces:
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Interfaces
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==========
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AXI Interface
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-------------
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The AXI interface is described in a separate chapter.
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*Applicability to configurations:*
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.. csv-table::
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:widths: auto
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:align: left
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:header: "Configuration", "Implementation"
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"CV32A60AX", "AXI implemented"
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"CV32A60X", "AXI implemented"
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"CV64A6_MMU", "AXI implemented"
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Debug Interface
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---------------
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The team is looking for a contributor for this section.
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We can likely reuse an E4 DVplan.
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Remember: the debug module (DTM) is not in the scope, so we focus on the debug interrupt.
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How to use the interface (HW/SW). We can refer to RISC-V specifications.
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If the section is too heavy, promote it to a separate chapter.
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*Applicability to configurations:*
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.. csv-table::
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:widths: auto
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:align: left
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:header: "Configuration", "Implementation"
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"CV32A60AX", "Debug interface implemented"
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"CV32A60X", "No debug interface"
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"CV64A6_MMU", "Debug interface implemented"
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Interrupt Interface
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-------------------
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The team is looking for a contributor for this section.
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We can likely reuse an E4 DVplan.
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How to use the interface (HW/SW). We can refer to RISC-V specifications.
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If the section is too heavy, promote it to a separate chapter.
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*The interrupt interface is applicable to all configurations.*
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TRI Interface
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-------------
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The TRI interface is exclusive of the AXI interface.
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For more information, refer to OpenPiton documents.
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*Applicability to configurations:*
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.. csv-table::
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:widths: auto
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:align: left
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:header: "Configuration", "Implementation"
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"CV32A60AX", "No TRI interface"
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"CV32A60X", "No TRI interface"
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"CV64A6_MMU", "No TRI interface"
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