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44 lines
1.9 KiB
Markdown
44 lines
1.9 KiB
Markdown
# CVA6: Verification Environment for the CVA6 CORE-V processor core
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- [Directories](#directories)
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- [Prerequisites](#prerequisites)
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- [Test execution](#test-execution)
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- [Verification plan](#verification-plan)
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- [Environment variables](#environment-variables)
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- [32-bit configuration](#32-bit-configuration)
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## Directories:
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- **bsp**: board support package for test-programs compiled/assembled/linked for the CVA6.
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This BSP is used by both `core` testbench and `uvmt_cva6` UVM verification environment.
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- **regress**: scripts to install tools, test suites, CVA6 code and to execute tests
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- **sim**: simulation environment (e.g. riscv-dv)
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- **tb**: testbench module instancing the core
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- **tests**: source of test cases and test lists
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There are README files in each directory with additional information.
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## Verification plan
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Verification plan is available only for vcs tool and located in sim/cva6.hvp, it's used within a modifier to filter out only needed features. Example sim/modifier_embedded.hvp for embedded config.
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To generate the coverage database user should run at least a test or regression with coverage enabled by setting:
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- `export cov=1`
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To view or edit verification plan use command:
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- `cd sim`
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- `verdi -cov -covdir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp`
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To generate verification plan report in html format use command:
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- `cd sim`
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- `urg -hvp_proj cva6_embedded -group instcov_for_score -hvp_attributes description -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp`
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## Environment variables
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Other environment variables can be set to overload default values
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provided in the different scripts.
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The default values are:
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- `DV_TARGET`: `cv64a6_imafdc_sv39`
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- `DV_SIMULATORS`: `veri-testharness,spike`
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- `DV_TESTLISTS`: `../tests/testlist_riscv-tests-$DV_TARGET-p.yaml
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../tests/testlist_riscv-tests-$DV_TARGET-v.yaml`
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- `DV_OPTS`: no default value
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