Florian Zaruba db0ba0d6e1 Mock UVM store queue interface		2017-05-29 18:47:58 +02:00
..
util	Add very preliminary instruction tracer	2017-05-16 18:34:30 +02:00
alu.sv	ALU cleanup remove branch logic	2017-05-16 11:37:26 +02:00
ariane.sv	[WIP] Re-worked LSU dcache interface	2017-05-29 14:29:45 +02:00
branch_unit.sv	Add new branch unit	2017-05-21 11:03:36 +02:00
btb.sv	✅ Add fetch fifo testbench stub	2017-05-14 20:11:39 +02:00
commit_stage.sv	🐛 Fixes in instruction aligner	2017-05-16 15:19:42 +02:00
compressed_decoder.sv	Restructure IF stage	2017-05-15 18:36:31 +02:00
controller.sv	Fix issue #31	2017-05-12 19:21:42 +02:00
csr_buffer.sv	👾 Fix synthesis warnings	2017-05-07 22:52:25 +02:00
csr_regfile.sv	Remove simulation warnings	2017-05-08 12:41:20 +02:00
dcache_arbiter.sv	Mock UVM store queue interface	2017-05-29 18:47:58 +02:00
decoder.sv	🐛 Fixes in instruction aligner	2017-05-16 15:19:42 +02:00
ex_stage.sv	[WIP] Re-worked LSU dcache interface	2017-05-29 14:29:45 +02:00
fetch_fifo.sv	Clean LSU from un-timeable logic	2017-05-18 11:07:22 +02:00
fifo.sv	Add core memory stub	2017-05-23 10:20:52 +02:00
id_stage.sv	Only resolve branch if it was indeed a branch inst	2017-05-16 12:35:30 +02:00
if_stage.sv	🎨 Remove pre-fetch buffer, module was redundant	2017-05-27 19:12:13 +02:00
issue_read_operands.sv	Fix issue #31	2017-05-12 19:21:42 +02:00
load_unit.sv	Add request side of D$ interface	2017-05-29 16:15:11 +02:00
lsu.sv	[WIP] Re-worked LSU dcache interface	2017-05-29 14:29:45 +02:00
lsu_arbiter.sv	Implement exception handling in LSU	2017-05-22 19:06:40 +02:00
mmu.sv	[WIP] Re-worked LSU dcache interface	2017-05-29 14:29:45 +02:00
mult.sv	🎨 Reorganized folder structure	2017-05-02 11:36:07 +02:00
pcgen.sv	ALU cleanup remove branch logic	2017-05-16 11:37:26 +02:00
ptw.sv	First test run of LSU	2017-05-18 17:39:06 +02:00
regfile.sv	🎨 Reorganized folder structure	2017-05-02 11:36:07 +02:00
regfile_ff.sv	🎨 Reorganized folder structure	2017-05-02 11:36:07 +02:00
scoreboard.sv	Put flush to sequential process	2017-05-12 14:54:21 +02:00
store_queue.sv	[WIP] Re-worked LSU dcache interface	2017-05-29 14:29:45 +02:00
store_unit.sv	[WIP] Re-worked LSU dcache interface	2017-05-29 14:29:45 +02:00
tlb.sv	Clean LSU from un-timeable logic	2017-05-18 11:07:22 +02:00