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André Sintzoff 21506e4c66
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docs: add CV32A60X configuration in RISC-V ISA manual (#2838) 
* docs: spec_builder.py: add missing extensions
* docs: fix unpriv manual (opcode map, Zcmop)
* in opcode map, write not used when corresponding extension is disabled
* use correct condition for Zcmop extension
* docs: remove PMP chapter when no PMP
* docs: add tailored RISC-V ISA manual for CV32A60X configuration

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-03-19 00:03:00 +01:00
..
classes.py Design Document, add ID_STAGE description (#1832) 2024-02-16 16:17:46 +01:00
define_blacklist.py User config generator becomes a Python tool to work with configs (#2003) 2024-04-04 15:56:29 +02:00
parameters_extractor.py doc: keep documentation in sync with the code (#2558) 2024-10-25 12:27:09 +02:00
spec_builder.py docs: add CV32A60X configuration in RISC-V ISA manual (#2838) 2025-03-19 00:03:00 +01:00