Ariane RISC-V CPU

For detailed documentation refer to the online documentation (Login: zarubaf Password: zaruba).

Getting Started

Go and get the RISC-V tools.

Checkout the repository and initialize all submodules

git checkout git@iis-git.ee.ethz.ch:floce/ariane.git
git submodule update --init --recursive

Build Ariane by using the Makefile:

make build

Start the simulation using Modelsim:

make sim

To specify the test to run use (e.g.: you want to run rv64ui-p-sraw inside the riscv-tests isa folder:

make sim riscv-test=rv64ui-p-sraw

If you call simc instead of sim it will run without the GUI.

Or start any of the unit tests by:

make dcache_arbiter

Contributing

Check out the contribution guide

Test Overview

Test Name	P/F/U	Test Name	P/F/U	Test Name	P/F/U
add	✅	lb	✅	sll	✅
addi	✅	lbu	✅	slli	✅
addiw	✅	ld	✅	slliw	✅
addw	✅	lh	✅	sllw	✅
and	✅	lhu	✅	slt	✅
andi	✅	lui	✅	slti	✅
auipc	✅	lw	✅	sltiu	✅
beq	✅	lwu	✅	sltu	✅
bge	✅	or	✅	sra	✅
bgeu	✅	ori	✅	srai	✅
blt	✅	sb	⬜	sraiw	✅
bltu	✅	sd	⬜	sraw	✅
bne	✅	sh	⬜	srl	✅
sub	✅	simple	✅	srli	✅
subw	✅	jal	✅	srliw	✅
sw	⬜	jalr	✅	srlw	✅
xor	✅
xori	✅