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cache_subsystem
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Break timing loop in axi adapter arbiter of WB cache (#1761)
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2024-01-15 15:18:11 +01:00 |
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cvxif_example
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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frontend
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Code coverage: condition RTL With parameters (#1703)
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2023-12-13 07:52:47 +01:00 |
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include
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csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)
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2024-01-15 14:34:25 +01:00 |
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mmu_sv32
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verible-verilog-format: apply it on core directory (#1668)
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2023-12-04 11:16:35 +00:00 |
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mmu_sv39
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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pmp
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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acc_dispatcher.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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alu.sv
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csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)
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2024-01-15 14:34:25 +01:00 |
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amo_buffer.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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ariane_regfile.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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ariane_regfile_ff.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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ariane_regfile_fpga.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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axi_shim.sv
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Code coverage: condition RTL With parameters (#1703)
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2023-12-13 07:52:47 +01:00 |
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branch_unit.sv
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fix: exception on misaligned branch if no RVC (#1719)
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2023-12-19 10:03:11 +01:00 |
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commit_stage.sv
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Modify coding style to improve CC (#1642)
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2023-11-21 19:04:55 +01:00 |
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compressed_decoder.sv
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csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)
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2024-01-15 14:34:25 +01:00 |
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controller.sv
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Modify coding style to improve CC (#1642)
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2023-11-21 19:04:55 +01:00 |
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csr_buffer.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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csr_regfile.sv
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csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)
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2024-01-15 14:34:25 +01:00 |
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cva6.sv
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csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)
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2024-01-15 14:34:25 +01:00 |
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cva6_accel_first_pass_decoder_stub.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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cvxif_fu.sv
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verible-verilog-format: apply it on core directory (#1668)
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2023-12-04 11:16:35 +00:00 |
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decoder.sv
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csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)
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2024-01-15 14:34:25 +01:00 |
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ex_stage.sv
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verible-verilog-format: apply it on core directory (#1668)
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2023-12-04 11:16:35 +00:00 |
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Flist.cva6
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Update version of the HPDcache submodule (#1673)
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2023-12-06 09:25:31 +01:00 |
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Flist.cva6_gate
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Parametrize debug module (#1382)
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2023-09-13 16:22:24 +02:00 |
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fpu_wrap.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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id_stage.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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instr_realign.sv
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verible-verilog-format: apply it on core directory (#1668)
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2023-12-04 11:16:35 +00:00 |
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issue_read_operands.sv
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Code coverage: condition RTL With parameters (#1703)
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2023-12-13 07:52:47 +01:00 |
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issue_stage.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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load_store_unit.sv
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Code_coverage: condition RTL with the IS_XLEN64 parameter (#1666)
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2023-12-04 22:21:48 +01:00 |
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load_unit.sv
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Code coverage: condition RTL With parameters (#1703)
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2023-12-13 07:52:47 +01:00 |
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lsu_bypass.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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mult.sv
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Code coverage: condition RTL With parameters (#1703)
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2023-12-13 07:52:47 +01:00 |
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multiplier.sv
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csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)
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2024-01-15 14:34:25 +01:00 |
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perf_counters.sv
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Fix event tracing on more commit ports. (#1665)
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2023-12-06 11:49:32 +01:00 |
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scoreboard.sv
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Code coverage: condition RTL With parameters (#1703)
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2023-12-13 07:52:47 +01:00 |
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serdiv.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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store_buffer.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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store_unit.sv
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Code coverage: condition RTL With parameters (#1703)
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2023-12-13 07:52:47 +01:00 |
