André Sintzoff 3afe870d78 csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)		2024-01-15 14:34:25 +01:00
..
axi_mem_if@b494701501	Add user field between memory and caches (#857)	2022-04-20 12:47:07 +02:00
bootrom	Remove DROMAJO (#1204)	2023-04-24 23:05:53 +02:00
clint	ariane_testharness/ariane_xilinx: Fix AXI ID width (#813)	2022-02-06 11:17:21 +01:00
fpga	csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)	2024-01-15 14:34:25 +01:00
openpiton	Define AXI as cva6 input parameters (#1315)	2023-07-24 10:34:30 +02:00
register_interface@73de8e51b7	Bump register interface to v0.3.1 (#819)	2022-02-10 14:19:12 +01:00
riscv-dbg@e19d69efe7	riscv-dbg: update to v0.4.1 to support 32-bit CVA6 debug (#746)	2021-10-01 17:02:34 +02:00
rv_plic@5b5c5a4c1c	Bump register interface to v0.3.1 (#819)	2022-02-10 14:19:12 +01:00
src	Merge CVA6Cfg and ArianeCfg (#1321)	2023-09-28 11:41:38 +02:00
tb	Check that loaded elf segment does not overlap on last loaded address (#1755)	2024-01-11 11:37:00 +01:00