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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
340 commits 16 branches 13 tags 288 MiB
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Florian Zaruba 4d7b9a1b75 [WIP] Implement exception handling
2017-05-31 23:17:07 +02:00
docs 📝 Slightly update LSU timing diagrams 2017-05-29 16:41:08 +02:00
include [WIP] Implement exception handling 2017-05-31 23:17:07 +02:00
src [WIP] Implement exception handling 2017-05-31 23:17:07 +02:00
tb [WIP] Implement exception handling 2017-05-31 23:17:07 +02:00
test Add decode, issue, flush and commit logic to tracer 2017-05-30 15:44:01 +02:00
uvm-scaffold@d59b8d6a51 Instantiated dcache interface for store queue test 2017-05-29 19:09:14 +02:00
.gitignore Adapt dcache arbiter testbench using new dcache if 2017-05-29 15:51:31 +02:00
.gitlab-ci.yml Fix .gitlab-ci.yml 2017-05-29 16:46:19 +02:00
.gitmodules Add UVM scaffolding submodule 2017-04-30 18:23:56 +02:00
CHANGELOG 📝 Add CHANGELOG to gitlab, manually created 2017-04-21 11:09:30 +02:00
CONTRIBUTING.md Fix issue #8 2017-05-05 11:06:37 +02:00
LICENSE 📝 Add license 2017-04-21 11:11:40 +02:00
Makefile Re-add test target to Makefile 2017-05-29 19:34:12 +02:00
mkdocs.yml 📝 Add timing diagram for memory interface 2017-05-07 13:09:05 +02:00
README.md 📝 Added contribution guide 2017-04-20 23:06:47 +02:00

README.md

build status coverage report

Ariane RISC-V CPU

For detailed documentation refer to the online documentation (Login: zarubaf Password: zaruba).

Contributing

Check out the contribution guide