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cva6/core
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Steffen Persvold 75807530f2
Add support for "high" counter CSRs in 32-bit mode (#847) 
* Add support for "high" counter CSRs in 32-bit mode

In 32bit mode MCYCLEH, MINSTRETH, CYCLEH, TIMEH and INSTRETH are
used to return the most significant 32-bit value of the counters
which are now always 64-bit wide.

Signed-off-by: Steffen Persvold <spersvold@gmail.com>

* Enable writing of MCYCLEH and MINSTRETH CSRs

Signed-off-by: Steffen Persvold <spersvold@gmail.com>
2022-05-12 10:46:40 +02:00
..
cache_subsystem wt_dcache_wbuffer.sv: remove init for user (#870) 2022-04-29 14:21:47 +02:00
cvxif_example cvxif: Flist modifications for core-v-verif and synthesis (#781) 2021-12-29 14:58:54 +01:00
example_tb Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
fpu@79f75e0a0f Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
frontend Make C extension optional (#833) 2022-03-25 16:01:17 +01:00
include Add support for "high" counter CSRs in 32-bit mode (#847) 2022-05-12 10:46:40 +02:00
mmu_sv32 Dev dcache 32bits (#849) 2022-04-11 14:54:09 +02:00
mmu_sv39 Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
pmp Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
alu.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
amo_buffer.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
ariane.sv Add cv-x-interface (#780) 2021-12-22 12:31:56 +01:00
ariane_regfile.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
ariane_regfile_ff.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
axi_adapter.sv 🐛 wb_dcache: Fix unaligned SC return data bug (#838) 2022-03-15 07:33:23 +01:00
axi_shim.sv Add user field between memory and caches (#857) 2022-04-20 12:47:07 +02:00
branch_unit.sv Fix update of the BHT on correct not taken prediction (#754) 2021-10-10 11:06:23 +02:00
commit_stage.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
compressed_decoder.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
controller.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
csr_buffer.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
csr_regfile.sv Add support for "high" counter CSRs in 32-bit mode (#847) 2022-05-12 10:46:40 +02:00
cva6.sv cva6.sv: change RVFI exception signal (#873) 2022-05-12 08:46:37 +02:00
cvxif_fu.sv Add cv-x-interface (#780) 2021-12-22 12:31:56 +01:00
decoder.sv decoder.sv: Remove unnecessary assignment (#788) 2022-01-14 15:00:17 +01:00
dromajo_ram.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
ex_stage.sv Add cv-x-interface (#780) 2021-12-22 12:31:56 +01:00
Flist.cv32a6_imac_sv0 Replace SyncDpRam by tc_ram (#861) 2022-04-28 20:13:55 +02:00
Flist.cv32a6_imac_sv32 Replace SyncDpRam by tc_ram (#861) 2022-04-28 20:13:55 +02:00
Flist.cv32a6_imafc_sv32 Replace SyncDpRam by tc_ram (#861) 2022-04-28 20:13:55 +02:00
Flist.cv64a6_imafdc_sv39 Replace SyncDpRam by tc_ram (#861) 2022-04-28 20:13:55 +02:00
Flist.cv64a6_imafdc_sv39_gate Replace SyncDpRam by tc_ram (#861) 2022-04-28 20:13:55 +02:00
fpu_wrap.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
id_stage.sv Make C extension optional (#833) 2022-03-25 16:01:17 +01:00
instr_realign.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
issue_read_operands.sv Add cv-x-interface (#780) 2021-12-22 12:31:56 +01:00
issue_stage.sv Add cv-x-interface (#780) 2021-12-22 12:31:56 +01:00
load_store_unit.sv Dev dcache 32bits (#849) 2022-04-11 14:54:09 +02:00
load_unit.sv Dev dcache 32bits (#849) 2022-04-11 14:54:09 +02:00
mult.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
multiplier.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
perf_counters.sv Fix per counters for second commit port (#751) 2021-10-09 10:19:29 +02:00
re_name.sv Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
scoreboard.sv Fixed issue counter in order to leverage the full scoreboad length (#802) 2022-01-24 19:48:17 +01:00
serdiv.sv Fix erroneous division (fixes #421) (#796) 2022-01-22 08:48:57 +01:00
store_buffer.sv Dev dcache 32bits (#849) 2022-04-11 14:54:09 +02:00
store_unit.sv Dev dcache 32bits (#849) 2022-04-11 14:54:09 +02:00