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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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Florian Zaruba e9df593b07 Adapted Makefile to preliminary TB structure
2017-03-19 00:29:33 +01:00
include Linting alu, fixed some size mismatch issues 2017-03-18 21:45:10 +01:00
tb UVM Alu: Mock implementation for Alu TB 2017-03-19 00:24:56 +01:00
alu.sv Alu: Cleanup and first 64-bit version 2017-03-18 23:28:19 +01:00
ariane.sv Added initial top-level module with mem and debug if 2017-03-18 20:21:58 +01:00
Makefile Adapted Makefile to preliminary TB structure 2017-03-19 00:29:33 +01:00
README.md Added simple register file and README 2017-03-18 19:55:23 +01:00
regfile.sv Made register file 64 bit by default 2017-03-18 19:57:02 +01:00

README.md

Ariane RISC-V CPU

6 stage, out-of-order RISC-V CPU

Regfile

The register file has two read ports and one write port.