cva6/fpga
2018-11-07 17:00:46 +01:00
..
ariane.srcs/sources_1/ip Merge branch 'fpga_dev' of github.com:pulp-platform/ariane into fpga_dev 2018-10-30 17:32:57 +01:00
constraints Merge branch 'fpga_dev' of github.com:pulp-platform/ariane into fpga_dev 2018-10-30 17:32:57 +01:00
scripts Fix PLIC address map and DTS 2018-10-10 17:23:03 +02:00
src Update bootrom 2018-11-07 17:00:46 +01:00
xilinx Clean-up fpga folder 2018-10-29 11:53:21 +01:00
.gitignore Add Xilinx IPs 2018-10-03 14:36:48 +02:00
ariane.cfg Wire-up clint, first debug test passing 2018-09-14 22:05:40 +02:00
Makefile Add Xilinx IPs 2018-10-03 14:36:48 +02:00
mig-genesys-2.ucf Start adding Genesys 2 support 2018-09-26 12:01:30 +02:00