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cva6/config/riscv-config
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Zbigniew Chamski ed89c717f7
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[CV32A65X] Update PMPADDRn spec to make bit 0 ROCST 0. Update config files. (#2651) 
Update CV32A65X-annotated privileged ISA specification to reflect the fact that with PMP granularity 8 and only supported PMP address matching modes being OFF and TOR, bit 0 of the pmpaddr0..pmpaddr7 registers can be safely made read-only zero. Update riscv-config specifications and its generated files accordingly.
2024-12-09 13:22:38 +01:00
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cv32a65x [CV32A65X] Update PMPADDRn spec to make bit 0 ROCST 0. Update config files. (#2651) 2024-12-09 13:22:38 +01:00
Makefile Update riscv-config infra to better match expressivity needs of CV32A65X. (#2193) 2024-06-04 18:12:14 +02:00
README.md Add initial riscv-config input specs, validation harness and YAML outputs for CV32A65X. (#2133) 2024-05-21 07:21:57 +02:00

README.md

File organization

  • Makefile: the makefile needed to regenerate the Yaml files using riscv-config.
  • TARGET: directory holding input and output files for configuration named TARGET (currently only cv32a65x)
    • spec: Directory holding input files
      • isa_spec.yaml: specification of the ISA, including CSRs and privileges (expressed as canonical extension letters)
      • custom_spec.yaml: specification of custom CSRs
      • platform_spec.yaml: specification of platform-level values/properties
    • generated: Directory holding generated files produced by riscv-config from the spec files
      • isa_gen.yaml: ISA definition completed y riscv-config
      • custom_gen.yaml: Custom CSR definitions completed by riscv-config
      • platform_gen.yaml: Platform-specific values/properties completed by riscv-config

Prerequisites

  • Python3 (tested with 3.9 on RedHat Enterprise Linux 8)

Invocation

From any directory, run

make -C <CVA6_top_directory>/config/riscv-config all