github-mirrors/cve2
1
0
Fork 0
mirror of https://github.com/openhwgroup/cve2.git synced 2025-04-22 04:57:25 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Readd ALU flag to EX stage, use it for branch decision

Browse source
This commit is contained in:
Sven Stucki 2015-08-31 13:06:43 +02:00
parent 4015362ee8
commit 2c72b487dc
3 changed files with 11 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

1
alu.sv
View file

@ -31,7 +31,6 @@
module alu
(
// Inputs of the ALU
input logic [`ALU_OP_WIDTH-1:0] operator_i,
input logic [31:0] operand_a_i,
input logic [31:0] operand_b_i,

19
ex_stage.sv
View file

@ -27,9 +27,6 @@
// //
// //
////////////////////////////////////////////////////////////////////////////////
// int = internal signals
// wb = writeback
// sp = special registers
`include "defines.sv"
@ -100,15 +97,16 @@ module ex_stage
// Internal output of the LU
logic [31:0] alu_result;
logic [31:0] alu_result;
logic alu_flag;
logic [31:0] alu_adder_lsu_int; // to LS unit
logic [31:0] alu_adder_lsu_int; // to LS unit
logic [31:0] mult_result;
logic [31:0] mult_result;
assign regfile_alu_we_fw_o = regfile_alu_we_i;
assign regfile_alu_waddr_fw_o = regfile_alu_waddr_i;
assign regfile_alu_we_fw_o = regfile_alu_we_i;
assign regfile_alu_waddr_fw_o = regfile_alu_waddr_i;
always_comb
begin
@ -139,7 +137,7 @@ module ex_stage
assign hwloop_cnt_data_o = hwloop_cnt_i;
// Branch is taken when result[0] == 1'b1
assign branch_decision_o = alu_result[0];
assign branch_decision_o = alu_flag;
assign jump_target_o = alu_operand_c_i;
@ -163,7 +161,8 @@ module ex_stage
.adder_lsu_o ( alu_adder_lsu_int ),
.result_o ( alu_result )
.result_o ( alu_result ),
.flag_o ( alu_flag )
);

4
exc_controller.sv
View file

@ -97,9 +97,9 @@ module exc_controller
// - illegal instruction exception and IIE bit is set
// - IRQ and INTE bit is set and no exception is currently running
// - Debuger requests halt
assign trap_hit_o = trap_insn_i || dbg_flush_pipe_i || dbg_st_en_i || (illegal_insn_i & dbg_dsr_i[`DSR_IIE]) || (irq_present_o & dbg_dsr_i[`DSR_INTE] & (~exc_running_p));
assign trap_hit_o = trap_insn_i || dbg_flush_pipe_i || dbg_st_en_i || (illegal_insn_i && dbg_dsr_i[`DSR_IIE]) || (irq_present_o && dbg_dsr_i[`DSR_INTE] && (~exc_running_p));
assign irq_present_o = (irq_i || irq_nm_i) & irq_enable_i;
assign irq_present_o = (irq_i || irq_nm_i) && irq_enable_i;
// Decoder for exc_reason signal
// this signal tells the exception controller which is the exception